JPH07121602A - Layout verification device and verification method for semiconductor integrated circuit - Google Patents

Abstract

(57) [Abstract] [PROBLEMS] To provide a layout verification device and verification method for a semiconductor integrated circuit, which can improve the efficiency of the design of the semiconductor integrated circuit and shorten the design period as much as possible. [Structure] Before designing the layout of a semiconductor integrated circuit, whether or not the plurality of types of cells used are adjacent to each other and whether or not they are compatible with each other is determined by determining whether or not the cells are mutually left and right for all combinations of each cell. By verifying the case where the cells are replaced with each other and the case where one of the cells is replaced with the other on the left and right, the placement and wiring of each cell on the board can be quickly determined, and the error caused by the placement can be corrected. The design period can be shortened because there is no need for designing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout verifying apparatus and a verifying method for verifying whether cells used in a semiconductor integrated circuit are compatible with each other.

[0002]

2. Description of the Related Art Conventionally, for designing a semiconductor integrated circuit, there is a method of laying out by using, for example, a plurality of types of logic cells in CAD or the like according to the application. This method
First, a cell to be used is designed or data of a cell designed in advance is selected from the library. And, for each cell, do not exert any other physical, electrical, or thermal effects,
That is, it verifies that the so-called design rule is met.
Next, after placing each cell on the substrate manually or automatically on the screen, it is verified whether adjacent cells do not affect each other, and if they affect, placement of each cell on the substrate, Repeat the work of changing the wiring and placing each cell on the board on the screen again, and the work of verifying the influence of adjacent cells, and in some cases, change the design of the cell to be used and comprehensively design rules. If it conforms to the above, the cells to be used and their arrangement were decided.

However, as described above, after actually arranging and wiring each cell on the substrate and then verifying whether the design rule is satisfied, re-arrangement and re-wiring when an error occurs near the boundary between the cells However, there is a problem that the design period of the semiconductor integrated circuit becomes long because of the difficulty.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and its main purpose is to improve the efficiency of the design of a semiconductor integrated circuit and to extend the design period. It is an object of the present invention to provide a layout verification device and a verification method for a semiconductor integrated circuit, which can be shortened as a whole.

[0005]

According to the present invention, the above-described object is to determine whether or not a plurality of types of cells used in a semiconductor integrated circuit to be created are compatible with each other. A layout verification device for a semiconductor integrated circuit for verification before design, comprising means for storing layout data of the plurality of types of cells, and actually extracting two data from the stored layout data of each cell. And a means for verifying whether or not they are compatible with each other when the cells are arranged adjacent to each other, wherein the verification means performs the verification for all combinations of the cells. And when two cell layout data are extracted from the layout data of the plurality of types of cells and the cells are actually arranged adjacent to each other, It is achieved by providing a layout verification method characterized by verifying whether the case before the design of the semiconductor integrated circuit for all combinations of the respective cells. In particular, it is preferable to verify whether or not they are compatible with each other when the cells are replaced with each other on the left and right, and when the cells are replaced with each other on the left and right with one of the cells turned upside down.

[0006]

As described above, before the layout is performed using the plurality of cells of the semiconductor integrated circuit, it is determined whether or not the plurality of types of cells to be used are arranged adjacent to each other and whether or not they are compatible with each other. Promptly determine the placement and wiring of each cell on the substrate by verifying the case where the cells are swapped to the left and right with respect to all combinations, and the case where one of the cells is flipped to the left and right. be able to.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of a semiconductor integrated circuit designing apparatus incorporating a layout verification apparatus to which the present invention is applied. In this embodiment, a design device for designing an LSI using standard cells will be described. This design apparatus includes a processing unit 1 that actually performs layout processing and the like, a storage unit 2 that stores layout data of various standard cells and layout data of various components.
It has a display 3, a keyboard 4 and a pointing device 5 as an interface with the operator. Here, the processing unit 1 is provided with a verification processing unit 1a as a verification means for performing a verification process described later.

FIG. 2 is a flow chart for explaining the main part of the verification process in this embodiment. Incidentally, each standard cell used in the LSI to be designed is selected before executing this flow, and the selected standard cell is not arranged on the substrate.

First, of the standard cells stored in the storage unit 2 in step 1, an identification number is assigned to each standard cell used in the LSI to be designed (FIG. 3). Select one or two types of cells from the assigned standard cells.
Then, in Steps 3 to 6, the layout verification is performed to determine whether the selected cells are arranged adjacent to each other and the arrangement satisfies the design rule. Verification processing unit 1 when left and right are replaced with each other
a. Next, in step 7, it is determined whether or not the above verification has been performed for all combinations of standard cells used in the LSI to be designed. If the above verification has not been performed for all combinations, the process returns to step 2,
If yes, this routine ends. Further, FIG. 4 schematically shows a combination of arrangements (4 types) when the selected cells are switched to the left and right and when the cells are switched to the left and right with one of the cells turned upside down.

After performing the above verification on all combinations of standard cells used in the LSI, if a combination not shown in the drawing, which does not satisfy the design rule, is found, the display 3 indicates that. The message is displayed, and the operator is instructed as to whether to replace the cell to be used, change the design, or add a condition at the time of arranging the cell. Then, the processes of steps 1 to 7 are performed again. If a combination that does not satisfy the design rule is not found, the processing unit 1 performs the placement process of each cell on the substrate.

[0012]

As is apparent from the above description, according to the layout verification apparatus and verification method for a semiconductor integrated circuit of the present invention, a plurality of types of cells used before the layout design of the semiconductor integrated circuit are performed. If the cells are arranged adjacent to each other, whether or not they match each other is verified for all combinations of each cell when the cells are interchanged left and right with each other and when one of the cells is interchanged left and right with each other turned over. By arranging them in advance, it is possible to quickly determine the placement and wiring of each cell on the substrate and eliminate the need for redesigning due to placement errors, thus reducing the design period.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a semiconductor integrated circuit designing apparatus to which the present invention is applied.

FIG. 2 is a flowchart showing a layout verification processing procedure performed by the design apparatus of FIG.

3 is an explanatory diagram showing a state in which identification numbers 1 to n are assigned to standard cells used in an LSI designed by the designing apparatus of FIG. 1. FIG.

FIG. 4 is an explanatory diagram showing combinations of adjacent states of standard cells with identification numbers 1 and 2.

[Explanation of symbols]

 1 Processing Unit 1a Verification Processing Unit 2 Storage Unit 3 Display 4 Keyboard 5 Pointing Device

Claims (4)

[Claims] 1. A layout verification device for a semiconductor integrated circuit, for verifying whether or not a plurality of types of cells used in a semiconductor integrated circuit to be created are arranged, before designing the semiconductor integrated circuit. And a means for storing the layout data of the plurality of types of cells, and mutually matching when two data are extracted from the stored layout data of each cell and the cells are actually arranged adjacent to each other. A layout verifying device, comprising: means for verifying whether or not to perform the verification, wherein the verification means verifies all combinations of the cells. 2. The verification means verifies whether or not they are compatible with each other when the cells are interchanged left and right with each other, and when the cells are interchanged left and right with one of the cells turned upside down. The layout verification device according to claim 1. 3. A layout verification method for a semiconductor integrated circuit for verifying whether or not they are compatible with each other when a plurality of types of cells used in a semiconductor integrated circuit to be created are arranged before designing the semiconductor integrated circuit. It is to be noted that when two cell layout data are extracted from the layout data of the plurality of types of cells and the cells are actually arranged adjacent to each other, whether or not they are compatible with each other is determined based on all combinations of the respective cells. The method for verifying a layout is characterized in that the verification is performed before designing the semiconductor integrated circuit. 4. The verification step comprises a step of verifying whether or not they are compatible with each other when the cells are exchanged with each other on the left and right sides and when one of the cells is exchanged with the left side on the other side. 4. The method according to claim 3,
Layout verification method described in.