JPH07122604A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Abstract] [Objective] While enabling electrical inspection of a semiconductor integrated circuit device (semiconductor chip), suitable metal wire bonding is possible to realize other pins. [Structure] First input / output terminals 2 having minute terminal dimensions are arranged at a minute pitch dimension in the peripheral portion of a semiconductor chip 1, and second input / output terminals 3 are arranged in a region inside the first input / output terminals 2 more than the first input / output terminals. The input and output terminals 2 and 3 are individually arranged to be electrically connected by the connection portion 4 while being arranged with a large terminal size and pitch size. By bonding a metal wire to the second input / output terminal 3, it is possible to secure positional accuracy and realize highly reliable bonding. Further, by arranging the first input / output terminals 2 in a row in the peripheral portion of the semiconductor chip, the probes of the inspection device can be brought into contact with each other and the inspection can be facilitated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device suitable for increasing the number of pins.

[0002]

2. Description of the Related Art In a conventional semiconductor integrated circuit device, as shown in FIG. 5, an internal element region 223 is formed at the center,
A plurality of input / output terminals 22 are arranged in the peripheral portion of the semiconductor chip 21 having a rectangular outer shape. Since the input / output terminal 22 is connected to a metal wire such as aluminum or gold having a diameter of 30 μφ as an electrode pad, these metal wires can be bonded and a short circuit due to interference of adjacent metal wires is prevented. In addition, it is required that the size is a predetermined size or more and the pitch size is a predetermined size or more. For example, in the case of a semiconductor integrated circuit device having a 15 mm square chip with about 500 pins, each input / output terminal is 100 to 120 μm square.
They are formed to have a size of about 110 to 130 μm and arranged in an array.

With such a configuration of the input / output terminals, when the semiconductor chip is required to have an extremely large number of pins of 800 to 2000 pins in accordance with the high integration of the semiconductor integrated circuit device in recent years, the input / output terminals are required. 22 pitch size 6
It is necessary to reduce the thickness to about 0 to 70 μm. However, such a fine pitch dimension is disadvantageous in securing the positional accuracy at the time of bonding of the above-described metal wire, makes reliable bonding difficult, and makes it difficult to prevent a short circuit between adjacent metal wires. Becomes difficult to realize.

For this reason, conventionally, as shown in FIG. 6, there has been proposed a semiconductor chip 31 in which the input / output terminals 32 are arranged on substantially the entire surface including the internal element region 32 (Japanese Patent Laid-Open No. Sho 6-62).
4-67951). In this semiconductor integrated circuit device, by arranging a large number of input / output terminals 32 in a matrix on substantially the entire surface of the semiconductor chip 31, the terminal size and pitch size of each input / output terminal 32 are secured to a predetermined value or more, and the above-mentioned bonding is performed. In this case, it is possible to solve the problem at the time of, and enhance the effect of preventing a short circuit between adjacent metal wires.

[0005]

However, when the input / output terminals 32 are arranged on substantially the entire surface of the semiconductor chip 31, the inspection probe is brought into contact with the input / output terminals in order to electrically inspect the semiconductor chip 31. When conducting the energization inspection by using the existing probe array inspection device, it becomes impossible to use the existing probe array inspection device, and it is necessary to prepare a special probe array inspection device. Further, usually, a large number of probes of the inspection device are arranged in the circumferential direction, but in order to apply to the semiconductor chip of FIG. 6, it is necessary to arrange these probes in a matrix. There is a problem that the structure becomes complicated and the cost of the inspection device is increased. An object of the present invention is to provide a semiconductor integrated circuit device that enables electrical inspection of a semiconductor chip by using a normal inspection device, and solves a problem at the time of bonding a metal wire and enables other pins. To do.

[0006]

SUMMARY OF THE INVENTION A semiconductor integrated circuit according to the present invention comprises a plurality of first input / output terminals each having a minute terminal size and arranged at a peripheral portion of a semiconductor chip with a minute pitch size, and a first input / output terminal. A plurality of second input / output terminals arranged in a region inside the first input / output terminals with terminal dimensions and pitch dimensions larger than those of the first input / output terminals, and electrically connected to the first input / output terminals, respectively. And an input / output terminal of. For example, at least a part of the first input / output terminal, at least a part of the second input / output terminal, and a connection portion for electrically connecting these input / output terminals to each other are integrally formed by one conductive film. . Further, the materials of the surface portions of the first input / output terminal and the second input / output terminal may be different.

[0007]

[Operation] By bonding a metal wire to the second input / output terminal having a large terminal size and pitch,
Positioning accuracy can be secured and highly reliable bonding can be realized, and thus mutual short circuit of metal wires can be prevented. Further, by arranging the first input / output terminals having a small terminal size and a small pitch size in a row in the peripheral portion of the semiconductor chip, the probes of the inspection device can be brought into contact with each other, and the inspection can be facilitated.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing an embodiment of the present invention, in which a large number of first input / output terminals 2 are arranged in a row along the peripheral edge of the semiconductor chip 1 in the peripheral portion of the semiconductor chip 1 formed in a rectangular shape. Has been done. In addition, inside the first input / output terminal 2,
The same number of second input / output terminals 3 are arranged in two rows along the arrangement direction of the first input / output terminals 2. And
The first input / output terminal 2 and the second input / output terminal 3 are in close proximity to each other in a one-to-one correspondence, and are electrically connected to each other by the connecting portion 4.

FIG. 2 is an enlarged view of portion A of FIG.
(A) is a top view and (b) is the BB line expanded sectional view. In the element region of the main surface portion of the silicon substrate 10 that constitutes the semiconductor chip 1, required internal elements are formed by using a technique such as lithography, ion implantation, and etching, and the internal element region 11 including these elements is formed. ing. Then, a multilayer wiring layer 12 in which an insulating film and a conductive film formed in a desired pattern are laminated is formed thereon, and the respective elements in the internal element region 11 are electrically connected to each other to obtain a desired semiconductor integrated circuit. Are configured. Then, this multilayer wiring layer 12
An aluminum film is patterned on the uppermost layer to form the terminal wiring layer 13.

The terminal wiring layer 13 has a portion corresponding to the first input / output terminal 2, a portion corresponding to the second input / output terminal 3, and these first and second input / output terminals 2 and 3. And the connecting portion 4 for electrically connecting the two are integrally formed, and the planar shape thereof is formed so as to be close to a so-called dog bone. Then, the cover insulating film 14 is formed on the terminal wiring layer 13.
And in the cover insulating film 14, windows 14a and 14a are formed in the portions corresponding to the first and second input / output terminals, respectively.
14b is opened. Due to the opened window 14a, the first input / output terminal 2 is formed on a part of the exposed terminal wiring layer 13. The second input / output terminal 3 is formed by selectively forming a titanium / tungsten film 15 and a gold film 16 in a region including the other portion of the terminal wiring layer 13 exposed by the opened window 14b. Is formed. In manufacturing the second input / output terminal 3, after the window 14b is opened in the cover insulating film 14, the titanium / tungsten film 15 and the gold film 16 are formed on the upper surface of the cover insulating film 13, and thereafter, It can be formed by selective etching using a photoresist or the like as a mask.

At this time, the first input / output terminals 2 are arranged in one line along the periphery of the semiconductor chip 1, but the length of the connecting portion 4 of the terminal wiring layer 13 is set to long, short, and long cycles. By setting to repeat with, one second arranged inside
The first input / output terminal 2 may be arranged outside the input / output terminal 3 so as to sandwich the input / output terminal 3. The terminal size of the first input / output terminal 2 is 50
The pitch dimension is 60 to 70 μm. On the other hand, the second input / output terminal 3 has a terminal size of 150 μm □, which is larger than this, and its pitch size is 200 to 500.
Increase to about 0 μm.

According to the semiconductor integrated circuit device having this structure,
When the metal wire is bonded to the semiconductor chip 1, the second input / output terminal 3 is bonded. In this case, the second
Since the terminal size of the input / output terminal 3 is sufficiently large, it becomes easy to ensure the required positional accuracy during bonding, and highly reliable metal wire bonding can be realized. Further, since the pitch size of the second input / output terminals 3 is increased, it is possible to prevent the metal wires bonded at the adjacent positions from contacting each other and being short-circuited.

On the other hand, in the electrical inspection of the semiconductor chip, the first input / output terminals 2 arranged in the peripheral portion are used.
Although the first input / output terminal 2 has a small terminal size and a small pitch size, it is sufficient to bring the probe of the inspection device into contact with the respective terminals, which may be a obstacle to the required inspection. It never happens. Rather, by arranging the first input / output terminals 2 in a row along the periphery of the semiconductor chip, it becomes possible to use the conventionally provided probe arranging inspection device as it is, and to perform a special inspection. It does not require a device, and its price increase can be avoided.

Since the gold film 16 is formed on the surface of the second input / output terminal 3 through the titanium / tungsten film 15 as a barrier metal, it is suitable for a metal wire made of aluminum or gold. Bonding can be realized. On the other hand, since the first input / output terminal 2 is composed of only the terminal wiring layer 13, it is advantageous in terms of simplifying the structure and saving resources.

FIG. 3 is a view showing another embodiment of the present invention and is a sectional view corresponding to FIG. 2B of the above embodiment.
In this embodiment, the gold film 16 on the surface of the second input / output terminal 3 is used.
When the solder bumps 17 are formed on the semiconductor chip, the semiconductor chip is mounted or packaged without using a metal wire, for example, when the semiconductor chip is mounted using a TAB tape, or directly mounted on a lead frame. Is effective for. Note that, as shown in FIG. 4, a laminated film of the titanium / tungsten film 15 and the gold film 16 may be formed also on the first input / output terminal 2. In this case, instead of using the first input / output terminal 2 only for inspection, it is also possible to bond a metal wire to some of the first input / output terminals 2 and use it for electrical connection. Is.

The above-described embodiment is merely an example of the present invention, and particularly the arrangement of the second input / output terminals is arbitrary, for example, the second input / output terminals are shown in FIG. As in the conventional configuration, it is possible to arrange the semiconductor chips on the entire surface in a form close to a matrix. The terminal wiring layer may be formed of an aluminum alloy, and the barrier metal may be titanium nitride or another metal.

[0017]

As described above, according to the present invention, the first input / output terminals having a minute terminal size are arranged in a row at the peripheral portion of the semiconductor chip with a minute pitch size, and the first input / output terminals having a large terminal size are arranged in the inner region. Arrange the 2 input / output terminals with a large pitch,
In addition, since the first input / output terminal and the second input / output terminal are electrically connected to each other, by bonding the metal wire to the second input / output terminal, the positional accuracy is secured and the high accuracy is ensured. Reliable bonding can be realized and mutual short circuit of metal wires can be prevented. Further, by contacting the probe of the inspection device with the first input / output terminal to perform the inspection, the existing inspection device can be used and the inspection can be facilitated. This makes it possible to increase the number of pins of the semiconductor integrated circuit device. Further, the first input / output terminal and the second input / output terminal are made of different materials, and the first input / output terminal is made of aluminum or an aluminum alloy, and the second input / output terminal is made of aluminum or aluminum. By forming a barrier metal film such as titanium on the alloy and forming a gold film on the barrier metal film, it is possible to satisfactorily bond the metal wire to the second input / output terminal, while saving resources or This is advantageous in terms of simplification of the structure.

[Brief description of drawings]

FIG. 1 is a plan view schematically showing the overall configuration of an embodiment of a semiconductor integrated circuit device of the present invention.

2 is an enlarged view of a portion A in FIG. 1, (a) is an enlarged plan view thereof, and (b) is an enlarged sectional view taken along line BB thereof.

FIG. 3 is a sectional view corresponding to FIG. 2B of another embodiment of the present invention.

FIG. 4 is a sectional view of yet another embodiment of the present invention, which corresponds to FIG. 2 (b).

FIG. 5 is a schematic plan view of a semiconductor chip of a conventional semiconductor integrated circuit device.

FIG. 6 is a schematic plan view of a semiconductor chip of another conventional semiconductor integrated circuit device.

[Explanation of symbols]

 1 Semiconductor Chip 2 First Input / Output Terminal 3 Second Input / Output Terminal 4 Connection 10 Silicon Substrate 12 Multilayer Wiring Layer 13 Terminal Wiring Layer 14 Cover Film 15 Titanium / Tungsten Film 16 Gold Film 17 Solder Bump

Claims (5)

[Claims] 1. A plurality of first input / output terminals each having a minute terminal size and arranged at a minute pitch in a peripheral portion of a semiconductor chip on which a semiconductor integrated circuit is formed, and a region inside the first input / output terminal. A plurality of second input / outputs arranged in a terminal size and a pitch size larger than the terminal size and the pitch size of the first input / output terminals, and each of which is individually electrically connected to the first input / output terminal. A semiconductor integrated circuit device comprising: a terminal. 2. At least a part of the first input / output terminal,
2. The semiconductor integrated circuit device according to claim 1, wherein at least a part of the second input / output terminal and a connecting portion for electrically connecting these input / output terminals to each other are integrally formed by one conductive film. 3. The semiconductor integrated circuit device according to claim 1, wherein the material of the surface portions of the first input / output terminal and the second input / output terminal is different. 4. The first input / output terminal is made of aluminum or aluminum alloy, and the second input / output terminal is made of gold / aluminum.
4. The semiconductor integrated circuit device according to claim 3, which has a laminated structure of titanium / tungsten or titanium nitride / aluminum or aluminum alloy. 5. The semiconductor integrated circuit device according to claim 4, wherein the second input / output terminal has solder bumps formed on the surface thereof.