JPH07122814B2 - Sequence controller - Google Patents

Description

TECHNICAL FIELD The present invention relates to a sequence controller which is a combination of a 1-bit processor and a multi-bit processor (generally an 8-bit processor or a 16-bit processor).

2. Description of the Related Art A sequence controller using a 1-bit processor is not good at processing arithmetic instructions and making complicated decisions, whereas a sequence controller using a multi-bit processor has a step number for executing a sequence instruction of a 1-bit processor. This is 2 to 3 times the case, and there is a problem that the processing time is long.

Therefore, it has been attempted to configure a sequence controller by combining a 1-bit processor and a multi-bit processor so as to have the advantages of both. FIG. 2 shows a conventional example of such a sequence controller.

In this conventional example, a 1-bit processor a and an 8-bit processor are combined, and an output section of the 1-bit processor a and an 8-bit processor are combined.
1 word 1 between data bus b of bit processor
Eight bit I / O memories M ₀ , ..., M ₇ are arranged. Each I / O memory M ₀ , ..., M ₇ has an address of OOH to FFH, and the output data from the 1-bit processor a is written to a predetermined address of the addressed I / O memory, and then each I / O memory Data corresponding to the corresponding addresses (data stored in eight I / O memories, including the output data) are simultaneously output to the data bus b.

Problems to be Solved by the Invention According to the above conventional example, when executing one sequence instruction, the access time for writing the output data from the 1-bit processor to the addressed I / O memory and the I / O memory There is a problem that the access time for outputting the data of the / O memory to the data bus in parallel is required, and the instruction execution time becomes longer than that of the sequence controller using the 1-bit processor.

Means for Solving the Problems In order to solve the above problems, the present invention relates to a sequence controller including a combination of a 1-bit processor and a multi-bit processor, and an output unit of the 1-bit processor and a data bus of the multi-bit processor. 1 word 1 bit I / O memory corresponding to the number of bits of the data bus and the same number of output control gate circuits are arranged between
The output section of the bit processor is connected to each I / O memory and each output control gate circuit, while the data output section of each I / O memory is connected to each output control gate circuit, and the output section of each output control gate circuit is connected. Is connected to the data bus, and the output data from the 1-bit processor is addressed by I / O
It is characterized in that the data is written in a predetermined address of the memory, and at the same time, the output data is output to the data bus together with the data stored in the address corresponding to the predetermined address of another I / O memory. .

Operation According to the above configuration, it is possible to simultaneously write the output data from the 1-bit processor to the addressed I / O memory and output the parallel data including the output data to the data bus. It is possible to reduce the execution time of the sequence instruction by half as compared with.

Embodiment In the illustrated embodiment, a general-purpose microcomputer 1 equipped with an 8-bit processor and a 1-bit processor 2 are combined to mainly constitute a sequence controller.

Eight of the I / O memory M ₀ between the 1-bit output unit and the data bus 3 of the microcomputer 1 of the processor _{2, M 1, ..., M} 7 and the respective
Output control gate circuits G ₀ , G ₁ , ..., G ₇ corresponding to the I / O memory are arranged. The I / O memory is of a 1-bit 1-bit type and has addresses OOH to FFH, and a 256-bit random access memory may be used, for example. This I / O
The memory includes a decoder circuit.

The output control gate circuits G ₀ , G ₁ , ..., G ₇ have a first AND gate AND I and a second AND gate AND I, as shown in FIG.
It is composed of II and Owaged OR.

The 1-bit processor 2 has 1-bit input / output and includes a result register which is a 1-bit accumulator.

1-bit processor 2 from program 4 on the microcomputer 1 side
Is given an operation code of 5 and is based on this 1
The bit processor 2 executes the instruction. Further, 11-bit address data 6 from the program 4 is given to the output control section of the 1-bit processor 2. The lower 3 bits A0, A1, A2 of the address data 6 are Y ₀ , ...,
Decoded by Y ₇ , it addresses one of the eight I / O memories M ₀ , M ₁ , ..., M ₇ . Upper 8 of address data 6
Bits A ₃ , ..., A ₁₀ specify corresponding addresses for each I / O memory M ₀ , M ₁ , ..., M ₇ .

The output of the 1-bit processor 2 is the I / O memory M ₀ , M ₁ , ..., M ₇
Of the output control gate circuits G ₀ , G ₁ , ..., G _{7 while} being input to the data input terminal DIN of
Entered in. On the other hand, I / O memory M _0, M _1, ..., output data data output terminal DOUT than the output control gate circuit G _0, G ₁ from M _7, ..., the second AND gate the AND II of G ₇ Is entered. 1st AND gate AND I and 2nd AND gate AND
II is connected to the data bus 3 through the OR gate.

Addressing signal decoded by the address coder 7
Y ₀ , Y ₁ , ..., Y ₇ are input to the output enable terminal OE of each I / O memory M ₀ , M ₁ , ..., M ₇ and each first AND gate AND I via the NOT gate NOT. Meanwhile, each I / O directly
The write enable terminals WE of the memories M ₀ , M ₁ , ..., M ₇ and the respective second AND gates AND II are input.

Therefore, for example, if the program 4 gives an operation code 5 of a data output instruction (store instruction) and predetermined address data 6 and the address data 6 is binary data (00000011110), the 1-bit processor 2 output data (0 or 1) is outputted, when the output data is written to the addressed 03F addresses of I / O memory M ₆ simultaneously, together with the output data,
The data stored at the address 03H of the other I / O memories M ₀ , ... M ₅ , M ₇ excluding the I / O memory M ₆ are output to the data bus 3 in parallel.

This case will be specifically described. The lower 3 bits (110) of the address data 6 are decoded by the address decoder 7, and only Y ₆ is set to (0), and the I / O memory M ₆ can be written and the data cannot be output. And the output data from the 1-bit processor 2 is the first AND gate AND
It is possible to output directly from I and further close the second AND gate AND II. On the other hand, Y ₀ , ... Y ₅ , Y ₇ becomes (1), which makes other I / O memories M ₀ , ... M ₅ , M ₇ unwritable and data output possible, and the first AND gate AND I Closed, and then from the second AND gate AND II to each I / O memory M ₀ , ...
The data stored in M ₅ and M ₇ can be output.

And the upper 8 bits of the address data 6 ((00000011)
By this, the 03H address of each I / O memory M ₀ , M ₁ , ..., M ₇ is selected. Then, the output data is written to the address 03H of the I / O memory M _{6, and} the output data is output to the data bus 3 via the first AND gate AND I and the OR gate OR of the output control gate circuit G ₆ . At the same time, other I / O memory M _0, ... M _5, data stored in 03H address of M ₇ is, the output control gate circuit G ₀ corresponding to respective: second G _5, G ₇ The data is output to the data bus 3 via the AND gate AND II and the OR gate OR.

As described above, according to the present invention, the parallel data including the output data from the 1-bit processor 2 can be output to the data bus at the same timing as writing the output data to the addressed I / O memory. The present invention can be applied not only to a sequence controller including a combination of a 1-bit processor and an 8-bit processor, but also to a sequence controller including a combination of a 1-bit processor and another multi-bit processor such as a 16-bit processor. it can.

EFFECTS OF THE INVENTION Since the present invention has the above-described configuration and operation, it provides a sequence controller capable of processing arithmetic instructions and making complex judgments and shortening the processing time similarly to the one configured using a 1-bit processor. can do.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional example. 1 ... Microcomputer equipped with multi-bit processor 2 ... 1-bit processor 3 ... Data bus G ₀ , G ₁ , ..., G ₇ ...... Output control gate circuit M ₀ , M ₁ , ..., M ₇ ...... 1 Word 1-bit I / O memory.

Claims (1)

[Claims] 1. A sequence controller comprising a combination of a 1-bit processor and a multi-bit processor, wherein a number corresponding to the number of bits of the data bus is provided between the output section of the 1-bit processor and the data bus of the multi-bit processor. 1-word 1-bit I / O memory and the same number of output control gate circuits are arranged, and the output part of the 1-bit processor is connected to each I / O memory and each output control gate circuit, while the data of each I / O memory is connected. The output part is connected to each output control gate circuit, the output part of each output control gate circuit is connected to the data bus, and the output data from the 1-bit processor is written to a predetermined address of the addressed I / O memory. At the same time, the output data is output to the data bus together with the data stored in the address corresponding to the predetermined address of another I / O memory. Sequence controller characterized by being configured so.