JPH07123003A - A/d converter - Google Patents

Abstract

PURPOSE:To compare plural bits simultaneously and to attain high speed conver sion without bit by bit, by comparison providing plural number of comparison reference voltages and comparators for A/D conversion. CONSTITUTION:A control circuit 106 provides an output of contents latched by each of comparison registers 107-109 to a multiple reference voltage generating circuit 110. The circuit 110 has a D/A conversion function and converts plural digital values to be received simultaneously into analog signals to provide the output to comparators 103-105. Each of the comparators 103-105 compares an output of a sample-and-hold circuit 102 with an output of the circuit 110 to provide an output of '1' when the output of the circuit 102 is higher and to provide an output of $0' when the output of the circuit 102 is lower conversely. The control circuit 106 controlling timing of A/D conversion receives outputs of the comparators 103-105 to decide the content of the output to allow each of the registers 107-109 to latch the content and outputs the latched content in the registers 107-109.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter that converts an input analog signal into a digital signal and outputs the digital signal.

[0002]

2. Description of the Related Art The prior art of a successive approximation A / D converter and a follow-up comparison A / D converter, which are the basis of the present invention, will be described.

FIG. 3 is a diagram showing the structure of a successive approximation A / D converter which has been conventionally used.

In this conventional example, an input terminal 301 for receiving a signal to be A / D converted, a sample & hold circuit 302 for holding the input signal, a signal held by the sample & hold circuit 302 and D Comparator 313 that compares the output of the A / A converter 315, a comparison register 314 that holds the output of the comparator 313, a D / A converter 315 that converts the value of the comparison register 314 into an analog signal, and the circuit described above. It is an A / D converter configured with a control circuit 36 for controlling the constituent elements.

An analog signal input from the input terminal 301 is held by the sample & hold circuit 302. Output of sample & hold circuit 302 and D / A converter 31
The signals from 5 are compared by the comparator 313, and the digital conversion value is determined in order from the most significant bit to the least significant bit.

As the first step of A / D conversion, first, the input signal received at the input terminal 301 is sampled by the sample & hold circuit 302. At this time, the comparison register 3
A digital value in which only the most significant bit is set is stored in 14, and the other bits are reset.
This value is converted into an analog signal by the D / A converter 315. At this time, the analog signal output from the D / A converter 315 has a value of half the full scale. The output of the D / A converter 315 is input to the comparator 313 and compared with the analog input signal held in the sample & hold circuit 302. As a result, if the analog input signal is larger, the comparator 313 outputs "1", and conversely, if the analog input signal is smaller, the comparator 313 outputs "0". The output signal of the comparator 313 is input to the most significant bit set by the comparison register 314,
The most significant bit of is determined.

Next, the upper 2nd bit is set, and the operation after the analog signal conversion processing by the D / A converter 315 is repeated until the comparison of the least significant bit is completed.
When the determination of the least significant bit of the comparison register 314 is completed, one A / D conversion is completed.

Since the successive approximation A / D converter operates as described above, when the conversion precision is n bits, one conversion requires n comparisons from the most significant bit to the least significant bit. . Therefore, one A / D conversion of the successive approximation A / D converter
When the conversion accuracy is n bits, the D conversion time requires a time for performing comparisons n times.

FIG. 4 shows the structure of a conventional tracking comparison type A / D converter. FIG. 4 shows an input terminal 401 for receiving a signal to be A / D converted, a sample & hold circuit 402 for holding the signal, a signal held by the sample & hold circuit 402 and D / A converter 415
Of the output of the comparator 413 and the comparator 413
Control circuit 406 for receiving the output of
Is an A / D converter including a register 416 for incrementing or decrementing a held value in response to the output signal of the above, and a D / A converter 415 for converting the value of the register 416 into an analog value.

In the conventional follow-up comparison method, the previous A / D conversion result is held and used for this A / D conversion.

The value of the register 416 holding the previous A / D conversion result is converted into an analog signal by the D / A converter 415, and this analog signal and the analog input signal of this time are compared by the comparator 413. If the analog input signal is larger, the comparator 413 outputs "1". Conversely, if the analog input signal is smaller, the comparator 413 outputs "0". The control circuit 406 outputs a signal for incrementing the content of the register 416 by 1 when the output of the comparator 413 is “1”, and the register 4 when the output of the comparator 13 is “0”.
A signal that decrements the contents of 16 by 1 is output. The register 416 increments or decrements its contents according to the signal from the control circuit 406.

Hereinafter, the value of the register 416 incremented or decremented is used, and the comparison with the analog input signal is repeated again. Input signal and D / A converter 415
The value of the register 416 at the time when the output signals of the above are equal to each other becomes the A / D conversion result.

Since the follow-up comparison type A / D converter operates as described above, one conversion time varies. If the previous input signal and the current input signal are almost equal, the A / D conversion can be completed by several comparisons. Conversely, if the previous input signal and the current input signal are far from each other, a considerably large number of comparisons are required and the A / D conversion time becomes long. When the conversion accuracy is n bits, the maximum value is 0 when the previous input signal is 0, and when the current input signal is full scale, the value is incremented by 1. Therefore, 2 ⁿ comparisons are required.

[0014]

A conventional follow-up comparison type A / D converter used for converting an analog signal with little fluctuation is 2 ⁿ at maximum when the A / D conversion accuracy is n bits.
There is a problem in that it requires comparison twice and takes too much conversion time.

On the other hand, in the conventional successive approximation A / D converter, the conversion time is always constant, and when the A / D conversion precision is n bits, even if the analog input signal does not change,
There is a problem that the comparison is always required n times and the conversion time is unnecessarily required.

The present invention has been made in view of the problems of the above-mentioned conventional techniques, and is capable of performing A / D at high speed.
An object is to realize an A / D converter that can perform conversion.

[0017]

An A / D converter of the present invention is an input terminal to which an analog signal to be A / D converted is input, and a sample for holding the analog signal input from the input terminal. By converting the & hold circuit and the input digital signals into analog signals,
A multi-reference voltage generating circuit that generates a plurality of different reference voltages; a plurality of comparators that respectively compare the signal held by the sample-and-hold circuit with each reference voltage generated by the multi-reference voltage generating circuit; A plurality of comparison registers provided corresponding to the plurality of comparators and a plurality of bits stored in each comparison register according to each comparison result of the plurality of comparators; And a control circuit for outputting the stored contents to the multi-reference voltage generating circuit as a plurality of digital signals for converting into a reference voltage.

In this case, the control device sets several high-order bits of the previous A / D conversion result to each comparison register at the start of the conversion operation, and sets the following plural bits so that the stored contents are different from each other. You may.

An A / D converter according to another aspect of the present invention is
An input terminal to which an analog signal to be A / D converted is input, a sample & hold circuit that holds the analog signal input from the input terminal, and a plurality of input digital signals are converted to analog signals. A plurality of reference voltage generating circuits for generating a plurality of different reference voltages, a plurality of comparisons for respectively comparing the signal held by the sample & hold circuit, and each reference voltage generated by the multiple reference voltage generating circuit. And a plurality of comparison registers provided corresponding to the plurality of comparators, fixing means for fixing arbitrary bits of the plurality of comparison registers at the start of A / D conversion, and a plurality of comparators of the plurality of comparators. The contents stored in a plurality of bits of each comparison register are set according to each comparison result, and the contents stored in each comparison register are stored in the multi-reference voltage generation circuit as a reference voltage. And having a control circuit for outputting a plurality of digital signals for converting.

[0020]

Since a plurality of reference voltages for comparison and comparators for A / D conversion are provided, a plurality of bits can be compared at the same time without performing the comparison for each bit as in the conventional example. , Fast conversion is done.

Further, since the contents of the plurality of comparison registers are determined by the control device and the fixing means, for example, the upper several bits of the previous A / D conversion result are left and only the lower plurality of bits are changed. Is possible and has little fluctuation,
The analog signal can be converted at a higher speed.

[0022]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention, which will be described below with reference to FIG. Here, an example of an 8-bit A / D converter using three comparators is shown.

The circuit includes an analog input terminal 101, a sample & hold circuit 102 for holding an analog voltage,
Three comparators 103 to 105, multi-reference voltage generation circuit 11
0, comparison registers 107 to 109 provided corresponding to the comparators 103 to 105, and comparison registers 10 respectively.
A register 111 having a function of setting a holding state of arbitrary bits 7 to 109 and a control circuit 106 for controlling each circuit described above.

The digital values stored in the comparison registers 107-109 are converted into analog values corresponding to the comparison registers 107-109 by the multi-reference voltage generation circuit 110 and input to the comparators 103-105, respectively. The contents of the register 111 are variable and can be set freely. By adjusting this value, analog input terminals 101 with different amplitudes
More input analog input signals can be supported. An analog input signal with a small amplitude should hold the upper bits of each comparison register 107-109 as much as possible, and an analog input signal with a large amplitude does not hold the upper bits of each comparison register 107-109 much. Just do it.

The control circuit 6 controls each of these comparison registers 10
The multi-reference voltage generation circuit 10 outputs the contents held in 7 to 109. The multi-reference voltage generation circuit 10 has a D / A conversion function, and simultaneously converts a plurality of digital values sent from the control circuit 6 into analog signals to compare the comparators 103-1.
Output to 05.

Each of the comparators 103 to 105 has an output of the sample and hold circuit 2 and a multi-reference voltage generating circuit 10.
Are compared, and if the output of the sample and hold circuit 2 is larger, "1" is output, and conversely, if the output of the multiple reference voltage generation circuit 10 is larger, "0" is output.

The control circuit 6 for controlling the timing of A / D conversion receives the outputs of the comparators 103 to 105, determines the contents to be held in the comparison registers 107 to 109 according to the contents of the outputs, and holds them. Then each comparison register 1
The stored contents of 07 to 109 are read and output to the multi-reference voltage generation circuit 10.

Next, a specific conversion operation of this embodiment will be described.

The previous A / D conversion result is set to "xxxxxxxxx" in 8-bit binary number. Where "x" is
It is “0” or “1”. These values are stored in the comparison registers 107 to 109.

In the following description, it is assumed that the register 111 contains a signal holding the upper 4 bits of the comparison registers 107 to 109 in advance.

When this A / D conversion is started, the analog input signal input from the analog input terminal 101 is
It is held by the sample & hold circuit 102. The control circuit 106 uses the register 11 for the comparison register 107.
A signal for setting bits other than the upper 4 bits set by 1 is sent to, and a signal for resetting bits other than the upper 4 bits set by the register 111 is sent to the comparison register 109. As a result, the values shown in Table 1 are set in the comparison registers 107-109.

[0033]

[Table 1] MSB: most significant bit LSB: least significant bit The values shown in Table 1 are converted into an analog signal by the multi-reference voltage generation circuit 110 through the control circuit 106, and each comparator 103.
To 105.

The first comparison is intended to confirm whether the input signal is between the values in the comparison register 107 and the comparison register 109.

Assuming that the analog input signal is the comparison register 1
If it is between 07 and the value of the comparison register 108, 1
In the second comparison, the above values are compared to the respective comparison registers 107 to 10
Since it is set to 9, the output contents of the comparators 103 to 105 are as shown in Table 2.

[0036]

[Table 2] At this point, the input signal held by the sample-and-hold circuit 102 to be A / D converted is compared with the comparison register 10
It can be seen that the value is between 7 and the comparison register 109.
Therefore, since the upper 4 bits can be determined by "xxxx" as they are, the control circuit 106 sends a signal for determining the upper 4 bits to each of the comparison registers 107 to 109.

Conversely, the analog input signal is the comparison register 1
It is not between the values 07 and 109. Comparator 1 at this time
The outputs of 03 to 105 are all "1" or all "0" as shown in Table 3.

[0038]

[Table 3] When the control circuit 6 receives the values in Table 3, it can be seen that the analog input signal is not between the values in the comparison register 107 comparison register 109. Therefore, in the second comparison, since the input signal is not between the values of the comparison register 107 and the comparison register 109, the upper n bits of the comparison registers 107 to 109 held in the register 111 are invalidated and the most significant bit Since it is necessary to convert from the
The reference numeral 6 sends a signal for invalidating the upper 4 bits to each of the comparison registers 107 to 109.

From the second comparison, successive bits are converted from the bit next to the bit determined in the first comparison. Here, since three comparators are provided, it is possible to perform conversion by 2 bits.

The control circuit 106 outputs to the comparison registers 107 to 109 the value shown in Table 4 from the bit next to the bit already determined by the comparison so far, and resets all the subsequent bits. Output.

[0041]

[Table 4] For example, when the analog input signal is between the values of the comparison register 107 and the comparison register 109, the bits determined at the time of the second comparison are the upper 4 bits. Also,
When the analog input signal is not between the values of the comparison register 107 and the comparison register 109, there is no bit determined during the second comparison.

Therefore, assuming that the analog input signal is between the values of the comparison register 107 and the comparison register 108, the values of the respective comparison registers 107 to 109 are shown in Table 5.
It will be as shown in.

[0043]

[Table 5] The control circuit 106 receives the values shown in Table 5 and outputs them to the multi-reference voltage generating circuit 110. Multi-reference voltage generation circuit 1
Reference numeral 10 converts the value input from the control circuit 106 into an analog signal, which is input to each of the comparators 103 to 105. Each of the comparators 103 to 105 compares the analog input signal with the analog signal converted by the multi-reference voltage generation circuit 10, and outputs the comparison result to the control circuit 106. The control circuit 106
The values corresponding to the respective outputs of the respective comparators 103 to 105 are output to the comparison registers 107 to 109 from the bit next to the bit already determined by the comparison so far. The output of the control circuit 106 is shown in Table 6.

[0044]

[Table 6] (i): When the input signal of the conversion target is smaller than the value of the comparison register 109 (ii): When the input signal of the conversion target is larger than the value of the comparison register 109 and smaller than the comparison register 108 (iii): The conversion target Input signal of the comparator register 108
Is larger than the value of and is smaller than the comparator register 107 (iv): the input signal to be converted is the comparator register 107.
When the value is larger than the value of, each of the comparison registers 107 to 109 having received the output from the control circuit 106 substitutes the above value from the bit next to the already determined bit. That is, at this point, if the input signal to be converted has a value between the comparison register 107 and the comparison register 109, the upper 5th bit and the 6th bit are determined.

In this case, the control circuit 106 determines the bit to be compared, and at the same time, determines the bit to be compared from the bit next to the already determined bit. In this case, the upper 7 and 8 of the comparison registers 107 to 109 are used. The value shown in Table 4 is output to the bit.

Thereafter, the operations after the second comparison are repeated, and the A / D conversion is completed when the value of the least significant bit is determined.

Next, a second embodiment of the present invention will be described with reference to FIG.
Will be described with reference to.

In the first embodiment, the comparison registers 107 ...
The register 111 is provided as a fixing means for holding the upper n bits of 109, but in the second embodiment, the external input terminal 212 is provided so that it can be arbitrarily set from the outside. Since the other structure is the same as that of the first embodiment shown in FIG. 1, the same reference numerals as those in FIG.

In the present embodiment, the upper n bits of the digital value that is the A / D conversion candidate can be arbitrarily set regardless of the previous conversion result, so that it can be set according to the type of signal to be converted. Become.

In the embodiment described above, the register 111 and the external input terminal 212 are provided, but this function can be realized by the control circuit 106 as a matter of course. By providing these fixing means, the function required of the control means can be lowered, but the control circuit 106 may of course set the upper n bits of the digital value.

[0051]

Since the present invention is constructed as described above, it has the following effects.

By providing a plurality of comparators, a plurality of bits can be compared at the same time and a high-speed A / D can be obtained.
The effect is that conversion can be performed.

Since the value stored in the comparison register to be compared by each comparator can be arbitrarily set, it is possible to leave the previous A / D conversion result in the upper bits. When used in this way, there is an effect that A / D conversion can be performed at a higher speed for a signal having a small amplitude.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a conventional successive approximation type A / D converter.

FIG. 4 is a diagram showing a configuration of a conventional tracking comparison type A / D converter.

[Explanation of symbols]

 101 analog input terminal 102 sample & hold circuit 103 comparator 104 comparator 105 comparator 106 control circuit 107 comparison register 108 comparison register 109 comparison register 110 multi-reference voltage generation circuit 111 analog input terminal 212 external input terminal

Claims (3)

[Claims] 1. An A / D converter, comprising: an input terminal to which an analog signal to be A / D converted is input; a sample-and-hold circuit for holding the analog signal input from the input terminal; A multi-reference voltage generation circuit that generates a plurality of different reference voltages by converting the plurality of digital signals into analog signals, a signal held by the sample-and-hold circuit, and the multi-reference voltage generation circuit. A plurality of comparators for respectively comparing the reference voltages with each other, a plurality of comparison registers provided corresponding to the plurality of comparators, and a plurality of comparison registers according to respective comparison results of the plurality of comparators. Outputs a plurality of digital signals for setting the stored contents of bits and converting the stored contents of each comparison register to the multi-reference voltage generation circuit. And a control circuit for controlling the A / D converter. 2. The A / D converter according to claim 1, wherein the controller sets several high-order bits of the previous A / D conversion result to each comparison register at the start of the conversion operation, and An A / D converter characterized in that bits are set so that stored contents are different from each other. 3. In an A / D converter, an input terminal to which an analog signal to be A / D converted is input, a sample & hold circuit which holds the analog signal input from the input terminal, and an input terminal. A multi-reference voltage generation circuit that generates a plurality of different reference voltages by converting the plurality of digital signals to analog signals; a signal held by the sample-and-hold circuit; and a multi-reference voltage generation circuit. A plurality of comparators for respectively comparing the reference voltages with each other, a plurality of comparison registers provided corresponding to the plurality of comparators, and an arbitrary bit of the plurality of comparison registers at the start of A / D conversion. Fixing means for fixing the contents of a plurality of bits of each comparison register according to each comparison result of the plurality of comparators, and A / D converter, characterized in that a control circuit for outputting the content as a plurality of digital signals for converting the reference voltage to the multi-reference voltage generating circuit.