JPH07123140B2 - Method for manufacturing semiconductor integrated circuit - Google Patents
Method for manufacturing semiconductor integrated circuitInfo
- Publication number
- JPH07123140B2 JPH07123140B2 JP2171522A JP17152290A JPH07123140B2 JP H07123140 B2 JPH07123140 B2 JP H07123140B2 JP 2171522 A JP2171522 A JP 2171522A JP 17152290 A JP17152290 A JP 17152290A JP H07123140 B2 JPH07123140 B2 JP H07123140B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- base region
- signal transistor
- concentration
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Bipolar Integrated Circuits (AREA)
Description
【発明の詳細な説明】 (イ)産業上の利用分野 本発明はIcmaxと耐圧とhFEとを全て満足し得るトランジ
スタを具備する半導体集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a semiconductor integrated circuit including a transistor that can satisfy all of Icmax, breakdown voltage, and h FE .
(ロ)従来の技術 半導体集積回路では各拡散領域を共通に用いて工程を簡
略化すること、が基本的な技術思想であるので、各回路
素子は全て共通の拡散領域で構成され、同一チップ上の
素子(NPNトランジスタ)は全て同一の特性を有してい
た。(B) Conventional technology Since the basic technical idea is to use each diffusion region in common in a semiconductor integrated circuit to simplify the process, each circuit element is configured with a common diffusion region, and the same chip is used. All of the above elements (NPN transistors) had the same characteristics.
ところが、民生用、特に音響用IC等では、各種信号処理
用回路と同時に出力段のパワー系トランジスタが組み込
まれることが多く、回路的な要求から前記信号処理用の
小信号トランジスタと前記出力段用の大信号トランジス
タとで電流増幅率hFEを異ならしめる要求がある。つま
り、小信号トラジスタのhFEを100〜200とした時に、大
信号トランジスタのhFEを50程度に下げて最大コレクタ
電流Icmaxを増大するという要求である。However, in consumer ICs, especially audio ICs, etc., power system transistors in the output stage are often incorporated at the same time as various signal processing circuits, and due to circuit requirements, small signal transistors for signal processing and output stage transistors are used. There is a demand to make the current amplification factor h FE different from that of the large signal transistor. That is a request that the h FE of the small signal Torajisuta when 100 to 200, to increase the maximum collector current Icmax lowers the h FE of the large-signal transistor to about 50.
このようにhFEを変更する手段として、例えば特開昭60
−70756号公報に記載されているようにベース領域を個
々に別形成する手段がある。As means for changing h FE as described above, for example, Japanese Patent Laid-Open No.
There is a means for separately forming the base region as described in Japanese Patent Publication No. 70756.
即ち第3図に示す如く、エピタキシャル層(1)を分離
領域(2)で分離した各アイランド(3)に、小信号ト
ランジスタ(4)用のベース領域(5)と大信号トラン
ジスタ(6)用のベース領域(7)とを個々に形成する
ものである。この時、大信号トランジスタ(6)のベー
ス領域(7)は2つの手法が考えられる。1つは不純物
濃度を高く設定してhFEを小さくする手法(第4図第1
案)、2つは拡散深さを深くして(ベース幅を広げる)
hFEを小さくする手法(第4図第2案)である。That is, as shown in FIG. 3, each island (3) obtained by separating the epitaxial layer (1) by the separation region (2) has a base region (5) for the small signal transistor ( 4 ) and a large signal transistor ( 6 ). And the base region (7) of the above are individually formed. At this time, two methods can be considered for the base region (7) of the large signal transistor ( 6 ). One is a method to reduce the h FE by setting a high impurity concentration (Fig. 4, Fig. 1).
2) Deepen the diffusion depth (widen the base width)
It is a technique to reduce the h FE (second draft Figure 4).
(ハ)発明が解決しようとする課題 しかしながら、上記先の手法はシリコン結晶に対するボ
ロンの飽和限界があるためにそれ程高くはできず、従っ
てhFEを下げるにも限界があるという欠点があった。し
かもツェナ降伏による耐圧劣化が危惧される他、ベース
領域(7)をイオン注入で形成する場合はドーズ量が増
す分処理時間が長くなって工程の煩雑化を招く。他方、
後の手法はhFEを下げるという目的には合致するが、不
純物濃度と拡散深さとは密接な関係があり、ベースの不
純物濃度が低下して伝導度変調をきたすので、Icmaxが
増大しないという欠点があった。このことから、hFEが
同じであればベースの濃度は高い方がIcmaxを大きくで
きるのである。そして、不純物濃度とベース幅の両者を
制御したとしても、hFEとIcmaxの両者を満足させること
はやはり困難であった。(C) Problem to be Solved by the Invention However, the above-mentioned method has a drawback in that it cannot be increased so much due to the saturation limit of boron with respect to silicon crystals, and thus there is a limit in reducing h FE . Besides, there is a concern that the breakdown voltage may be deteriorated due to the Zener breakdown, and when the base region (7) is formed by ion implantation, the treatment time becomes long due to the increase of the dose amount, which complicates the process. On the other hand,
Although the latter method meets the purpose of lowering h FE , there is a close relationship between the impurity concentration and the diffusion depth, and the impurity concentration of the base decreases, which causes conductivity modulation, so that Icmax does not increase. was there. Therefore, if h FE same base concentration is the higher can be increased Icmax. Even if both the impurity concentration and the base width are controlled, it is still difficult to satisfy both h FE and Icmax.
(ニ)課題を解決するための手段 本発明は上記従来の欠点に鑑み成され、比較的高い不純
物濃度を有する大信号トランジスタ(25)のベース領域
(26)の底部に、ベース領域(26)よりは低い不純物濃
度を有する低濃度ベース領域(28)を形成することによ
り、小信号トランジスタ(16)よりは小さいhFEを有す
る大信号トランジスタ(25)を共存させると共に、前記
低濃度ベース領域(28)とIIL(20)のウェル領域(2
3)とを同時形成することにより、IILとの共存をも図る
ものである。(D) Means for Solving the Problems The present invention has been made in view of the above-mentioned conventional drawbacks, and a base region (26) is formed at the bottom of the base region (26) of a large signal transistor ( 25 ) having a relatively high impurity concentration. By forming the low-concentration base region (28) having a lower impurity concentration, a large-signal transistor ( 25 ) having a smaller h FE than the small-signal transistor ( 16 ) coexists and the low-concentration base region (28) is formed. 28) and IIL ( 20 ) well area (2
By simultaneously forming 3) and 3), it is possible to coexist with IIL.
(ホ)作用 本発明によれば、低濃度ベース領域(28)を重畳したこ
とによって大信号トランジスタ(25)のベース幅が広が
るので、そのhFEを小信号トランジスタ(16)のhFEより
小さく且つ適切な値に制御することができる。しかも、
ベースの一部は比較的高い不純物濃度を有するベース領
域(26)で構成するので、最大コレクタ電流Icmaxを大
にできる。そして、前記大信号トランジスタ(25)の低
濃度ベース領域(28)をIIL(20)の低濃度ウェル領域
(23)と同時形成するので、効率的に共存させることが
できる。According to (e) acts present invention, since the base width of the large signal transistor by superimposed low concentration base region (28) (25) widens less than the h FE of the h FE small signal transistor (16) And it can be controlled to an appropriate value. Moreover,
Since a part of the base is composed of the base region (26) having a relatively high impurity concentration, the maximum collector current Icmax can be increased. Since the low-concentration base region (28) of the large signal transistor ( 25 ) and the low-concentration well region (23) of the IIL ( 20 ) are simultaneously formed, they can coexist efficiently.
(ヘ)実施例 以下に本発明の一実施例を図面を参照しながら詳細に説
明する。(F) Embodiment One embodiment of the present invention will be described in detail below with reference to the drawings.
第1図は本発明による半導体集積回路を示す断面図であ
る。同図において、(11)はP型シリコン単結晶基板、
(12)は基板(11)表面にエピ成長して形成したN-型エ
ピタキシャル層、(13)はN+型埋め込み層、(14)は埋
め込み層(13)を囲みエピタキシャル層(12)を貫通す
るP+型分離領域、(15)は分離領域(14)によって個々
に分離されたアイランドである。FIG. 1 is a sectional view showing a semiconductor integrated circuit according to the present invention. In the figure, (11) is a P-type silicon single crystal substrate,
(12) is an N − type epitaxial layer formed by epitaxial growth on the surface of the substrate (11), (13) is an N + type buried layer, and (14) surrounds the buried layer (13) and penetrates the epitaxial layer (12). The P + -type isolation region (15) is an island individually isolated by the isolation region (14).
アイランド(15)の1つには小信号トランジスタ(16)
を形成すべくP型のベース領域(17)とN+型のエミッタ
領域(18)を形成し、アイランド(15)をコレクタとし
て縦型NPNトランジスタを形成する。(19)はN+型コレ
クタコンタクト領域である。One of the islands (15) has a small signal transistor ( 16 )
To form the P type base region (17) and the N + type emitter region (18), the island (15) is used as a collector to form a vertical NPN transistor. (19) is an N + type collector contact region.
他のアイランド(15)にはIIL(20)を形成すべくP型
のインジェクタ領域(21)と外部ベース領域(22)、P-
型のウェル領域(23)、N+型のコレクタ領域(24)を形
成し、ウェル領域(23)を逆方向縦型インバータトラン
ジスタのベースとしてIILを形成する。ウェル領域(2
3)をベースとすることにより、前記インバータトラン
ジスタのエミッタからベースへのキャリア注入の主体と
なるN+型埋め込み層(13)にベースが近接するので、高
い逆βが得られるというものである。On the other island (15), a P-type injector region (21), an extrinsic base region (22), and P − are formed to form IIL ( 20 ).
Type well region (23) and N + type collector region (24) are formed, and IIL is formed using the well region (23) as the base of the reverse vertical inverter transistor. Well area (2
By using 3) as a base, a high reverse β can be obtained because the base is close to the N + type buried layer (13) which is a main carrier injection from the emitter of the inverter transistor to the base.
そして、更に他のアイランド(15)には大信号トランジ
スタ(25)を形成すべくP型ベース領域(26)とN+型エ
ミッタ領域(27)を形成する他、ベース領域(26)に重
ねてP-型の低濃度ベース領域(28)を形成した。(29)
はN+コレクタコンタクト領域、(30)はシリコン酸化
膜、(31)は各電極である。ベース領域(17)(26)と
エミッタ領域(18)(27)は夫々共通の工程で形成し
た。また、IIL(20)のウェル領域(23)と大信号トラ
ンジスタ(25)の低濃度ベース領域(28)は同時形成し
た。Then, in another island (15), a P-type base region (26) and an N + -type emitter region (27) are formed in order to form a large signal transistor ( 25 ), and the island is overlaid on the base region (26). A P - type low concentration base region (28) was formed. (29)
Is an N + collector contact region, (30) is a silicon oxide film, and (31) is each electrode. The base regions (17) (26) and the emitter regions (18) (27) were formed in the same process. The well region (23) of the IIL ( 20 ) and the low concentration base region (28) of the large signal transistor ( 25 ) were formed simultaneously.
IILのウェル領域(23)は、前述したようにベース・エ
ミッタ接合を埋め込み層(13)に近接することが目的で
あるから、拡散深さは深く、且つ逆βを高くする為に低
不純物濃度としてある。具体的には、ベース領域(17)
(26)が表面濃度1018atoms・cm-2、拡散深さ1.0〜1.5
μに形成されるのに対し、ウェル領域(23)は表面濃度
1016〜1017atoms・cm-2、拡散深さ2.0〜3.0μに形成す
る。Since the IIL well region (23) is intended to have the base-emitter junction close to the buried layer (13) as described above, it has a deep diffusion depth and a low impurity concentration in order to increase the inverse β. There is. Specifically, the base area (17)
(26) has a surface concentration of 10 18 atoms · cm -2 and a diffusion depth of 1.0 to 1.5
well region (23) has a surface concentration
10 16 to 10 17 atoms · cm -2 and a diffusion depth of 2.0 to 3.0 μ are formed.
ウェル領域(23)と大信号トランジスタ(25)の低濃度
ベース領域(28)とは同時形成するので、低濃度ベース
領域(28)は当然に上記した不純物濃度と深さを有す
る。このように不純物濃度を低くした場合、不純物の表
面デプリートによるリーク電流の増大が危惧されるの
で、低濃度ベース領域(28)はベース領域(26)をはみ
出さないように形成した。つまり、低濃度ベース領域
(28)の全面をベース領域(26)で覆うように重畳した
のである。Since the well region (23) and the low-concentration base region (28) of the large signal transistor ( 25 ) are formed simultaneously, the low-concentration base region (28) naturally has the above-mentioned impurity concentration and depth. When the impurity concentration is lowered as described above, the increase in the leak current due to the surface depletion of impurities is feared, so the low concentration base region (28) is formed so as not to protrude from the base region (26). That is, the entire surface of the low-concentration base region (28) is superposed so as to be covered with the base region (26).
大信号トランジスタ(25)は、エミッタ領域(27)の下
部にベース領域(26)と低濃度ベース領域(28)とを有
するので、その不純物濃度プロファイルは第5図に示す
ような分布を有する。即ち、比較的高不純物濃度のベー
ス領域(26)が形成する比較的急峻な傾きと、比較的低
不純物濃度の低濃度ベース領域(28)が形成する緩やか
な傾きとの2段階の傾きを有する。結果、大信号トラン
ジスタ(25)のベース幅WBは同図に示す如く低濃度ベー
ス領域(28)の拡散深さで決まるので、ベース領域(2
6)だけの小信号トランジスタ(17)よりはベース幅を
大にでき、電流増幅率hFEを小にできる。低不純物濃度
の領域であるから、hFEが下がり過ぎるということも無
い。と同時に、大信号トランジスタ(25)のベースには
ベース拡散による比較的高不純物濃度のベース領域(2
6)が重なるので、ベースの伝導度変調による影響が少
なく、従ってhFEを下げたことにより得られるIcmaxの増
大を最大限有効に引き出すことができる。Since the large signal transistor ( 25 ) has the base region (26) and the low concentration base region (28) below the emitter region (27), its impurity concentration profile has a distribution as shown in FIG. That is, it has a two-step inclination, a relatively steep inclination formed by the base region (26) having a relatively high impurity concentration and a gentle inclination formed by the low concentration base region (28) having a relatively low impurity concentration. . As a result, the base width W B of the large signal transistor ( 25 ) is determined by the diffusion depth of the low-concentration base region (28) as shown in FIG.
The base width can be made larger and the current amplification factor h FE can be made smaller than that of the small signal transistor (17) having only 6). Since it is a low impurity concentration region, h FE will not drop too much. At the same time, the base of the large signal transistor ( 25 ) has a relatively high impurity concentration in the base region (2
Since 6) overlaps, the influence of the conductivity modulation of the base is small, and therefore the increase in Icmax obtained by lowering h FE can be maximized.
第2図A乃至第2図Dは本願集積回路の製造方法を示し
た。2A to 2D show a method of manufacturing the integrated circuit of the present application.
先ず第2図Aに示す如く埋め込み層(13)と下側の分離
領域(14)を形成した基板(11)上にエピタキシャル層
(12)を形成し、ボロン(B)を低濃度ベース領域(2
8)とウェル領域(23)に対応する部分に選択的に必要
なドーズ量だけイオン注入し、 第2図Bに示す通り基板(11)全体に熱処理を加えるこ
とによりエピタキシャル層(12)表面にドープしたボロ
ン(B)を所望深さまでドライブインをし、 第2図Cに示す通り上側の分離領域(14)を形成した
後、再びボロン(B)を選択的にイオン注入してドライ
ブインすることにより小信号トランジスタ(16)のベー
ス領域(17)と大信号トランジスタ(25)のベース領域
(27)、IIL(20)の外部ベース領域(22)とインジェ
クタ領域(21)とを全て同時形成し、 そして第2図Dに示す通りエミッタ拡散で小信号トラン
ジスタ(16)と大信号トランジスタ(25)のエミッタ領
域(18)(27)、およびIIL(20)のコレクタ領域(2
4)を形成する。First, as shown in FIG. 2A, an epitaxial layer (12) is formed on a substrate (11) on which a buried layer (13) and a lower isolation region (14) are formed, and boron (B) is added to a low concentration base region ( 2
8) and the well region (23) are selectively ion-implanted in a necessary dose amount, and heat treatment is applied to the entire substrate (11) as shown in FIG. The doped boron (B) is driven in to a desired depth to form an upper isolation region (14) as shown in FIG. 2C, and then boron (B) is selectively ion-implanted and driven in again. As a result, the base region (17) of the small signal transistor ( 16 ), the base region (27) of the large signal transistor ( 25 ), the external base region (22) of the IIL ( 20 ) and the injector region (21) are all formed simultaneously. Then, as shown in FIG. 2D, the emitter regions (18) and (27) of the small signal transistor ( 16 ) and the large signal transistor ( 25 ) and the collector region (2 of the IIL ( 20 ) are diffused by the emitter diffusion.
4) to form.
本願構成は、多少の熱処理を加えても拡散深さが変動し
にくい、拡散済みの低濃度ベース領域(28)にベース拡
散を処して小信号トランジスタ(16)と大信号トランジ
スタ(25)を形成するので、ベース拡散は小信号トラン
ジスタ(16)用に制御して拡散を行うことができる。従
って、小信号トランジスタ(16)、大信号トランジスタ
(25)共に特性の制御が極めて容易である。According to the configuration of the present application, the small signal transistor ( 16 ) and the large signal transistor ( 25 ) are formed by subjecting the diffused low-concentration base region (28) to base diffusion to prevent the diffusion depth from fluctuating even if some heat treatment is applied. Therefore, the base diffusion can be controlled and diffused for the small signal transistor ( 16 ). Therefore, it is extremely easy to control the characteristics of both the small signal transistor ( 16 ) and the large signal transistor ( 25 ).
(ト)発明の効果 以上に説明した通り、本発明によれば、大信号トランジ
スタ(25)に低濃度ベース領域(28)を重ねることによ
って、hFEが高い小信号トランジスタ(16)とhFEが小さ
い大信号トランジスタ(25)とを容易に共存できる利点
を有する。また、大信号トランジスタ(25)のベースは
比較的高い不純物濃度を有するベース領域(26)との重
畳であるから、伝導度変調によるIcmaxの低下が少な
く、従ってIcmaxを最大限に増大できる利点を有する。
さらに、大信号トランジスタ(25)のhFEを下げること
によってASOを増大せしめ、出力段トランジスタとして
適切な特性に製造できる利点をも有する。そして更に、
低濃度ベース領域(28)を利用することによって、大信
号、小信号共に特性の制御が容易であるという利点をも
有する。(G) Effect of the Invention As described above, according to the present invention, by superimposing the low-concentration base region (28) on the large-signal transistor ( 25 ), the small-signal transistor ( 16 ) and hFE having a high h FE can be obtained. Has the advantage that it can easily coexist with a large signal transistor ( 25 ) having a small size. In addition, since the base of the large signal transistor ( 25 ) is overlapped with the base region (26) having a relatively high impurity concentration, the decrease in Icmax due to conductivity modulation is small, and therefore the advantage that Icmax can be maximized is obtained. Have.
Furthermore, there is an advantage that ASO can be increased by lowering the h FE of the large signal transistor ( 25 ) and that the transistor can be manufactured to have appropriate characteristics as an output stage transistor. And further,
The use of the low-concentration base region (28) also has an advantage that characteristics of both large signals and small signals can be easily controlled.
そしてさらに、大信号トランジスタ(25)の低濃度ベー
ス領域(28)はIIL(20)のウェル領域(23)と共用す
るので、特に製造工程を増大すること無く3種類の素子
を共存できるという利点をも有する。Furthermore, since the low-concentration base region (28) of the large-signal transistor ( 25 ) is shared with the well region (23) of the IIL ( 20 ), there is an advantage that three types of devices can coexist without increasing the manufacturing process. Also has.
第1図は本発明を説明するための断面図、第2図A〜D
はその製造方法を説明するための断面図、第3図は従来
例を説明するための断面図、第4図は従来の不純物濃度
分布を示す図、第5図は本願の不純物濃度分布を示す図
である。FIG. 1 is a sectional view for explaining the present invention, and FIGS. 2A to 2D.
Is a cross-sectional view for explaining the manufacturing method thereof, FIG. 3 is a cross-sectional view for explaining a conventional example, FIG. 4 is a view showing a conventional impurity concentration distribution, and FIG. 5 is a impurity concentration distribution of the present application. It is a figure.
Claims (1)
タキシャル層を形成する工程、前記エピタキシャル層の
表面に一導電型の不純物をイオン注入し、所望深さに拡
散して大信号トランジスタ用の低濃度ベース領域とIIL
のウェル領域を形成する工程、 前記エピタキシャル層の表面に一導電型の不純物を選択
的に拡散し、小信号トランジスタ用のベース領域、前記
大信号トラジスタ用の前記低濃度ベース領域より浅くこ
れと重畳し前記低濃度ベース領域よりは高い不純物濃度
を有するベース領域、およびIILのインジェクタ領域と
外部ベース領域を形成する工程、 逆導電型の不純物を選択的に導入し、前記小信号トラン
ジスタのベース領域表面にミエミッタ領域を、前記大信
号トランジスタの低濃度ベース領域とベース領域とが重
畳する部分にエミッタ領域を、前記IILのウェル領域表
面にコレクタ領域を形成する工程、 とを具備することを特徴とする半導体集積回路の製造方
法。1. A large signal transistor in which a step of forming an epitaxial layer of opposite conductivity type on a semiconductor substrate of one conductivity type is carried out, impurities of one conductivity type are ion-implanted into the surface of the epitaxial layer and diffused to a desired depth. Low concentration base region and IIL
A well region of the epitaxial layer is selectively diffused into the surface of the epitaxial layer, and is shallower than the base region for the small-signal transistor and the low-concentration base region for the large-signal transistor. A step of forming a base region having an impurity concentration higher than that of the low-concentration base region, and an injector region and an external base region of IIL, selectively introducing an impurity of a reverse conductivity type, and a surface of the base region of the small signal transistor. And a collector region on the surface of the well region of the IIL, wherein the emitter region is formed in a portion where the low-concentration base region and the base region of the large signal transistor overlap each other, and the collector region is formed on the well region surface of the IIL. Manufacturing method of semiconductor integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2171522A JPH07123140B2 (en) | 1990-06-28 | 1990-06-28 | Method for manufacturing semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2171522A JPH07123140B2 (en) | 1990-06-28 | 1990-06-28 | Method for manufacturing semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0461268A JPH0461268A (en) | 1992-02-27 |
| JPH07123140B2 true JPH07123140B2 (en) | 1995-12-25 |
Family
ID=15924679
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2171522A Expired - Lifetime JPH07123140B2 (en) | 1990-06-28 | 1990-06-28 | Method for manufacturing semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07123140B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6566217B1 (en) | 1996-01-16 | 2003-05-20 | Mitsubishi Denki Kabushiki Kaisha | Manufacturing process for semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS502477A (en) * | 1973-05-07 | 1975-01-11 | ||
| JPS6439054A (en) * | 1987-08-04 | 1989-02-09 | Sanyo Electric Co | Semiconductor integrated circuit |
-
1990
- 1990-06-28 JP JP2171522A patent/JPH07123140B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0461268A (en) | 1992-02-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4826780A (en) | Method of making bipolar transistors | |
| US4780425A (en) | Method of making a bipolar transistor with double diffused isolation regions | |
| US4564855A (en) | High current PNP transistor forming part of an integrated monolithic circuit | |
| US5652153A (en) | Method of making JFET structures for semiconductor devices with complementary bipolar transistors | |
| EP0792514B1 (en) | Method of making an integrated circuit with complementary isolated bipolar transitors | |
| JP3443069B2 (en) | Method for manufacturing semiconductor device | |
| JPH07111975B2 (en) | Semiconductor integrated circuit and manufacturing method thereof | |
| JPS63175463A (en) | Bi-MOS integrated circuit manufacturing method | |
| JP2777054B2 (en) | Semiconductor device | |
| JPH0499328A (en) | bipolar transistor | |
| NL194711C (en) | Semiconductor device with a lateral pnp transistor and a vertical pnp transistor. | |
| JP3135615B2 (en) | Semiconductor device and manufacturing method thereof | |
| WO1994027324A1 (en) | A lateral bipolar transistor with variable base width and a method for controlling the base width | |
| JP2604793B2 (en) | Semiconductor device | |
| JPH0834244B2 (en) | Semiconductor integrated circuit device | |
| JPH02276271A (en) | Bipolar/CMOS semiconductor device and its manufacturing method | |
| JPH06283544A (en) | Horizontal type bipolar transistor having small leakage current in direction of substrate | |
| JPH01187868A (en) | semiconductor equipment | |
| JPH0461268A (en) | Integrated circuit device and manufacture thereof | |
| JPH05315549A (en) | Semiconductor device | |
| JPH067582B2 (en) | Semiconductor integrated circuit | |
| JPS58212171A (en) | Semiconductor device | |
| JPH0834214B2 (en) | Method for manufacturing semiconductor device | |
| JPS6092674A (en) | Constant voltage diode | |
| JPS6267855A (en) | Semiconductor injection integrated logic circuit device |