JPH07123760A - Motor controller - Google Patents

Abstract

PURPOSE:To obtain a motor controller which can control the speed of a motor with a simple and inexpensive constitution and can obtain a sufficiently strong start torque. CONSTITUTION:A motor controller is provided with pulse shifting sections 11 and 12 which successively shift pulses in accordance with clock pulses, a soft start bit generating section 2 which inputs data signals to the sections 11 and 12 upon receiving a start signal and successively expands the width of the data signals by adding the signals shifted by the sections 11 and 12 to the data signals as soft start bits, and a motor control section 6 which controls the turn on/off of the conducting circuit of a motor 8 in accordance with the pulses outputted from the sections 11 and 12. It is also possible to incorporate slow-down bit generating sections 3 and 4 which successively narrow the width of the data signals by adding the signals shifted by the sections 11 and 12 to the data signals as slow-down bits in the motor controller.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motor control device capable of so-called soft start and slow down, and is applicable as a control device for, for example, an induction motor for driving a movable rack.

[0002]

2. Description of the Related Art Among various motors, induction motors are widely used because of their simple structure and low cost. For example, an induction motor is also used as a drive source for an electric mobile shelf or an electric trolley. In these electric mobile shelves and electric carts, from the viewpoint of safety of other things such as prevention of falling of stored items, and from the viewpoint of ensuring accuracy of stop position,
A so-called soft start for slow starting is required, and a so-called slow down stop for slowing down and stopping slowly is required.

However, since the induction motor has a characteristic of rotating at a constant speed according to the frequency of the AC power supply, when it is necessary to convert the rotation speed, the pole number variable system or the frequency of the input power supply is used. Inverter control system is used for conversion. Further, in the case of a wound-type induction motor, there is also one in which speed control is performed by changing the resistance put in the rotor winding.

[0004]

In the conventional motor, especially the induction motor, there are the variable pole number method, the inverter control method, the variable resistance method, etc. in order to make the rotation speed variable as described above. Whichever method is used, there is a problem that the device becomes a large-scale device and the cost becomes high. Also,
In either drive system, a sufficient starting torque cannot be obtained, and in a drive system such as an electric moving rack or an electric trolley that is constantly under a constant load, an excessively large capacity motor is required. It was a factor of high.

The present invention has been made in order to solve the above-mentioned problems of the prior art. It is possible to control the speed of the motor with a simple and inexpensive structure and to obtain a sufficient starting torque. It is an object of the present invention to provide a motor control device capable of performing

[0006]

The invention according to claim 1 is
A data signal by inputting a data signal to the pulse shift unit by a start signal and a pulse shift unit that sequentially shifts pulses according to a clock pulse, and adding the signal shifted by the pulse shift unit to the above data signal as a soft start bit. It has a soft start bit generation unit that gradually increases the width, and a motor control unit that controls on / off of the energizing circuit to the motor according to the output pulse of the pulse shift unit.

According to a second aspect of the present invention, a pulse shift section for sequentially shifting pulses according to a clock pulse, and a signal shifted by the pulse shift section by inputting a slowdown signal are added as slowdown bits to the data signal to obtain data. It has a slow down bit generation unit that sequentially narrows the signal width, and a motor control unit that controls on / off of the energizing circuit to the motor according to the output pulse of the pulse shift unit.

According to a third aspect of the invention, when the data signal is narrowed to a certain width by the slowdown bit,
A slowdown creeping speed maintaining unit for maintaining the data signal width and maintaining the creeping speed is added to the invention according to claim 2.

[0009]

According to the first aspect of the present invention, the data signal is input to the pulse shift unit when the start signal is input, and the pulse shift unit sequentially shifts the output pulse according to the clock pulse. The shifted signal is added to the above data signal as a soft start bit by the soft start bit generation unit to sequentially widen the data signal width. As a result, the output pulse width of the pulse shift unit also gradually increases, so that the on-time width of the motor control unit controlled by the output pulse sequentially increases, and the motor speed sequentially increases, so-called soft start is performed.

According to the second aspect of the present invention, when the slowdown signal is input while the motor is being driven, the slowdown bit generating section uses the signal shifted by the pulse shift section as the slowdown bit. To narrow the data signal width in sequence. As a result, the output pulse width of the pulse shift section also gradually narrows, so the on-time width of the motor control section controlled by this output pulse sequentially narrows, and the motor speed gradually slows down, so-called slowdown is performed.

According to the third aspect of the invention, when the data signal is narrowed to a certain width by the slowdown bit,
Since the slowdown creep speed maintaining unit maintains the data signal width, the motor speed is also maintained at a constant creep speed.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a motor control device according to the present invention will be described below with reference to the drawings. In FIG. 1, reference numeral 1 indicates a flip-flop circuit, and reference numeral 2,
Reference numerals 3, 4 and 5 denote gate circuits, respectively. Gate circuit 2
Has an AND circuit 16 and an OR circuit 18. The gate circuit 3 has an OR circuit 20, an AND circuit 22, and an inverter 24. The gate circuit 4 includes an OR circuit 26 and an AND circuit 28.
Have. The gate circuit 5 is a NOR circuit 30 and an AND circuit 3.
2. Has an OR circuit 34. A start / stop signal and a slowdown signal are input as command signals from the outside.

The start / stop signal is input to the AND circuit 32 of the gate circuit 5, and the inverted signals of the start / stop signal from the inverter 14 are input to the shift registers 11 and 12 and the clear terminal of the flip-flop circuit 1, respectively. The slowdown signal is differentiated by the differentiating circuit 48 and input to the OR circuit 20 of the gate circuit 3. The slowdown signal is also inverted by the inverter 46 and input to the AND circuit 16 of the gate circuit 2, the OR circuit 26 of the gate circuit 4, and the NOR circuit 30 of the gate circuit 5, respectively.

Reference numeral 7 indicates a clock pulse generation circuit. The clock pulse generation circuit 7 rectifies a commercial AC power supply, for example, AC100V by a diode 36, blinks the light emitting diode 38 by the pulsation after the rectification, receives the blinking light by a light receiving element 40, and outputs the output of the light receiving element 40. By inputting to the Schmitt trigger circuit 42,
Generates a clock pulse with the same cycle as the cycle of the commercial AC power supply. This clock pulse is input to the clock pulse terminals of the flip-flop circuit 1 and the two shift registers 11 and 12, respectively.

The inverted output of the flip-flop circuit 1 is input to the OR circuit 18 of the gate circuit 2. The outputs Q1, Q2, Q3 and Q4 of the shift register 11 are all input to the NOR circuit 30 of the gate circuit 5, the output Q3 is to the OR circuit 26 of the gate circuit 4, and the output Q4 is the AND circuit of the gate circuit 4. It is input to the circuit 28. Shift register 1
Q1 of the outputs Q1, Q2, Q3 of 2 is the gate circuit 3
In the AND circuit 22, the Q2 is input to the AND circuit 16 of the gate circuit 2, and the Q3 is input to the OR circuit 18 of the gate circuit 2, and is inverted by the inverter 50, and the zero cross type solid state relay 6 (hereinafter referred to as “SSR”).
6 ”).

The output of the AND circuit 16 of the gate circuit 2 is input to the OR circuit 18, and the output of the OR circuit 18 is input to the data input terminal of the shift register 11 as the output of the gate circuit 2. The output of the AND circuit 22 of the gate circuit 3 is input to the OR circuit 20, and the output of the OR circuit 20 is input to the AND circuit 22 and inverted by the inverter 24, and then the output of the gate circuit 3 is output as the AND circuit of the gate circuit 4. 28 is input. AND circuit 28 of gate circuit 4
Of the shift register 12 as the output of the gate circuit 4.
Input to the data input terminal of. The output of the NOR circuit 30 of the gate circuit 5 and the output of the AND circuit 32 are input to the OR circuit 34, the output of the OR circuit 34 is input to the AND circuit 32, and the OR circuit 26 of the gate circuit 4 is output as the output of the gate circuit 5. Entered in.

The SSR 6 is of a phototransistor coupler insulation type and constitutes a motor control section for controlling on / off of a current-carrying circuit for the motor 8 using AC100V as a power source, and a pulse signal is outputted from an output Q3 of the shift register 12. The output causes the energizing circuit to turn on. The motor 8 is, for example, a moving rack drive motor, and an inertial load 9 is applied thereto. The motor 8 is a two-phase induction motor here.

Next, the operation of the above embodiment will be described with reference to FIGS.
Will also be described with reference to. First, referring to FIG. 2, the relationship between the operation of the SSR 6 and the motor rotation speed when the start / stop signal and the slowdown signal are input in the above embodiment will be schematically described. First, when the start / stop signal is "H", that is, when the start signal is input, the SSR6 is turned on / off at a constant cycle in synchronization with the sine waveform of AC100V. The number of pulses increases by one pulse in synchronism with the cycle, and eventually the ON state is maintained and the steady state is settled. Along with this, the rotation speed of the motor 8 gradually and linearly rises without suddenly rising, and eventually stabilizes at a constant rotation speed. Therefore, the motor 8 is what is called a soft start.

When the motor 8 is rotating at a constant speed,
When the slowdown signal is input, SSR6 turns AC10
It turns on and off at a constant cycle in synchronization with the 0 V sine waveform, and the on pulse width decreases by one pulse in synchronization with one cycle of the sine wave, and eventually settles to a constant pulse width. Along with this, the rotation speed of the motor 8 is not linearly decelerated but is linearly decelerated slowly, and eventually settles to a constant creep speed. Therefore, the motor 8 slows down. After that, when the start / stop signal is “L”, that is, when the stop signal is input, S
SR6 is turned off and the motor 8 is stopped.

The above operation will be described in more detail. Before the start signal is input, two shift registers 1
“H” is input to the clear terminals of the flip-flop circuits 1 and 12. Therefore, as is apparent from FIG. 9, the outputs of the shift registers 11 and 12 are all "L",
The inverted output of the flip-flop circuit 1 becomes "H" and all operations are stopped. Further, the above-mentioned output of the flip-flop circuit 1 is input to the data input terminal of the shift register 11 via the gate circuit 2 as it is as an “H” signal.

Now, when the start signal is inputted, this signal becomes an inverted signal "L" in the inverter 14 and inputted to the shift registers 11 and 12 and the clear terminals of the flip-flop circuit 1, respectively. Circuit 1 starts operation. Since the "H" signal is input to the data input terminal of the shift register 11 as described above, "H" is set in the shift register 11 at the rising edge of the clock pulse. On the other hand, in the flip-flop circuit 1, after the signal "L" is input to the clear terminal, the output becomes "L" at the next rising edge of the clock pulse and is maintained as it is. Therefore, due to the characteristics of the shift register, the outputs Q1, Q2, Q of the shift register 11 are
3 and Q4 are "H", "L", "L", and "L", respectively. After that, the output signal of the flip-flop circuit 1 becomes "L" as described above, so "L" is input to the data input terminal of the shift register 11, and due to the characteristics of the shift register, a signal is input for each clock pulse input. “H” shifts to the output terminal Q4 (see FIG. 9).

Here, the "H" signal is always output from the gate circuit 3, and the gate circuit 4 is supplied from the slow-down input terminal.
Since the "H" signal is always input also to, a circuit equivalent to the output Q4 of the shift register 11 being directly input to the data input terminal of the shift register 12 is obtained from the logical operation in the gate circuit 4. Therefore, the "H" signal that has been shifted to the output Q4 in the shift register 11 is the gate circuit 4
It is input to the data input terminal of the shift register 12 via (see FIG. 7).

Here, paying attention to the gate circuit 2, since the input from the flip-flop circuit 1 is always "L" and the input from the slowdown input terminal is always "H", the gate circuit 2 is shifted by a logical operation. Output Q of register 12
The circuit is the same as the OR circuit that inputs 2, Q3. Therefore, when the signal "H" shifts to Q2, the signal "H" is input to the data input terminal of the shift register 11 due to the characteristics of the gate circuit 2, and one signal "H" is input in this pulse cycle. It has been added. The signal "H" shifted to the output Q3 of the shift register 12 is directly input to the data input terminal of the shift register 11 via the gate circuit 2 (see FIG. 5). In this way, the signal "H" generated by the output Q3 of the shift register 12 and passing through the gate circuit 2 continues to rotate by shifting the seven pulse outputs of the two shift registers 11 and 12.

Further, when the output Q2 of the shift register 12 changes from "L" to "H", a signal "H" is input to the data input terminal of the shift register 11 due to the characteristics of the gate circuit 2, and One signal "H" is added to the seven pulse outputs, and the width of the signal "H" input to the data input terminal is widened by one pulse. By repeating the operation when the output Q2 of the shift register 12 changes to "H" and the two operations when the output Q3 changes to "H", the shift register 11
Outputs Q1, Q2, Q3, Q4 and shift register 1
The pulse width for shifting the respective outputs Q1, Q2, Q3 of No. 2 sequentially expands by one pulse, and eventually all seven outputs become "H".

The output Q3 of the shift register 12 is input to the SSR6 via the inverter 50, and the output Q3 turns on the energizing circuit for the SSR6, that is, the motor 8.
Since the off control is performed, the motor 8 is slowly started at the beginning of the start, the speed gradually increases, and eventually reaches the steady rotation speed. Thus, a so-called soft start is performed.

Next, when the slowdown signal is input during the steady rotation of the motor 8 (the slowdown signal becomes "H"), the inverted signal "L" by the inverter 46 is supplied to the gate circuits 2, 4 and 5. In addition to being input, the differential output of the slowdown signal by the differentiating circuit 48 is input to the gate circuit 3. The output of the differentiating circuit 48 becomes "H" for a moment at the rising edge of the slowdown signal and then becomes "L". Since the input Q1 from the output Q1 of the shift register 12 to the gate circuit 3 is "H", the logical operation of the gate circuit 3 indicates that the output of the gate circuit 3 and the input of the gate circuit 4 are temporarily "L". After that, it becomes “H” (see FIG. 6B). In the gate circuit 4, the input from the shift register 11 is "H", and the inputs from the gate circuit 5 and the slowdown input terminal are "L". Therefore, when a logical operation is performed, the output is until the next clock pulse rise. It becomes “L” (see FIG. 7B), this signal is input to the shift register 12, and the slowdown operation is started. After that, the signal "L" is shifted to the output Q3 due to the characteristics of the shift register.

Next, paying attention to the gate circuit 2, since the signals from the flip-flop circuit 1 and the slow-down input terminal are always "L", the output Q of the shift register 12
The circuit is equivalent to a circuit in which 3 and the data input terminal of the shift register 11 are directly connected. Therefore, the signal "L" reaching the output Q3 of the shift register 12 is directly input to the data input terminal of the shift register 11. Similarly, in the shift register 11, the signal "L" is shifted to the output Q4 due to the characteristics of the shift register. Focusing on the gate circuit 5 at this time, since the start / stop input is always "H", the signal "L" is continuously output by the logical operation regardless of other inputs (see FIG. 8B).

Next, paying attention to the gate circuit 4, the input from the gate circuit 3 is "H", and the other inputs other than the shift register 11 are "L". Therefore, this is a circuit equivalent to an AND circuit that receives the outputs Q3 and Q4 of the shift register 11. As a result, when the signal "L" reaches the output Q3 of the shift register 11, it is input to the shift register 12 via the gate circuit 4. Therefore, one signal “L” is added to the seven pulse periods in the two shift registers 11 and 12. Thereafter, the signal "L" is added to the pulse period one by one, and the width of each pulse to be shifted is sequentially narrowed by one pulse. When attention is paid to the gate circuit 5 when the number of the signals "L" becomes four, the outputs Q1 and Q of the shift register 11
When 2, Q3 and Q4 all become "L", the output is held at "H" due to the logical operation in the gate circuit 5 no matter what signal is input thereafter. Therefore, performing a logical operation in the gate circuit 4 under this condition is equivalent to directly connecting the output Q4 of the shift register 11 and the data input terminal of the shift register 12. Therefore, after that, the two shift registers 11 and 12 are continuously shifted with the same pulse period and the same pulse width, and this state is maintained.

As described above, the output Q3 of the shift register 12 controls on / off of the energizing circuit to the SSR 6, that is, the motor 8, so that the pulse width of the output Q3 is gradually narrowed by the input of the slowdown signal. The rotation speed of the motor 8 is gradually decreased to perform so-called slowdown. When the rotation speed is decreased to a certain speed, the pulse width of the output Q3 becomes constant and the motor 8 is kept at a low speed and a constant rotation speed.

Start / start in the above low speed rotation state
When the stop signal is “L”, that is, when the stop signal is input, the inverted signal “H” of the inverter 14 is input to the shift registers 11 and 12 and the clear terminals of the flip-flop circuit 1. From the characteristics of the shift register,
The outputs of the shift registers 11 and 12 are all "L",
All operations including the motor 8 are stopped.

As can be seen from the above description, the shift registers 11 and 12 form a pulse shift unit that sequentially shifts output pulses according to clock pulses when a data signal is input. The gate circuit 2 inputs the data signal to the pulse shift section by the start signal and adds the signal shifted by the pulse shift section to the above data signal as a soft start bit to generate a soft start bit to sequentially widen the data signal width. Make up part. The gate circuits 3 and 4 configure a slowdown bit generation unit that sequentially narrows the data signal width by adding the signal shifted by the pulse shift unit by the input of the slowdown signal to the data signal as a slowdown bit. . When the data signal is narrowed to a certain width by the slow down bit, the gate circuit 5
A slowdown creep speed maintaining unit that maintains the data signal width and maintains the creep speed is configured.

According to the above embodiment, the motor 8 is soft-started by the input of the start signal, the rotation of the motor 8 is gradually decelerated by the input of the slowdown signal, and then the motor 8 is kept at a constant low speed, and the stop signal is input. For example, when the motor 8 is used as a drive source for the moving rack, the moving rack slowly starts and slowly stops, so that it is possible to prevent accidents due to falling of stored items, and stopping the moving rack. Positional accuracy can be improved.

In the illustrated embodiment, the motor 8 is a single-phase induction motor, but it is not limited to this and may be, for example, a single-phase reversible motor. Further, the present invention is applicable not only to the AC motor but also to the DC motor, and not only to the rotary motor but also to the linear motor. Further, although the logical operation circuit is used in the illustrated embodiment, it may be controlled by software using a computer.

[0034]

According to the invention described in claim 1, the motor can be soft-started, and according to the invention described in claim 2, the speed of the motor can be gradually reduced, so that the motor can be slowly reduced. It is possible to mitigate a sudden impact at the time of starting or stopping, and it is possible to smoothly perform the operation of the object to be driven by the motor. Furthermore, when the motor is used as a drive source for the movable rack as in the invention described in claim 4, the movable rack can be slowly started and slowly stopped, so that accidents due to falling of stored items can be prevented. It is possible to improve the stop position accuracy of the moving shelf.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a motor control device according to the present invention.

FIG. 2 is a timing chart showing an outline of the operation of the above embodiment.

FIG. 3 is a timing chart showing the operation of each part at the start of the above embodiment.

FIG. 4 is a timing chart showing the operation of each unit during slowdown in the above embodiment.

FIG. 5 is a circuit diagram of one gate circuit in the above embodiment and a diagram showing a truth value of its operation.

FIG. 6 is a circuit diagram of another gate circuit in the above embodiment and a diagram showing a truth value of its operation.

FIG. 7 is a circuit diagram of still another gate circuit and a diagram showing a truth value of its operation.

FIG. 8 is a circuit diagram of still another gate circuit and a diagram showing a truth value of its operation.

FIG. 9 is a diagram showing a truth value of the operation of the shift register in the above embodiment.

[Explanation of symbols]

 2 Soft start bit generation unit 3 Slow down bit generation unit 4 Slow down bit generation unit 5 Slow down creep speed maintenance unit 8 Motor 11 Pulse shift unit 12 Pulse shift unit SSR Motor control unit

Claims (4)

[Claims] 1. A pulse shift unit for sequentially shifting pulses according to a clock pulse, a data signal is input to the pulse shift unit by a start signal, and the signal shifted by the pulse shift unit is added to the data signal as a soft start bit. By doing so, a motor control device comprising a soft start bit generation section for sequentially increasing the data signal width, and a motor control section for performing on / off control of the energizing circuit to the motor according to the output pulse of the pulse shift section. 2. A pulse shift unit for sequentially shifting pulses according to a clock pulse, and a slow shift signal for adding a signal shifted by the pulse shift unit to the data signal as a slow down bit to sequentially narrow the data signal width. A motor control device comprising a down-bit generation unit and a motor control unit that controls on / off of a current-carrying circuit to the motor according to an output pulse of a pulse shift unit. 3. The slow down creep speed maintaining unit for maintaining the creep speed by maintaining the data signal width when the data signal is narrowed to a certain width by the slow down bit. Motor control device. 4. The motor control device according to claim 1, wherein the motor is a moving rack drive motor.