JPH07129272A - Clock speed control circuit - Google Patents

Abstract

(57) [Summary] [Object] To provide a clock speed control circuit for varying the processing speed per unit time of a logic circuit and achieving low power consumption suitable for the required processing speed. [Structure] An oscillator circuit 1 outputs a clock 4 having a constant frequency like a crystal oscillator circuit, and outputs a clock speed control circuit 2
Controls the clock 4 to generate the operation clock 5, and the logic circuit 3 operates using the operation clock 5. The operation clock 5 is processed by the clock control circuit 2 so as to have a clock duration and a pause. That is,
The number of clock pulses per unit time can be changed according to the processing speed request by using the operation clock as an intermittent clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock speed control circuit for operating a logic system represented by a microcomputer and a digital signal processor (DSP) with low power consumption.

[0002]

2. Description of the Related Art Conventionally, as a method of reducing power consumption of a logic system composed of a CMOS-IC or the like, a technique of switching the frequency of an operation clock according to a processing speed request has been applied. This utilizes the characteristic that the current consumption of the CMOS-IC is proportional to the frequency of the operation clock, and is the basis of low power consumption. Further, the technology for reducing power consumption of a personal computer disclosed in Japanese Patent Laid-Open No. 4-134510 realizes further lower power consumption by switching the power supply voltage in accordance with the switching of the operation clock.

Also, as in Japanese Patent Publication No. 61-48727,
There is a technique of reducing power consumption in a standby state by stopping an operation clock of a logic system.

[0004]

However, when switching the operating clock frequency, 1) a plurality of oscillation circuits are provided in advance, or 2) the output of a single oscillation circuit is divided by a programmable frequency divider, Or 3) A variable frequency oscillator must be used, but in the case of 1), frequency selection cannot be increased due to cost and space problems, and in the case of 2), the selectable frequency is an integer fraction of the fundamental frequency. However, in the case of 3), there is a problem that the frequency accuracy is lowered because the crystal oscillator is not used, and the operating clock frequency cannot completely meet the processing speed requirement.

It is an object of the present invention to provide a clock speed control circuit for varying the processing speed of a logic circuit per unit time and achieving low power consumption suitable for the required processing speed.

[0006]

A clock speed control circuit of the present invention is a clock speed control circuit for receiving the reference clock from an oscillation circuit for outputting a reference clock and supplying an operation clock to a logic circuit. The operation clock includes means for generating the operation clock which is an intermittent clock in which a duration and a pause are repeated at a constant cycle, and means for varying a ratio between the duration and the pause. To do.

Further, the clock speed control circuit includes a first digital value storage circuit for determining the number of continuations,
A second digital value storage circuit for determining the number of pauses may be provided, and the operation of outputting the clock pulse for the number of sustains and not outputting the clock pulse for the number of pauses may be repeated.

Further, the first digital value storage circuit and the second digital value storage circuit may be written by the logic circuit.

Further, the clock speed control circuit may start the duration period in synchronization with a timing clock having a cycle longer than the reference clock, and may start the pause period by a pause pulse generated by the logic circuit. Good.

Further, the timing clock is a sampling clock of a digital signal, and the logic circuit performs digital signal processing in each sampling period, outputs a pause pulse to the clock speed control circuit after completion of unit processing, and The operation may be suspended until the sampling period.

[0011]

As described above, the number of clock pulses per unit time can be varied by controlling the ratio of the clock duration and the idle period by using the operation clock that determines the processing speed of the logic circuit as an intermittent clock. The same effect as the conventional technology that controls the power consumption by the clock frequency can be obtained, and furthermore, an arbitrary processing speed can be obtained by using a single frequency oscillation circuit, so it is possible to completely follow the changes in the processing speed demand. Can achieve the minimum power consumption.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A description will be given below with reference to the block diagram of FIG. 1 and the timing diagram of FIG. The oscillator circuit 1 outputs a clock 4 having a constant frequency like a crystal oscillator circuit, the clock speed control circuit 2 controls the clock 4 to generate an operation clock 5, and the logic circuit 3 uses the operation clock 5. Take action. The clock speed control circuit uses the operation clock as an intermittent clock and changes the number of clock pulses per unit time according to the processing speed request. The operation clock 5 is, for example, a waveform 8 by the clock speed control circuit 2.
And processed as indicated by waveform 9. Waveform 8 is 100
This is for obtaining a processing speed of%, which is similar to the conventional clock waveform. Waveform 9 is for trying to obtain a processing speed of 75%, and repeats the clock duration and rest periods at a ratio of 3: 1.

A first embodiment of the clock speed control circuit will be described below with reference to FIG. Clock signal 115
Is the input of the hexadecimal counters 105 and 106, the inverter 1
It is supplied to the input of 10 and the input of the AND gate 114. The reset inversion signal 116 is the memory circuit 10
It is supplied to the reset input of 0, the reset input of the hexadecimal counters 105 and 106, the input of the inverter 107, and the reset input of the D flip-flop 113.
The write signal 117 is supplied to the input of the memory circuit 100. The 4-bit data 118 is supplied to the storage circuit 100.

The output of the inverter 107 is the NOR gate 1
It is connected to 12 inputs. The output of the inverter 110 is connected to the clock input of the D flip-flop 113. D (1), D (2), D of the memory circuit 100
Outputs (4) and D (8) are hexadecimal counter 1 respectively.
05 D (1), D (2), D (4), D (8) inputs. D (1), D of the memory circuit 100
The (2), D (4), and D (8) outputs are connected to the inputs of the inverters 103, 101, 104, and 102, respectively. The outputs of the inverters 103, 101, 104 and 102 are D (1) of the hexadecimal counter 106,
It is connected to the D (2), D (4) and D (8) inputs.

Carry signal 12 of hexadecimal counter 105
0 is connected to the input of the AND gate 109. 16
The carry signal 121 of the advance counter 106 is connected to the input of the inverter 108 and the input of the NOR gate 112. The output of the inverter 108 is connected to the input of the AND gate 109. The output 122 of the AND gate 109 is connected to the input of the NOR gate 111. The output 123 of the NOR gate 111 is connected to the input of the NOR gate 112, the D input of the D flip-flop 113, and the LOAD input of the hexadecimal counter 105. The output 124 of the NOR gate 112 is the input of the NOR gate 111 and the L of the hexadecimal counter 106.
Connected to OAD input. D flip-flop 11
The output 125 of 3 is connected to the input of the AND gate 114. The AND gate 114 outputs the clock signal 119.

The clock speed control circuit configured as described above operates as follows. The memory circuit 100 stores the 4-bit data 118 at the rising edge of the write signal 117. The output of the memory circuit 100 is used as an initial value of the hexadecimal counter 105. The output of the memory circuit 100 is inverted by inverters 101, 102, 103 and 104 to 1
It is used as an initial value of the hexadecimal counter 106. The hexadecimal counters 105 and 106 set the carry signals 120 and 121 to the high level when the stored value becomes 15. The carry signal 120 and the carry signal 121 inverted by the inverter 108 are input to the AND gate 109.
Output signal 122 of AND gate 109 and NOR gate 1
The output signal 124 of 12 is input to the NOR gate 111. The output signal 123 and the carry signal 121 of the NOR gate 111 are input to the NOR gate 111. Traffic light 12
When 3 is low level, the hexadecimal counter 105 stores the initial value at the rising edge of the clock signal 115, and when the high level is 3, adds 1 to the value stored at the rising edge of the clock signal 115. When the signal 124 is low level, the hexadecimal counter 106 stores the initial value at the rising edge of the clock signal 115, and when the signal 124 is high level, adds 1 to the value stored at the rising edge of the clock signal 115. The signal 123 is the D flip-flop 1 at the falling edge of the clock signal 115.
13 is stored. The output signal 125 of the D flip-flop 113 and the clock signal 115 are input to the AND gate 114. The output signal 119 of the AND gate 114 is the operation clock of the present invention.

When the reset signal 116 is set to the low level, all the values in the memory circuit 100 are 0, and the hexadecimal counter 10
The values of 5 and 106 are all 0, the output signal 124 of the NOR gate 112 is low level, the value of the D flip-flop is 0,
The output signal 119 is reset to the clock signal 1
A continuous clock waveform similar to 15 appears. continue,
When the reset signal 116 is set to the high level, the memory circuit 10
The data can be written to 0. When a set value is given to the data 118 and the write signal is changed from the low level to the high level, the output signal 119 becomes an intermittent clock in which the N clock duration and the M clock pause are repeated as shown in Table 1.

[0018]

[Table 1]

When the output signal 119 is used as an operating clock of a microprocessor, the operating speed is 1/15.
The resolution can be set. Also, write signal 1
It is also possible to provide 17 and data 118 from a microprocessor operated by the output signal 119.

A second embodiment will be described with reference to FIG. The clock signal 210 is supplied to the clock input of the hexadecimal counter 202, the clock input of the D flip-flop, the input of the inverter 205, and the input of the AND gate 209. The inverted signal 211 of the reset is supplied to the reset input of the memory circuit 200, the reset input of the hexadecimal counter 202, the reset inputs of the D flip-flops 201 and 208, and the input of the inverter 203. The write signal 212 is supplied to the memory circuit 200. The 8-bit data is supplied to the storage circuit 200. The pause signal 214 is connected to the D input of the D flip-flop. The data output of the storage circuit 200 is connected to the data input of the hexadecimal counter 202.

Carry signal 21 of hexadecimal counter 202
7 is the input of the inverter 204 and the NOR gate 2
06 input. The output of the inverter 204 is connected to the LOAD input of the hexadecimal counter. The output of the inverter 203 is connected to the input of the NOR gate 207. The output of NOR gate 207 is connected to the input of NOR gate 206. The output 218 of the D flip-flop 201 is connected to the input of the NOR gate 207. The output of the NOR gate 206 is the input of the NOR gate 207 and the D of the D flip-flop 208.
Connected to input. The output of the D flip-flop 208 is connected to the input of the AND gate 209. AN
The D gate 209 outputs the clock signal 215.

The clock speed control circuit configured as described above operates as follows. The memory circuit 200 stores the 8-bit data 213 at the rising edge of the write signal 212. The 8-bit value of the memory circuit 200 is the hexadecimal counter 20.
Used as an initial value of 2. The hexadecimal counter 202 sets the carry signal 217 to the high level when the stored value becomes 255. The carry signal 217 is the inverter 2
It is inverted at 04 to become the signal 216. Hex counter 20
2 is the clock signal 210 when the signal 216 is low level
The initial value is stored at the rising edge of the clock signal 216 and 1 is added to the value stored at the rising edge of the clock signal 216 when it is at a high level. Therefore, the generation cycle of the carry signal 217 is (256−initial value) Doubled. The signal 217 and the output signal of the NOR gate 207 are input to the NOR gate 206. Pause signal 2 given from the outside
14 is a clock signal 210 for the D flip-flop 201.
Memorized at the start of. The output signal 219 of the NOR gate 206 and the output signal 21 of the D flip-flop 201
8 is input to the NOR gate 207. Signal 219
Is stored in the D flip-flop 208 at the falling edge of the clock signal 210. The output signal 220 of the D flip-flop 208 and the clock signal 210 are the AND gate 20
9 is input. Output signal 215 of AND gate 209
Is the operating clock of the present invention.

When the reset signal 211 is set to the low level, the values of the memory circuit 200 are all 0, and the hexadecimal counter 20
When the value of 2 is all 0, the output signal of the NOR gate 207 is low level, the value of the D flip-flop 201 is 0, and the value of the D flip-flop 208 is 0, the output signal 215 is the same as the clock signal 210. The continuous clock waveform of appears. Then, when the reset signal 211 is set to the high level, the output signal 215 can be stopped at the low level state by the stop signal 214. Rest signal 21
4 is a pulse that becomes high level for one clock cycle.
The pause period continues until the carry signal 217 becomes high level. A set value is given to the data 213 and the write signal 21
When 2 is changed from low level to high level, data can be written in the memory circuit 200 and the cycle of the carry signal 217 can be set.

The output signal 215 is used, for example, as an operating clock of the digital signal processor, and the pause signal 21 is used.
4 is configured to be generated by the digital signal processor after the completion of the unit processing, the unit processing and the operation clock pause can be repeated at a cycle of an integral multiple of the clock signal 210.

[0025]

The clock speed control circuit of the present invention is a clock speed control circuit for receiving the reference clock from the oscillation circuit for outputting the reference clock and supplying the operation clock to the logic circuit. Since a unit for generating the operation clock, which is an intermittent clock that repeats a duration period and a rest period at a fixed cycle, and a unit for varying the ratio of the duration period and the rest period, are provided, And a clock speed control circuit for achieving low power consumption suitable for a required processing speed.

[Brief description of drawings]

FIG. 1 is a simple block diagram of the present invention.

FIG. 2 is a timing diagram for explaining a clock waveform of the present invention.

FIG. 3 is a block diagram showing a first embodiment.

FIG. 4 is a block diagram showing a second embodiment.

[Explanation of symbols]

 101-104,107,108,110 Inverter 109,114 AND gate 111,112 NOR gate 113 D flip-flop

Claims (5)

[Claims] 1. A clock speed control circuit for receiving the reference clock from an oscillation circuit for outputting the reference clock and supplying the operation clock to a logic circuit, wherein the operation clock has a constant period and a pause period. A clock speed control circuit comprising: a means for generating the operation clock, which is an intermittent clock for repeating the above steps; and a means for varying the ratio of the sustain period and the pause period. 2. The clock speed control circuit comprises a first digital value storage circuit for determining the number of sustains and a second digital value storage circuit for determining the number of rests, and only the number of sustains is provided. The clock speed control circuit according to claim 1, wherein the operation of outputting the clock pulse and repeating the operation of not outputting the clock pulse for the number of pauses is repeated. 3. The clock speed control circuit according to claim 2, wherein the first digital value storage circuit and the second digital value storage circuit are written by the logic circuit. 4. The clock speed control circuit starts the duration period in synchronization with a timing clock having a cycle longer than that of the reference clock, and starts the pause period by a pause pulse generated by the logic circuit. The clock speed control circuit according to claim 1, wherein the clock speed control circuit is a clock speed control circuit. 5. The timing clock is a sampling clock for digital signals, and the logic circuit performs digital signal processing in each sampling period, outputs a pause pulse to the clock speed control circuit after completion of unit processing, and The clock speed control circuit according to claim 4, wherein the operation is suspended until the sampling period.