JPH07141307A - Synchronization circuit for multiprocessor system - Google Patents

Abstract

(57) [Summary] [Object] The present invention provides a synchronization circuit of a multiprocessor system capable of autonomously generating an interrupt signal for a specific processor when another processor is abnormal. According to the present invention, the time counting end pulse Pa of the second timer 22, the logical product of the time counting end pulse Ps of the first timer 21 and the latch output F of the flip-flop 23, and the time counting operation of the second timer 22. The interrupt signal I for the specific processor 11 is obtained by logically adding the logical product of the middle signal Ca and the negation of the synchronization signal SYNC generated by the other processor 12 which is input via the wired or common bus 14.
When the OR gate 24 for outputting as NT, the latch output F of the flip-flop 23, and the clocking operation signal Ca of the second timer 22 are both NO, the OR gate 24
The interrupt signal INT output from the other processor 12
AND gate 25 for outputting to the common bus 14 as a synchronization signal SYNC for the.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing circuit of a multiprocessor system, and more specifically, in a control system having a multiprocessor structure in which a control device is composed of a plurality of processors, each processor executes processing operations. The present invention relates to a synchronizing circuit for synchronizing with each other.

[0002]

2. Description of the Related Art For example, in a multiprocessor control system in which a control device is composed of a plurality of processors, when information generated and processed by a particular processor is to be used by another processor, those processors are used. A so-called dead time may occur in transmitting the information due to the configuration of the program activated by the. Hereinafter, how dead time is generated in a control system of this type of multiprocessor will be described with reference to the drawings.

FIG. 12 is a diagram for explaining how dead time occurs in a control system having a multiprocessor structure in which a control device is composed of two processors. As shown in the figure, for example, the time t of the program A started by the processor PA at regular intervals ts.
_The data generated when ₁ has passed is the program B that is started by the processor PB at the same constant period ts.
When trying to use the elapsed time of the time t ₂ of, if each of the start timings of the processors PA and PB match as shown in the figure, the time td required for transmission of data is necessarily, td = represented by t ₂ -t _1. Here, the times t ₁ and t ₂ relating to the generation and use of the above data can be arbitrarily set to a certain degree by the respective configurations of the programs A and B, so that the dead time td is minimized or becomes a constant value. It is sufficiently possible to prevent the influence of the dead time td on the control system from becoming a problem by performing such management.

However, if the start timings of the programs A and B do not match, the dead time td is naturally indefinite within the range of 0≤td <ts, and if the processors PA and PB are When the start timings of the programs A and B are managed based on the clocks generated from the independent crystal oscillators, it is generally difficult to make the oscillation frequencies of the crystal oscillators exactly match. Therefore, the dead time td also fluctuates temporally due to the deviation of the crystal oscillator. That is, in a control system of this type of multiprocessor configuration, unless special measures are taken, the dead time td in transmitting information is indefinite and fluctuates with time. For example, one control loop In the case where a plurality of processors are to be processed, the existence of this dead time td not only hinders the improvement of the control performance of the system, but also sometimes causes the control system to become unstable.

Therefore, in order to avoid such inconvenience, (a) a hardware interrupt is generated from a specific processor to another processor when transmitting information, and data transmission or reception is requested by this interrupt. Method to synchronize processing, or (b) supply the hardware signal used to activate interrupt processing in a specific processor to other processors, and use the same hardware signal (that is, the same hardware signal). (At the timing of), a method for synchronizing each processor so that each program is started is used.

[0006]

However, in the method (a) of the above two methods, an interrupt only for that purpose must be generated each time information is transmitted, and therefore the interrupt is generated. The software processing overhead associated with the processing imposes a heavy burden on the processor, resulting in a decrease in throughput. Also, in a system configuration in which the operation of a specific processor strongly affects the operation of another processor, the failure of that specific processor directly affects other processors,
From the point of view of system reliability, it is never preferable.

On the other hand, in the method (b), the operation of the hardware of the other processor on the side to which the hardware signal is supplied is completely the same as the operation of the hardware of the specific processor on the side of supplying the hardware signal. , Which results in extremely low system autonomy. Particularly, when an abnormality occurs in the hardware signal, the abnormality directly affects the operation of all the other processors, and thus this method is also problematic in terms of system reliability. In addition, if it is attempted to forcibly synchronize the cycle of another processor that is not synchronized with the cycle of the specific processor, the cycle on the side of the other processor may be transiently greatly changed. If the cycle is transiently greatly shortened, there is a possibility that a predetermined process cannot be completed within the cycle, which causes troubles.

In addition to these problems, for example, in a control system requiring a highly accurate timekeeping operation,
While the function that generates the signal that serves as the reference for timing operation is functioning normally, it is necessary to synchronize the cycle of another processor with the cycle of a specific processor or a dedicated signal. When an abnormality occurs in the dedicated signal cycle, the other processors must autonomously generate the interrupt signal by themselves.

The present invention has been made based on the above-mentioned circumstances, and an object thereof is to synchronize interrupt processing of a plurality of processors with each other without imposing a special burden on software processing. An object of the present invention is to provide a synchronizing circuit of a multiprocessor system capable of autonomously generating an interrupt signal for each processor when the function of generating a reference interrupt signal is abnormal.

[0010]

1 (a) and 1 (b) are block diagrams of the principle of the present invention. The present invention is in a multiprocessor system in which a plurality of processors operate in synchronization with a synchronization signal.

According to a first aspect of the present invention, a fixed-cycle interrupt signal to be synchronized, which is generated by another processor, is input, for example, via a wired or common bus, and at the same time, a clocking operation is started and the fixed cycle is started. A first time measuring means 1 for measuring a time period obtained by subtracting the time limit of the maximum value of the phase advance compensation from the cycle of the interrupt signal, and the time measuring operation is started at the same time when the time measuring operation of the first time measuring means 1 ends. Second time measuring means 2 for measuring the time limit of the maximum value of the phase advance compensation,
If the synchronization signal to be generated by the other processor is not input through the common bus during the timing operation of any of the first and second timing means 1 and 2, the timing operation of the second timing means 2 is performed. If the input is made via the common bus during the timekeeping operation of the second timekeeping means 2 at the time when is finished, at the time of the input, the common bus is sent during the timekeeping operation of the first timekeeping means 1. If the input signal is input as the interrupt signal, the interrupt signal output means 3 for generating an interrupt signal and outputting the interrupt signal to the processor at the time when the clock operation of the first clock means 1 is finished, and a synchronization signal to be generated by another processor. Is the first and second timing means 1,
When no input is made via the common bus during any of the time counting operations of 2, the interrupt signal output means 3 to the second time counting means 2
The interrupt signal output at the time when the timing operation of
It is characterized by comprising a synchronization signal output means 4 for outputting to the common bus as a synchronization signal for another processor.

According to a second aspect of the present invention, there is provided a circuit comprising a first timing means 1, a second timing means 2 and an interrupt signal output means 3, that is, a synchronization signal output means according to the first aspect of the invention. It is characterized in that a series of circuits except 4 are added to the other processor to establish a master-slave relationship of a synchronizing operation among a plurality of processors.

According to the third aspect of the invention, at the same time when the fixed cycle interrupt signal to be synchronized, which is generated by another processor, is input through the common bus, the clocking operation is started and the fixed cycle interrupt signal A first time measuring means 5 for measuring a time period corresponding to a region in which a phase difference should be compensated by a delay operation, and a time measuring operation of the first time measuring means 5 is started at the same time, and the time measuring operation is started at a fixed period. The second timing means 6 for timing the time period corresponding to the region to be compensated by the operation by advancing the phase difference in the period of the interrupt signal, and the timing operation of the second timing means 6 are started at the same time as the timing operation is started. A time period of the maximum value of the phase advance compensation amount obtained by subtracting the time period measured by the first time measuring unit 5 and the time period measured by the second time measuring unit 6 from the period of the fixed cycle interrupt signal; Timekeeping means 7 The fourth timing means 8 for starting the timing operation at the same time as the completion of the timing operation of the third timing means 7 and for timing the maximum value of the phase delay compensation amount and the synchronization to be generated by the other processors. If the activation signal is not input through the common bus during any of the timing operations of the first, second and third timing means (5, 6, 7), the timing operation of the third timing means 7 At the end time, if the input is made via the common bus during the time counting operation of any of the third and fourth time counting means (7, 8), the first time counting means 5 is set at the input time. If the input is made via the common bus during the timekeeping operation of the second timekeeping operation, the input is made via the common bus at the time when the timekeeping operation of the fourth timekeeping means 8 is completed. In this case, an interrupt signal is generated at the time when the time counting operation of the second time counting means 6 ends. The interrupt signal output means 9 for outputting to the processor and the synchronization signal to be generated by the other processor are common bus during the timing operation of any of the first, second and third timing means (5, 6, 7). Synchronization signal for outputting to the common bus an interrupt signal output from the interrupt signal output means at the time when the time counting operation of the third time counting means 7 ends when not input via the common bus The output means 10 is included.

According to a fourth aspect of the present invention, the first time counting means, the second time counting means, the third time counting means, the fourth time counting means (5, 6, 7, 8) and the interrupt signal output means 9 are provided. And a series of circuits excluding the synchronization signal output means 10 of the invention according to claim 3 is added to the other processor to set the master-slave relationship of the synchronization operation between the plurality of processors. It is characterized by being formed.

[0015]

According to the first aspect of the present invention, the interrupt signal output means 3 sends the synchronization signal to be generated by another processor to the first synchronization signal.
If no input is made via the common bus during any one of the timing operations of the second timing means 1 and 2, the second timing means 2
If the input is made via the common bus during the time counting operation of the second time counting means 2 at the time when the time counting operation of the above is finished, it is common during the time counting operation of the first time counting means 1 at the input time. When input through the bus, an interrupt signal is generated and output to the processor at the time when the time counting operation of the first time counting means 1 ends, and the synchronization signal output means 4 causes another When the synchronization signal to be generated by the processor is not input through the common bus during the timekeeping operation of either the first or second timekeeping means 1 or 2, the interrupt signal output means 3 to the second timekeeping means The interrupt signal output at the time when the timing operation of 2 is finished is output to the common bus as a synchronization signal for other processors. As a result, the fixed-cycle interrupt signal to be synchronized by the processor is synchronized with the synchronization signal generated by another processor in the direction of advancing the phase, and the interrupt signal for the processor is interrupted when the other processor is abnormal. Are generated autonomously, and at the same time, supply a synchronization signal to the common bus on behalf of other processors.

According to a second aspect of the present invention, the synchronization circuit according to the first aspect is assigned to the processor, and a series of circuits except the synchronization signal output means 4 according to the first aspect is assigned to another processor. In the meantime, the master-slave relationship of the synchronization operation is set to achieve the synchronization.

Further, in claim 3, the interrupt signal output means 9 causes the synchronization signals to be generated by the other processors to be the first, second and third timing means (5, 6, 7).
If no input is made via the common bus during any of the time counting operations of the above, at the time when the time counting operation of the third time counting means 7 ends, one of the third and fourth time counting means (7, 8) When input is made via the common bus during the timekeeping operation, at the input time, and when input is made via the common bus during the timekeeping operation of the first timekeeping means 5, the fourth timekeeping means 8 is provided. If an input is made via the common bus during the time counting operation of the second time counting means 6 at the time when the time counting operation of the second time counting means 6 ends, an interrupt signal is generated at the time when the time counting operation of the second time counting means 6 ends. And output to the processor, and the synchronization signals to be generated by the other processors are the first, second and third synchronization signals.
When no input is made through the common bus during any of the time counting operations of the time measuring means 5, 6, and 7, the synchronizing signal is output from the interrupt signal output means 9 at the time when the time measuring operation of the third time measuring means 7 ends. The interrupt signal output by the means 10 will be output on the common bus as a synchronization signal for the other processors. As a result, the fixed-cycle interrupt signal to be synchronized generated by the specific processor is synchronized in the direction of advancing or delaying the phase by the interrupt signal output from the interrupt signal output means, and when another processor is abnormal. An interrupt signal for the processor is autonomously generated, and at the same time, the synchronization signal is supplied to the common bus on behalf of the other processors.

Further, in claim 4, the synchronization circuit according to claim 3 is assigned to the processor, and a series of circuits except the synchronization signal output means 10 according to claim 3 is assigned to another processor. By setting the master-slave relationship of the synchronizing operation in the meantime, the period of the fixed-cycle interrupt signal generated by the specific processor is fixed while the entire control system is synchronized.

[0019]

Embodiments of the present invention will now be described in detail with reference to the drawings. First, a control system having a multiprocessor configuration in which a control device to which the present invention is applied is composed of a plurality of processors will be described.

FIG. 2 is a block diagram of a control system having a multiprocessor configuration in which the control device is composed of two processors. As shown in the figure, this control system includes a processor (CPU-b) 11 and a processor (CPU-a) other than this processor (CPU-b) 11.
12 and further, these processors (C
PU-b) 11 and processor (CPU-b) 12
And a synchronization circuit 1 for a multiprocessor system according to the present invention
3 and a common bus 1 wired or
4 are mutually connected.

The synchronizing circuit 13 of the multiprocessor system used here is another processor (CPU-a).
The active pulse of the synchronization signal SYNC generated by 12 (here, it is low level, the same applies hereinafter) is the common bus 1
4 is input, the interrupt signal INT which is synchronized with the input timing of the synchronization signal SYNC is generated and supplied to the processor (CPU-b) 11, and the synchronization signal SYNC is also supplied. Other processor (CPU
-A) If it is not input due to an abnormality in 12 or the like, the interrupt signal INT is autonomously generated at a predetermined timing and supplied to the processor (CPU-b) 11.

The synchronization signal SYNC generated by the other processor (CPU-a) 12 is the processor (CPU-CPU).
-A) It is output to the common bus 14 in synchronization with the interrupt signal generated inside 12.

Next, a first embodiment embodying the synchronizing circuit 13 of the multiprocessor system shown in FIG. 2 will be described. FIG. 3 is a circuit diagram showing a specific configuration of the synchronization circuit 13 of the multiprocessor system according to the first embodiment. FIG. 4 is a diagram for explaining synchronization by the synchronization circuit 13 of the multiprocessor system according to the first embodiment.

First, as shown in FIG. 3, the synchronization circuit 13 of the multiprocessor system includes a first timer 21.
(First time counting means 1), second timer 22 (second time counting means 2), flip-flop 23, OR gate 24
(Interrupt signal output means 7), logical product gate 25 (synchronization signal output means 8), and various gates 31 to 34 such as NOT and logical product which operate in association with them.

That is, as shown in FIGS. 3 and 4,
The first timer 21 starts a timing operation at the same time when the fixed cycle interrupt signal to be synchronized is supplied to the processor (CPU-b) 11, and thereby the phase advance compensation component from the cycle Ts of the fixed cycle interrupt signal. The time period Ts-Ta obtained by subtracting the time period Ta of the maximum value of
At the same time as the timing of s-Ta ends, the timing end pulse Ps is output. The first timer 21 restarts the time measurement immediately after the time measurement ends. In addition, the second timer 22 starts the timing operation at the same time when the timing operation of the first timer 21 ends and the timing end pulse Ps is input, so that the time Ta of the maximum value of the phase advance compensation is Ta. Is used to measure the time, and during the time-measuring operation of the target time Ta, the time-measuring signal C
a is output, and at the same time as the timing ends, the timing end pulse Pa
Is output.

On the other hand, the flip-flop 23 is an RS flip-flop, and the active pulse of the synchronization signal SYNC generated by the other processor (CPU-a) 12 during the time counting operation of the first timer 21 is the common bus 14. It is memorized that it was input via. The active pulse is set by a pulse that is inverted by the gate (negative) 31, and the output set in this state, that is, the latch output F
Is output.

Further, the OR gate 24 outputs the time counting end pulse Pa of the second timer 22, the time counting end pulse Ps of the first timer 21, and the latch output F of the flip-flop 23.
And a synchronization signal SYNC generated by another processor (CPU-a) 12 which is input via the common bus 14 and the clock operation signal Ca of the second timer 22. The logical sum of the logical product by the gate (logical product) 33 and the negative by the gate 31 is output as the interrupt signal INT to the processor (CPU-b) 11, and the first timer is generated by the interrupt signal INT. 21 reset start, second timer 2
2 and the flip-flop 23 are reset.

The logical product gate 25 detects by the gate (logical product) 34 that the latch output F of the flip-flop 23 and the clocking signal Ca of the second timer 22 are both inactive (not active). If
The interrupt signal INT output from the OR gate 24 is used as a synchronization signal S for the other processor (CPU-a) 12.
Output to the common bus 14 as YNC.

Next, the operation of the synchronizing circuit 13 of the multiprocessor system according to the first embodiment configured as described above will be described. First, even when the synchronization signal SYNC is not input from the common bus 14 during the time counting operation of the first timer 21 which measures the time period Ts-Ta, and also during the time counting operation of the second timer 22 which measures the time period Ta. Synchronization signal SYN
When C is not input, at least during the period Ts of the fixed-cycle interrupt signal generated by the processor (CPU-b) 11, the synchronization signal SYNC to be generated by another processor (CPU-a) 12 is changed. Since it is not input due to an abnormality, the synchronization circuit 13 of this multiprocessor system autonomously generates the interrupt signal INT at the moment when the period Ts of the fixed-cycle interrupt signal has expired, and the interrupt signal INT is sent to the processor (CPU- b) 11 and supplies the synchronization signal SYNC to the common bus 14
It is also supplied to the other processor (CPU-a) 12 via. That is, if the synchronization signal SYNC is not input during the time counting operation of the first timer 21 and the time counting operation of the second timer 22, the second fixed timer interrupt signal is output at the moment when the cycle Ts of the previous fixed cycle interrupt signal has expired. Since the timer 22 outputs the timing end pulse Pa, this timing end pulse Pa is operated by the logical sum gate 24 so that the specific processor (CPU-
b) The signal is output as the interrupt signal INT to 11 and the latch output F of the flip-flop 23 and the clocking signal Ca of the second timer 22 at this time are both inevitable. , OR gate 2 above
The interrupt signal INT output from the processor 4 is supplied to another processor (CPU-
a) Common bus 1 as synchronization signal SYNC for 12
4 is output.

On the other hand, after the first timer 21 for measuring the time period Ts-Ta is finished, the synchronization signal SYN is outputted from the common bus 14 during the time measurement operation of the second timer 22 for measuring the time period Ta.
When C is input, the synchronization circuit 13 of the multiprocessor system immediately generates only the interrupt signal INT synchronized with the input timing of the synchronization signal SYNC and outputs it to the processor (CPU-b) 11 Supply to. That is, if the synchronization signal SYNC is input during the time counting operation of the second timer 22, the gate 3 is activated while the second timer 22 outputs the time counting operation signal Ca.
Since the logical product of 3 is obtained, the logical product of the logical product of 3 is obtained by the operation of the logical sum gate 24.
Will be immediately output as an interrupt signal INT to the. At this time, since the flip-flop 23 outputs the latch output F, the gate 34 and the AND gate 25 prevent the synchronization signal SYNC from being output to the common bus 14. As a result, when the phase difference between the fixed-cycle interrupt signal generated by the processor (CPU-b) 11 and the synchronization signal SYNC generated by another processor (CPU-a) 12 is in the range of -Ta to 0, , The synchronization signal SY input via the common bus 14
The operation becomes passive with respect to the NC, and at this time, the interrupt signal INT output from the OR gate 24 causes the fixed-cycle interrupt signal to be synchronized, which is supplied to the processor (CPU-b) 11, to change its phase. -It is synchronized immediately in the direction to advance in the range of Ta to 0.

Finally, when the synchronization signal SYNC is input from the common bus 14 during the timing operation of the first timer 21 for timing the time period Ts-Ta, the synchronization circuit 13 of this multiprocessor system is At the moment when the time period Ts-Ta has expired, only the interrupt signal INT is generated and supplied to the specific processor (CPU-b) 11. That is, the synchronization signal S is generated during the time counting operation of the first timer 21.
When YNC is input, the latch output F is immediately output from the flip-flop 23, and then the previous time period Ts-T
When a has expired, the first timer 21 outputs the timing end pulse Ps.
Since the logical product of the gate 32 is obtained at the moment when is output, the logical product of this logical product is the interrupt signal INT to the processor (CPU-b) 11 by the operation of the logical sum gate 24.
Further, the latch output F of the flip-flop 23 causes the synchronizing signal SY to be output to the common bus 14 by the action of the gate 34 and the AND gate 25.
NC will not be output. As a result, the fixed-cycle interrupt signal supplied to the processor (CPU-b) 11 and the synchronization signal S generated by another processor (CPU-a) 12 are generated.
Even if the phase difference with YNC exceeds Ta, common bus 1
4 becomes to operate passively with respect to the synchronization signal SYNC input via the processor 4, and the interrupt signal INT output from the OR gate 24 causes the processor (C
The fixed-cycle interrupt signal to be synchronized, which is generated by PU-b) 11, is synchronized in such a direction as to advance its phase by the maximum time Ta.

FIG. 5 is a timing chart when the processor (CPU-b) 11 of the first embodiment described above synchronously pulls in the synchronization signal of the cycle Tsa of the processor (CPU-a) 12. The processor (CPU-a) 12 has an interrupt signal (CPU-a Interrupt) Sa _{11 to} S of a cycle Tsa.
Works with a ₁₆ . Further, the interrupt signal Sa ₁₁ -SA _{1 6}
Is a signal in the processor (CPU-a) 12, and the interrupt signal Sa ₁₁ from the processor (CPU-a) 12
To Sa ₁₆ are synchronization signals (SYNC; B _{11 to} B) of the bus 14.
₁₆ ) is output. Note that here, the processor (CP
U-a) 12 is a master CPU. This synchronization signal S
a ₁₁ to -SA ₁₆ processor (CPU-b) 11 operates to synchronize as follows.

The interrupt signal Sa ₁₁ is output as a bus interrupt signal, that is, a synchronization signal B ₁₁ to the common bus 14. Here, it is assumed that the interrupt signal Sb ₁₁ is applied to the processor (CPU-b) 11 from the synchronization circuit 13 of the multiprocessor system. It should be noted that the synchronization circuit 13 of the multiprocessor system can be connected to the processor
b) Let Tsb be the basic interrupt cycle to 11. Further, the above-mentioned time period Ta is set to Tab. This time period T
When the synchronization signal B ₁₁ corresponding to the interrupt signal Sa ₁₁ of the processor (CPU-a) 12 exists between sb and Tab, the synchronization circuit 13 of the multiprocessor system of the processor (CPU-b) 11 has a time period Tsb. At the end of -Tab, the interrupt signal Sb ₁₁ is output to the processor (CPU-b) 11.

Then, the time period Tsb after the interrupt signal Sb ₁₁ is reached.
Since the synchronization signal B ₁₂ is present during −Tab, the synchronization circuit 13 of the multiprocessor system similarly outputs the interrupt signal Sb _{1 2} to the processor (CPU-b) 11. The same applies to the next clock, and the interrupt signal S
b ₁₃ is output to the processor (CPU-b) 11.

On the other hand, after the interrupt signal Sb _{13 of} the processor (CPU-b) 11 is output, the time period Tsb-T
No synchronization signal is added during period a. Therefore, the synchronization circuit 13 of the multiprocessor system has the time limit Tsb-T.
When the ab ends, the interrupt signal Sb _{1 4} ′ is not output, and when the synchronization signal B ₁₄ is added, the signal is output as the interrupt signal Sb ₁₄ to the processor (CPU-b) 11. When the synchronization signal B ₁₄ is not applied during the time period Tab, the interrupt signal Sb ₁₄ ″ is output at the end of the time period Tab. In FIG. 5, the interrupt signal synchronization Tsa of the processor (CPU-a) 12 is Tsa. Is shorter than the synchronization of the interrupt signal of the processor (CPU-b) 11, the synchronization signal B ₁₄ is generated within the time period Tab.

Thereafter, the synchronizing signals B ₁₅ , S ₁₅ are synchronized with the interrupt signals Sa ₁₅ , Sa ₁₆ to the processor (CPU-a) 12.
B ₁₆ is output, and correspondingly, the synchronizing circuit 13 of the multiprocessor system outputs interrupt signals Sb ₁₅ and Sb ₁₆ .

By the above operation, the processor (C
PU-a) 12 is synchronized with the interrupt signal of the processor (C
The interrupt signal to PU-b) 11 is synchronized. The first
In this embodiment, when the processor becomes the master, the cycle of the interrupt signal of the processor Tsa is the processor (CP
It must be shorter than the period Tsb of the interrupt signal Ub) 11. Next, a second embodiment in which the synchronization circuit 13 of the multiprocessor system shown in FIG. 2 is embodied will be described.

FIG. 6 is a circuit diagram showing a specific structure of the synchronizing circuit 13 of the multiprocessor system according to the second embodiment. FIG. 7 is a diagram for explaining synchronization by the synchronization circuit 13 of the multiprocessor system according to the second embodiment.

First, as shown in FIG. 6, the synchronization circuit 13 of the multiprocessor system includes a first timer 41.
(First time measuring means 5), second timer 42 (second time measuring means 6), third timer 43 (third time measuring means 7), fourth timer 44 (fourth time measuring means 8) , A first flip-flop 45, a second flip-flop 46, an OR gate 47 (interrupt signal output means 9), an AND gate 48
(Synchronization signal output means 10), and various gates 51, such as NOT, logical product, and logical sum, which operate in association with these
It is configured with 59.

The first timer 41 is a processor (CPU
-B) By starting the timing operation at the same time when the fixed period interrupt signal to be synchronized with 11 is supplied, the time period corresponding to the region of the period Ts of the fixed period interrupt signal that should be compensated for by the delay action. Time Ts ₁ . During the timekeeping operation of the target time period Ts _1, the timekeeping operation signal Cs ₁ is output, and simultaneously with the end of the timekeeping, the timekeeping end pulse Ps ₁ is output.
The first timer 41 is a self-propelled timer, and if it is not reset, it automatically restarts after the maximum time is counted.

The second timer 42 starts the timing operation at the same time when the timing operation of the first timer 41 ends and the timing end pulse Ps ₁ is input. Previous is intended for measuring the time period Ts ₂ corresponding to the region to be compensated by proceeds operating a phase difference of the period of the periodic interrupt signal during counting operation In the time counting operation of the time period Ts ₂ of the target signal Cs ₂ is output, and at the same time as the end of the timing, a timing end pulse Ps ₂ is output.

The third timer 43 starts the timing operation at the same time when the timing operation of the second timer 42 is finished and the timing end pulse Ps ₂ is inputted, so that the cycle Ts of the previous fixed cycle interrupt signal is started. From the time period Ts ₁ measured by the first timer 41 and the time period T measured by the second timer 42
The time limit Ta ₁ of the maximum value of the phase advance compensation minus s ₂
Time. At the time of the operation, during the timekeeping operation of the target time period Ta ₁ , the timekeeping operation signal Ca ₁ is output, and simultaneously with the end of the timekeeping, the timekeeping end pulse Pa ₁ is output.

The fourth timer 44 starts the timing operation at the same time when the timing operation of the third timer 43 ends and the timing end pulse Pa ₁ is input, so that the maximum value of the phase delay compensation component Time Ta ₂ is timed. During the timekeeping operation of the target time period Ta _2, the timekeeping operation signal Ca ₂ is output, and simultaneously with the end of the timekeeping, the timekeeping end pulse Pa ₂ is output.

The first flip-flop 45 is used by another processor (CPU-a) during the time counting operation of the first timer 41.
For example, an RS flip-flop that stores that the active pulse of the synchronization signal SYNC generated by 12 is input through the common bus 14, and the active pulse is inverted by the gate (negative) 51 and the second pulse. Gate (logical product) 5 with signal Cs ₁ during timer operation of timer 41 of ₁
The logical product of 2 sets or latches the latched output F ₁ in this state. Further, the second flip-flop 46 receives the active pulse of the synchronization signal SYNC generated by the other processor (CPU-a) 12 during the time counting operation of the second timer 42 via the common bus 14. For example, an RS flip-flop for storing the pulse, the active pulse of which is inverted by the gate 51 and the signal C during clock operation of the second timer 42.
Set or latch by the logical product of the gate (logical product) 53 with s _2, and in this state, the latch output F ₂
Is output.

Further, the logical sum gate 47 is a logical product of the gate (logical product) 54 of the time counting end pulse Pa ₂ of the fourth timer 44 and the latch output F _{1 of} the first flip-flop 45, and the third timer. 43 timing end pulse Pa ₁ and the first
Latch output F ₁ whether the flip-flop 45 with the logical product by the gate (logical product) 55 the latch output F ₂ of the absence of the second flip-flop 46, the count end pulse Ps ₂ of the second timer 42 second the gate of the latch output F ₂ of the second flip-flop 46 (logical product) 56 by logical, and the third time counting operation in the signal Ca ₁ timer 43 counting operation in the signal Ca ₂ of the fourth timer 44 Gate (logical sum) 57
And a synchronization signal SY generated by another processor (CPU-a) 12 input via the common bus 14.
Gate (AND) 58 with negation by gate 51 of NC
The logical sum of the logical product by the processor (CPU-b) 1
While outputting as an interrupt signal INT for 1,
This interrupt signal INT is used to reset / start the first timer 41, reset the second timer 42, and reset the third timer 42.
The timer 43 is reset, the fourth timer 44 is reset, the first flip-flop 45 is reset, and the second flip-flop 46 is reset.

[0046] Then, AND gate 48 includes a latch output F ₁ of the first flip-flop 45 is not both and the latch output F ₂ of the second flip-flop 46 (not active), and other Processor (CPU-a) 1
The gate 51 and the gate (logical product) 5 are that the synchronization signal SYNC generated by 2 is not input through the common bus 14.
9 and the interrupt signal INT output from the OR gate 47 is detected by another processor (CPU).
-A) The synchronization signal SYNC for 12 is output to the common bus 14.

Next, the operation of the synchronizing circuit 13 of the multiprocessor system according to the second embodiment configured as described above will be described. First, time Ts ₁ and time Ts ₂
The synchronization signal SYNC is not input from the common bus 14 during the time-measuring operation of each of the first timer 41 and the second timer 42 that respectively time the time, and the time of the third timer 43 that times the time period Ta ₁ is measured. Synchronization signal SYN during operation
When C is not input, at least during the period Ts of the fixed-cycle interrupt signal generated by the processor (CPU-b) 11, the synchronization signal SYNC to be generated by another processor (CPU-a) 12 is changed. Since it is not input due to an abnormality, the synchronization circuit 13 of this multiprocessor system autonomously generates the interrupt signal INT at the moment when the period Ts of the fixed-cycle interrupt signal has expired, and the interrupt signal INT is sent to the processor (CPU- b) 11 and supplies the synchronization signal SYNC to the common bus 14
It is also supplied to the other processor (CPU-a) 12 via. That is, the first timer 41 outputs the signal Cs ₁
If the synchronization signal SYNC is not input during the output of the signal, the action of the gate 52 causes the first flip-flop 4 to operate.
If the latch output F ₁ of No. 5 becomes negative and the synchronization signal SYNC is not input while the second timer 42 is outputting the in-time counting signal Cs ₂ , the action of the gate 53 causes the _second output. The latch output F ₂ of the flip-flop 46 also becomes unacceptable, and the logical product of the gate 55 is output at the moment when the period Ts of the previous fixed period interrupt signal has expired and the time counting end pulse Pa ₁ has been output from the third timer 43. Therefore, this logical product is output as the interrupt signal INT to the specific processor (CPU-b) 11 by the operation of the logical sum gate 47. Further, at this time, the latch output F ₁ of the first flip-flop 45 and the second flip-flop 4
Since both the latch output F ₂ and the latch output F _{2 of} 6 are NO as described above, the interrupt signal INT output from the OR gate 47 is operated by the gate 59 and the AND gate 48 so that another processor (CPU- a) It is output to the common bus 14 as a synchronization signal SYNC for 12.

On the other hand, after the respective timers of the first timer 41 and the second timer 42 for measuring the time period Ts ₁ and the time period Ts ₂ respectively have finished, the third timer 43 for measuring the time period Ta ₁ and the time period Ta ₂ respectively. When the synchronization signal SYNC is input from the common bus 14 to any one of the clocking operations of the fourth timer 44 and the fourth timer 44, the synchronization circuit 13 of the multiprocessor system detects the synchronization signal S.
Interrupt signal INT synchronized with YNC input timing
Only generate immediately and make this a processor (CPU-b)
Supply to 11. That is, if the synchronization signal SYNC is input during the time counting operation of the third timer 43 or the fourth timer 44, the time counting operation signal is output from the third timer 43 or the fourth timer 44 via the gate 57. The gate 58 is activated while Ca ₁ or the signal Ca ₂ during clock operation is being output.
Therefore, the logical product is immediately output as the interrupt signal INT to the processor (CPU-b) 11 by the operation of the logical sum gate 47. Further, since the output of the gate 51 is not negative at this time, the common bus 14 is operated by the operation of the gate 59 and the AND gate 48.
The synchronization signal SYNC will not be output to. As a result, the phase difference between the fixed-cycle interrupt signal generated by the processor (CPU-b) 11 and the synchronization signal SYNC generated by another processor (CPU-a) 12 is -Ta ₁ to + Ta ₂
In the range of, the processor operates passively with respect to the synchronization signal SYNC input via the common bus 14, and at this time, the interrupt signal INT output from the OR gate 47 causes the processor ( The fixed-cycle interrupt signal to be synchronized, which is supplied to the CPU-b) 11, changes its phase.
Is immediately synchronized -ta ₁ ~ + Ta direction or retard direction to advance in the _second range.

The first timer 4 for measuring the time period Ts ₁
The synchronization signal SYNC from the common bus 14 during the timing operation of 1
, The synchronization circuit 13 of the multiprocessor system generates only the interrupt signal INT at the moment when the time Ta ₂ measured by the fourth timer 44 expires and outputs it to the processor (CPU). -B) Supply to 11. That is, the first timer 41 is a signal C during clock operation.
If the synchronization signal SYNC is input while s ₁ is being output, the latch output F ₁ is immediately output from the first flip-flop 45 by the action of the gate 52, and then the previous time period Ta ₂ is output. Since the logical product of the gate 54 is obtained at the moment when the time expires and the fourth timer 44 outputs the timing end pulse Pa ₂ , the logical product is obtained by the operation of the logical sum gate 47. 11 is output as the interrupt signal INT, and the latch output F ₁ of the first flip-flop 45 causes the synchronization signal SYNC to be output to the common bus 14 by the action of the gate 59 and the AND gate 48. No output. As a result, even when the lead phase difference between the fixed cycle interrupt signal supplied to the processor (CPU-b) 11 and the synchronization signal SYNC generated by another processor (CPU-a) 12 exceeds Ta ₂ ,
It operates passively with respect to the synchronization signal SYNC input via the common bus 14, and the interrupt signal INT output from the OR gate 47 at this time causes the processor (CP
The U-b) 11 generated fixed-cycle interrupt signal to be synchronized is synchronized in the direction in which its phase is delayed by a maximum time Ta ₂ .

Finally, when the synchronization signal SYNC is input from the common bus 14 during the timing operation of the second timer 42 for timing the time period Ts ₂ , the synchronization circuit 13 of this multiprocessor system is At the moment when the time limit Ts ₂ expires, only the interrupt signal INT is generated and supplied to the processor (CPU-b) 11. That is, if the synchronization signal SYNC is input while the second timer 42 is outputting the signal Cs ₂ during clock operation, the latch output F is immediately output from the second flip-flop 46 by the action of the gate 53.
₂ is output, and after this, the _second time period Ts ₂ expires and the second
Since the logical product of the gate 56 is obtained at the moment when the timer 42 outputs the timing end pulse Ps ₂ , this logical product is operated by the logical sum gate 47.
-B) Output as an interrupt signal INT for 11. Further, due to the latch output F ₂ of the second flip-flop 46, the synchronizing signal SYNC is not output to the common bus 14 by the action of the gate 59 and the AND gate 48. As a result, the fixed-cycle interrupt signal supplied to the processor (CPU-b) 11 and another processor (CPU-a)
12 has a delay phase difference of T from the synchronization signal SYNC.
Even when a ₁ is exceeded, it operates passively with respect to the synchronization signal SYNC input through the common bus 14, and the interrupt signal INT output from the OR gate 47 at this time causes the processor ( The fixed-cycle interrupt signal to be synchronized, which is supplied to the CPU-b) 11, is synchronized in such a direction as to advance its phase by the maximum time Ta ₁ .

FIG. 8 is a timing chart of synchronization pull-in to the master CPU. In the second embodiment of the present invention, the time periods Ts ₁ and Ts ₂ are timed. Processor (CP
U-b) 11 corresponding to the above-mentioned time periods Ts ₁ , Ts ₂ of the synchronization circuit 13 of the multiprocessor system Ts ₁ b, Ts ₂
Let b. Similarly, the times Ta ₁ and Ta ₂ are changed to the times Ta ₁ b,
Let Ta ₂ b. It should be noted that the cycle Tsb = Ts ₁ b + Ts ₂ b + Ta ₁
b.

Further, the multiprocessor system synchronization circuit 13 does not perform the synchronization pull-in to the synchronization signal, and the processor (CPU-b) 11 receives the interrupt signal S.
It is assumed that b ₂₁ is output from the multiprocessor system synchronization circuit 13. Then, the processor (CPU-a) 1
It is assumed that interrupt signals Sa _{21 to} Sa ₂₅ are generated within 2.

Synchronization circuit 1 of multiprocessor system
It is assumed that the synchronization signal B ₂₁ is output to the bus 14 within the time period Ts ₁ b after the output of the synchronization signal Sb ₂₁ by the signal S3. At this time, it operates to delay the interrupt signals to the processor (CPU-b) 11, a timed Tsb + Ta ₂ b namely timed _{Ts 1 b + Ts 2 b +} Ta 1 b + Ta 2 b interruption signal Sb ₂₂ at the end of the processor (CPU - b) Output to 11. Similarly, after the synchronization signal Sb ₂₂ is output, the time period Ts ₁ b
Since the synchronization signal B ₂₂ is output during the period, the time period Tsb = T
At the end of s ₁ b + Ts ₂ b + Ta ₁ b, the timing operation of the time period Ta ₂ b is started in order to delay without generating an interrupt signal.

On the other hand, the following synchronizing signal B ₂₃ is sent from the bus 14 during the time period Ta ₁ b and time period Ta ₂ b (time period Ta ₂ in FIG. 8).
(b)), the synchronizing circuit 13 of the multiprocessor system outputs the interrupt signal Sb ₂₃ to the processor (CPU-b) 11 in synchronization with the synchronizing signal B ₂₃ . That is, the synchronization signal B ₂₃ is output to the processor (CPU-b) 11 as the interrupt signal Sb ₂₃ .

The synchronization signal B ₂₃ is sent to the processor (CPU-
a) Since it is synchronized with the interrupt signal Sa _{23 of} 12, the processor (CPU-b) 11 and the processor (C
PU-a) 12 is synchronized.

Once the synchronization is applied, the time period Ts starts from the next time.₁b
And time limit Ts₂No interrupt occurs between b and Tsb-T
a₁Since it occurs between b and Tsb, the synchronization signal is always generated.
Issue B _{twenty four}, B_{twenty five}Interrupt signal Sb synchronized with_{twenty four}, Sb_{twenty five}The
Output to the processor (CPU-b) 11.

By the above operation, the synchronization circuit 13 of the multiprocessor system outputs an interrupt signal synchronized with the interrupt signal of the processor (CPU-a) 12 which is the master processor to the processor (CPU-b) 11.

In the above-described first embodiment of the present invention, the cycle Tsb of the processor on the side where the synchronization is pulled in must be larger than the cycle Tsa of the processor to be the master CPU, but the above-described first embodiment of the present invention. In the second embodiment, both are configured to be synchronized.

In the multiprocessor system described above, the interrupt signal to one processor is used as the master and the interrupt signal to the other processor is synchronized with it, but the present invention is not limited to this. For example, the synchronization circuit 13 of the multiprocessor system in FIG. 2 may be provided in each processor so that they can be synchronized with each other.

FIG. 9 is a block diagram of a control system having a multiprocessor configuration in which the control device is composed of two processors. In FIG. 9, the two processors 11 and 15 have synchronization circuits 13 and 16 of a multiprocessor system, respectively, and are configured to synchronize with each other. In this case, the entire system synchronizes with the fast interrupt cycle.

FIG. 10 is a timing chart of synchronous pull-in of the two processors 11, 15 when the cycle Tsa is longer than the cycle Tsb in the first embodiment. In such a case, the idea of a master processor does not apply.

While the interrupt signals Sa _{31 to} Sa _{33 of the} processor (CPU-a) 15 are generated, the processor (CPU-a)
a) Since the phase of 15 is advanced, the synchronizing signals B _{31 to} B ₃₃ are output to the common bus 14 in synchronization with the interrupt signals Sa _{31 to} Sa ₃₄ . At this time, the synchronization circuit 13 of the multiprocessor determines that the interrupt signals Sb _{31 to} Sb ₃₃ of the processor (CPU-b) 11 are behind, and outputs the signal in the direction of advancing the phase, that is, at the end of the cycle Tsb-Tab. To do. Since the external synchronization signal is not input during the time period Tsb-Tab after the interrupt signal Sb ₃₃ , it is monitored whether the synchronization signal is input from the outside during the time period Tab. During this period, since the synchronization signal B ₃₄ is added, the interrupt signal Sb ₃₄ is output to the processor (CPU-b) 11 in synchronization with it. Synchronization can be achieved at this point.

Since the system shown in FIG. 9 is configured so as to synchronize with each other, for example, when the cycle Tsb is shorter than the cycle Tsa, the processor (CPU-a) 15 synchronizes with the cycle Tsb.

In FIG. 10, since the period Tsb is shorter than the period Tsa after the interrupt signal Sb ₃₄ is generated in synchronization with the interrupt signal Sa ₃₄ , the processor (C
The interrupt signal Sb ₃₅ to PU-b) 11 is generated first.
Then, the synchronization circuit 13 of the multiprocessor system outputs the interrupt signal to the system bus.

On the other hand, the synchronizing circuit 16 of the multiprocessor system does not generate any signal after the previously generated interrupt signal Sa ₃₄ , and waits for the time period Tsa. During this period, the interrupt signal Sb ₃₅ is output, so that the interrupt signal Sa ₃₅ is generated corresponding to the synchronization signal B ₃₅ synchronized with it and output to the processor (CPU-a) 15.

After that, since the cycle Tsb is short, the above-mentioned operations are sequentially repeated. That is, a fast processor (CPU-
b) Operates in a system synchronized with 11 cycles. Figure 11
FIG. 8 is a timing chart of synchronization pull-in of two CPUs when the cycle Tsb is shorter than the cycle Tsa in the second embodiment.

For example, when the synchronization circuit 13 of the multiprocessor system measures the time period Ts ₁ b, the processor (CPU
-A) Synchronization signal B in synchronization with interrupt signal Sa _{41 of} 15
Consider the case where ₄₁ is output to the common bus 14.

Synchronization circuit 1 of multiprocessor system
In _No. 3, since the synchronization signal B ₄₁ is generated during the timekeeping operation of the time period Ts ₁ b, the time point Ta ₁ b ends the time measurement, that is, the interrupt signal Sb ₄₁ to the processor (CPU-b) 11 is generated. When the time Tsb elapses from the next time, the next interrupt signal Sb ₄₂
The timing operation of the time period Ta ₂ b is started without generating. Furthermore, timed Ta since the sync signal B ₄₂ of the next is not input from the ₂ b common bus 14 during timing operation, at timing operation end timed Ta ₂ b, i.e. timed Tsb + Ta ₂ from the occurrence of the interrupt signal Sb ₄₁ When b has elapsed, an interrupt signal Sb ₄₂ is generated to the processor (CPU-b) 11.

Subsequently, the synchronization signal B ₄₂ is output to the common bus 14 in synchronization with the interrupt signal Sa ₄₂ to the processor (CPU-a) 15. When the synchronization signal B ₄₂ is output, the synchronization circuit 13 of the multiprocessor system keeps time Ts ₁ b, so that the time Ts ₁ b ends, that is, the processor (CPU-b) 11 receives. When the time period Tsb elapses after the interrupt signal Sb ₄₂ is generated, the next interrupt signal Sb ₄₃ is not generated, and the timing operation of the time period Ta ₂ b is started. Synchronization circuit 13 of multiprocessor system
Interrupt signal Sa ₄₃ is applied to the processor (CPU-a) 15 while the timer Ta ₂ b is being timed, and the synchronization signal B ₄₃ is output to the common bus 14 in synchronization with it, synchronization of the multiprocessor system is performed. circuit 13 an interrupt signal Sb ₄₃ in synchronization with the synchronization signal B ₄₃ processor (CPU-b) 11
Occur to.

Here, the interrupts in the multiprocessor system can be synchronized. On the other hand, the cycle Tsb is the cycle T
If shorter than sa is timed T from the generation of the synchronization signal B ₄₃
An interrupt signal Sb ₄₄ is generated before sa has elapsed, and it is output as a synchronization signal B ₄₄ to the common bus 14 and is further added to the synchronization circuit 16 of the multiprocessor system. The synchronization circuit 16 of the multiprocessor system has a time limit of Ts ₁ a + T
When the synchronization signal B ₄₄ is added during the timing of the time period Ta ₁ a after the timing of s ₂ a is finished, the multiprocessor system synchronization circuit 16 synchronizes with the synchronization signal B ₄₄ and the processor (CPU -A) Output the interrupt signal Sa ₄₄ to 15. Then, this state is sequentially repeated.
That is, the interrupt signal Sa corresponding to the interrupt signal Sb _44
44, also interrupt signal Sa _45, Sa ₄₆ is outputted in response to the interrupt signal Sb _45, Sb _46.

As described above, by providing the multiprocessor system synchronization circuits 13 or 16 with each other, the operations are performed in synchronization with each other in an early cycle, and they are also operated in synchronization.

The first and second embodiments based on the configurations of the first and second inventions have been described above in detail, but in these first and second embodiments, a specific processor (CPU- b) Synchronization and phase of the fixed-cycle interrupt signal generated by 11 and other processor (CPU)
-A) Since the cycle and the phase of the fixed-cycle interrupt signal 15 are continuously corrected by the synchronization signal SYNC after the next cycle, the processor (CPU-b) 11 There is a possibility that a subtle change may continue to occur in the cycle Ts of the fixed cycle interrupt signal of. Therefore, the synchronization circuits 13 of the multiprocessor system of the first and second embodiments described above and a series of circuits excluding their AND gates 25, 48, etc. are combined for corresponding ones. Further, by setting the master-slave relationship of the synchronizing operation between the combinations, the processor on the master side (the side having the SYNC output circuit) of the master-slave relationship while synchronizing the entire control system. Of the fixed-cycle interrupt signal generated by
s becomes fixed.

In the present embodiment, the control system having a multiprocessor structure in which the control device is composed of two processors has been described as an example, but in the present invention, the control device is composed of three or more processors. It is also applicable to a control system having a multiprocessor configuration. Further, the present invention is not limitedly applied to the control system having the multiprocessor configuration as shown in the embodiments, and in addition to this, it is necessary to synchronize other periodic signals. It is applicable to all hardware.

Further, in the first and second embodiments of the present invention, the timer and the flip-flop are reset by the interrupt signal INT. In this case, the output synchronization signal S
YNC is a short pulse. To widen the pulse width of the synchronization signal SYNC, the interrupt signal INT is not reset directly but reset by delaying the interrupt signal INT. This delay allows the system to operate stably.

[0075]

As described above in detail, according to the present invention, in the case where the fixed-cycle interrupt signal generated by a specific processor to be synchronized is the first embodiment, the interrupt signal output means 3 is used. Is synchronized in the direction of advancing the phase by the interrupt signal output from the device, and in the case of the second embodiment, is synchronized in the direction of advancing or delaying the phase by the interrupt signal output from the interrupt signal output means 9. Therefore, the interrupt processing of multiple processors is synchronized with each other without affecting the execution time of software, and even when there is an abnormality in another processor,
An interrupt signal for a specific processor is autonomously generated, and the synchronization signal output means 4 and 10 also supply the synchronization signal to other processors.

Further, the master-slave relationship of the synchronizing operation is set between the first embodiment and the series of circuits excluding the synchronizing signal output means 4 of the first embodiment, and similarly, the second operation is performed. While setting the master-slave relationship of the synchronization operation between the embodiment of FIG. 3 and the series of circuits excluding the synchronization signal output means 10 of the second embodiment, while synchronizing the entire control system,
The cycle of the fixed-cycle interrupt signal generated by a specific processor is fixed.

[Brief description of drawings]

1A and 1B are block diagrams of the principle of the present invention.

FIG. 2 is a block diagram of a control system having a multiprocessor configuration in which a control device is composed of two processors.

FIG. 3 is a circuit diagram showing a specific configuration of a synchronization circuit of the multiprocessor system according to the first embodiment.

FIG. 4 is a diagram for explaining synchronization by the synchronization circuit of the multiprocessor system according to the first embodiment.

FIG. 5 is a timing chart of synchronization pull-in to a master CPU.

FIG. 6 is a circuit diagram showing a specific configuration of a synchronization circuit of the multiprocessor system according to the second embodiment.

FIG. 7 is a diagram for explaining synchronization by the synchronization circuit of the multiprocessor system according to the second embodiment.

FIG. 8 is a timing chart of synchronization pull-in to a master CPU.

FIG. 9 is a block diagram of a control system having a multiprocessor configuration in which a control device is composed of two processors.

FIG. 10 is a timing chart of synchronization pull-in of the two processors 11 and 15 when the cycle Tsa is longer than the cycle Tsb in the first embodiment.

FIG. 11 is a timing chart of synchronization pull-in of two CPUs when the period Tsa is shorter than the period Tsb in the second embodiment.

FIG. 12 is a diagram for explaining a situation in which a dead time is generated in a control system having a multiprocessor configuration in which a control device includes two processors.

[Explanation of symbols]

 1 1st timing means 2 2nd timing means 3 Interrupt signal output means 4 Synchronization signal output means 5 1st timing means 6 2nd timing means 7 3rd timing means 8 4th timing means 9 Interrupt signal Output means 10 Synchronization signal output means 11 Processor (CPU-b) 12 Processor (CPU-a) 13 Synchronization circuit of multiprocessor system 14 Common bus 21 First timer 22 Second timer 23 Flip-flop 24 OR gate 25 AND gate 41 First timer 42 Second timer 43 Third timer 44 Fourth timer 45 First flip-flop 46 Second flip-flop 47 Logical OR gate 48 Logical AND gate

Claims (4)

[Claims] 1. A multiprocessor system in which a plurality of processors operate in synchronization with a synchronization signal,
At the same time as the fixed-cycle interrupt signal to be synchronized generated by another processor is input via the common bus, the clocking operation starts, and the time limit of the maximum value of phase advance compensation is subtracted from the cycle of the fixed-cycle interrupt signal. And a first timing means (1) for timing a time period, and the timing operation of the first timing means (1) is started at the same time when the timing operation of the first timing means (1) is finished, and the timing of the maximum value of the phase advance compensation is measured. The second timing means (2) for synchronizing and the synchronization signal to be generated by the other processor are supplied via the common bus during the timing operation of any of the first and second timing means (1, 2). If no time is input by the second time measuring means, at the time when the time measuring operation (2) of the second time measuring means ends,
When the time is input through the common bus during the time counting operation of the time counting means (2), at the time of the input, through the common bus during the time counting operation of the first time measuring means (1). When input, an interrupt signal output means (3) for generating an interrupt signal and outputting it to the processor at the time when the time counting operation of the first time counting means (1) is finished; The synchronization signal to be transmitted is the first
And when no input is made via the common bus during any of the timing operations of the second timing means (1, 2), the interrupt signal output means (3) measures the time of the second timing means (2). A multi-processor comprising: a synchronization signal output means (4) for outputting an interrupt signal output at the time when the operation is finished to the common bus as a synchronization signal for the other processor. System synchronization circuit. 2. A circuit comprising the first clocking means (1), the second clocking means (2) and an interrupt signal output means (3) is added to the other processor to synchronize a plurality of processors. 2. The synchronization circuit for a multiprocessor system according to claim 1, wherein a master-slave relationship of the digitizing operation is set. 3. A multiprocessor system in which a plurality of processors operate in synchronization with a synchronization signal,
When the fixed-cycle interrupt signal to be synchronized that is generated by another processor is input via the common bus, the timing operation starts at the same time, and the phase difference in the cycle of the fixed-cycle interrupt signal is set in the area to be compensated by the delayed operation. The first timing means (5) for timing the corresponding time period and the timing operation of the first timing means (5) are finished at the same time when the timing operation is started, and the phase difference among the cycles of the fixed cycle interrupt signal is calculated. Second timing means (6) for timing a time period corresponding to the region to be compensated for in the advance operation, and the timing operation of the second timing means (6) is started at the same time when the timing operation is started, and the fixed period interrupt is performed. The time period of the maximum value of the phase advance compensation amount obtained by subtracting the time period measured by the first time measuring means (5) and the time period measured by the second time measuring means (6) from the signal period is measured. Third timing means ( ), And the fourth timing means (8) which starts the timing operation at the same time when the timing operation of the third timing means (7) ends and measures the time limit of the maximum value of the phase delay compensation component, The synchronization signal to be generated by the processor is the first,
The time at which the time counting operation of the third time counting means (7) ends if no input is made via the common bus during any time counting operation of the second and third time counting means (5, 6, 7) In the case where an input is made via the common bus during the time keeping operation of any one of the third and fourth time keeping means (7, 8), the first time keeping means ( When an input is made via the common bus during the timekeeping operation of 5), the second timekeeping means (6) is in the timekeeping operation at the time when the timekeeping operation of the fourth timekeeping means (8) is completed. And an interrupt signal output means (9) for generating an interrupt signal and outputting the interrupt signal to the processor at the time when the time counting operation of the second time counting means (6) is completed when the signal is input to the processor via the common bus. , The synchronization signal to be generated by the other processor is the first, second and third synchronization signals. If no input is made via the common bus during any time counting operation of the time counting means (5, 6, 7), the time counting operation of the third time counting means (7) from the interrupt signal output means (9) Synchronization signal output means (10) for outputting, to the common bus, an interrupt signal output at the time when the process ends as a synchronization signal for the other processor.
And a synchronization circuit for a multiprocessor system, comprising: 4. The first timing means (5), the second timing means (6), the third timing means (7), the fourth timing means (8), and the interrupt signal output means (9). A circuit consisting of
3. The synchronization circuit for a multiprocessor system according to claim 2, wherein the synchronization circuit is added to the other processor to establish a master-slave relationship for synchronization operation among a plurality of processors.