JPH07142702A - Bipolar transistor generation method - Google Patents

Abstract

(57) [Abstract] [Object] The present invention compensates for transistor characteristic variations that occur when forming an emitter contact by dry etching in a bipolar transistor generation method. A base impurity is ion-implanted again into an intrinsic base region immediately below an emitter contact that was eroded during the formation of an emitter contact by dry etching to compensate the characteristics of the region. As a result, it is possible to substantially recover the decrease in the base width and the fluctuation in the base impurity profile that occur during etching. This makes it possible to more easily form a small-sized bipolar transistor.

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. Field of Industrial Application Conventional Technology Problem to be Solved by the Invention (FIG. 5) Means for Solving the Problem Action Example (FIGS. 1 to 4) (1) First Example (FIGS. 1 and 2) ) (2) Second embodiment (FIGS. 3 and 4) (3) Other embodiments Effect of the invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar transistor producing method, and is particularly suitable for application to an emitter contact producing method.

[0003]

2. Description of the Related Art Today, the demand for higher integration of semiconductor integrated circuits is increasing, and accordingly, the demand for miniaturization of bipolar transistors used in various circuit parts is also increasing. One of the technologies for miniaturizing the bipolar transistor is miniaturization of the emitter contact. Dry etching is suitable for finely processing the processing size of the emitter contact.

[0004]

However, in general, dry etching is more effective than wet etching in the interlayer insulating film 4.
The etching selection ratio between the base region 2 and the base region 2 is small, and the influence of overetching during etching of the interlayer insulating film 4 cannot be ignored (FIG. 5). That is, if the overetching reaches a deep portion, the base region may disappear due to implantation of an emitter impurity in a subsequent process. In addition, the base width and the profile of the base impurities may change due to overetching, which causes a problem that the operating characteristics of the transistor change.

For this reason, wet etching is mainly used today. However, since wet etching is isotropic etching, there is a problem that the size of the emitter contact cannot be made very small. Further, if the size of the emitter contact is large, the capacitance between the emitter and the base becomes large, and the operating speed of the transistor decreases.

The present invention has been made in consideration of the above points, and it is an object of the present invention to propose a production method capable of obtaining a bipolar transistor having a small characteristic variation even when finely processing an emitter contact by dry etching. To do.

[0007]

In order to solve such a problem, in the present invention, after forming an emitter contact by dry etching, a base impurity (boron) is ion-implanted and the intrinsic base region 12 immediately below the emitter contact. The step (1-5) of compensating for the characteristic of 1) is included in the step of forming the bipolar transistor.

Further, in the present invention, after the formation of the emitter contact by dry etching, the first step (2) for compensating the characteristics of the intrinsic base region 22 immediately below the emitter contact by ion-implanting the base impurity (boron). −
4) and, after the first step, a second step (2-6) of forming an emitter region 26 by implanting an emitter dopant (arsenic) into the intrinsic base region 22 immediately below the emitter contact,
After the second step, the emitter electrode 25A is placed on the emitter area.
The third step (2-7) of forming a film and the emitter electrode 25.
A fourth step of implanting a base impurity (boron) into the intrinsic base region 22 located outside the emitter region 26 using the resist pattern 27 used in forming A as a mask to form the external base 22A in the intrinsic base region ( 2-
8) and are included in the bipolar transistor production process.

[0009]

The base impurity (boron) is ion-implanted again into the intrinsic base region 12 immediately below the emitter contact eroded during the formation of the emitter contact by dry etching to compensate the characteristics of the region.
It is possible to almost eliminate the decrease of the base width and the variation of the base impurity profile due to the dry etching. As a result, the size of the bipolar transistor can be further reduced, and the degree of integration of the semiconductor integrated circuit can be increased.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

(1) First Embodiment In the manufacturing process of this embodiment, the narrow base width in dry etching of an emitter contact is recovered by re-implantation of base impurity ions, and then an emitter region is formed. This is the main process. NPN in the following order
The manufacturing process of the bipolar transistor will be described.

First, a surface region of the silicon substrate 10 excluding a portion forming a base region is selectively wet-oxidized to form an element isolation oxide film (LOCOS: local oxidation of).
silicon) 11 is formed. Next, the silicon nitride film used as a mask when forming the element isolation oxide film 11 is selectively etched with hot phosphoric acid to expose the element formation region. Subsequently, boron ions, which are P-type impurities, are ion-implanted into the element formation region in the order of 10 ¹³ ions / cm ² to form the intrinsic base region 12 (FIG. 1 (1-1)).

A resist is applied to the surface of the intrinsic base region 12 to cover one surface thereof, and then a partial region is patterned to form a resist pattern 13 for forming an external base. Then, 10 ¹⁵ boron ions / cm are added to this opening.
External base 12A by ion implantation in ² orders
Are formed (FIG. 1 (1-2)). This external base 12A
Will be the contact region of the base extraction electrode when completed.

After forming the external base 12A, the resist pattern 13 is removed from the surface of the substrate, and then an interlayer insulating film 14 having a film thickness of 100 nm is formed on the surface by chemical vapor deposition (CVD). To grow. Next, the surface of the interlayer insulating film 14 is covered with a resist, and a partial region thereof is patterned to form an emitter contact window forming pattern 15 (FIG. 1 (1-
3)).

After this step, the interlayer insulating film 14 is removed by dry etching to expose the intrinsic base region 12. Normally, the etching amount at the time of dry etching is set so that an extra etching is applied by about 30% as compared with the film thickness of the interlayer insulating film 14. Therefore, the intrinsic base region 12 formed in the previous step is removed. The film thickness becomes thin (FIG. 1 (1-4)).

Therefore, this time, the thinned intrinsic base region 1
Base impurity ions are additionally implanted to recover the film thickness of 2. In this embodiment, boron ions are implanted at the order of 10 ¹² to 10 ¹³ ions / cm ² . By this ion implantation, the base region 12B of the emitter contact portion spreads downward and is restored to a film thickness substantially the same as the film thickness of the intrinsic base region 12 in the peripheral portion. At the same time, the base impurity profile is also restored to the state before etching (Fig. 1).
(1-5)).

After this, a polysilicon film 16 is grown on the surface of the substrate to form an emitter electrode by chemical vapor deposition. Subsequently, arsenic ions, which are N-type impurities, are ion-implanted into the entire surface of the polysilicon film 16 and arsenic ions are introduced into the intrinsic base region 12B located immediately below the emitter contact portion, which is thinner than other regions. Is injected (FIG. 2 (1-6)).

After that, the arsenic ions implanted in the intrinsic base region 12B are thermally diffused to emit the emitter region 1.
Form 7. Next, the step of forming an emitter electrode is performed. First, a resist is applied on the surface of the polysilicon film 16 and patterned to form a resist pattern 18 (FIG. 2).
(1-7)). Subsequently, the polysilicon film 16 is patterned using the resist pattern 18 to form an emitter polysilicon electrode 16A (FIG. 2 (1-8)).

After the formation of the emitter electrode is completed,
If the surface of the emitter polysilicon electrode 16A is covered with a thick interlayer insulating film, a contact window is formed in the interlayer insulating film located above the external base region 12A, and aluminum is deposited in the opening to form the base electrode. good. As a result, it is possible to realize an NPN bipolar transistor whose characteristics are stable even though the transistor size is small.

According to the above structure, after the emitter contact window is formed by dry etching, boron ions are additionally implanted into the emitter contact, whereby the base width of the intrinsic base region 12 narrowed by etching. And it is possible to compensate the fluctuation of the impurity profile. As a result, it is possible to meet the demand for fine processing of the NPN bipolar transistor, and it is possible to promote miniaturization of the semiconductor integrated circuit.

(2) Second Embodiment Here, in addition to fine processing of the emitter contact by dry etching, a manufacturing process of a bipolar transistor having a short distance between the emitter region and the external base and a small element size as a whole will be described. In this manufacturing process, the external base formation process is performed after the emission region formation process,
The main process is to form an external base using the resist pattern used when processing the emitter electrode as a mask. The manufacturing process of the NPN transistor will be described below in order.

First, a surface region of the silicon substrate 20 excluding a portion forming a base region is selectively wet-oxidized to form an element isolation oxide film 21. Next, the silicon nitride film used as a mask when forming the element isolation oxide film 21 is selectively etched with hot phosphoric acid to expose the element formation region. Subsequently, boron ions, which are P-type impurities, are ion-implanted into the element formation region at an order of 10 ¹³ ions / cm ² to form the intrinsic base region 22 (see FIG.
1)).

Next, chemical vapor deposition (CVD)
After forming the interlayer insulating film 23 by means of (or deposition), the resist applied on the upper surface thereof is patterned to form a resist pattern 24 for opening an emitter contact (FIG. 3 (2-2)). Here, the interlayer insulating film 23 is 1
It is an oxide film having a film thickness of 00 [nm] and is formed by flowing a reaction gas for 20 to 30 minutes on a substrate heated to about 850 [° C.].

Then, using the resist pattern 24 formed in the previous step as a mask, the interlayer insulating film 23 located in the opening is removed by dry etching to form an emitter contact. After this step, the intrinsic base region 22 previously formed is exposed. Normally, the etching amount at the time of dry etching is set so that an extra etching is applied by about 30% compared with the film thickness of the interlayer insulating film 23, so that the intrinsic base region 22 formed in the previous step is removed. The film thickness becomes thin (Fig. 3 (2-
3)).

Therefore, this time, the thinned intrinsic base region 2
Base impurity ions are additionally implanted to recover the film thickness of 2. As in the case of the previous embodiment, boron ions were added at 10 ¹²
Ion implantation is performed on the order of -10 ¹³ ions / cm ² . By this ion implantation, the intrinsic base region 22B in the emitter contact portion spreads downward and is restored to a film thickness almost equal to the film thickness of the intrinsic base region 22 in the peripheral portion. At the same time, the profile of the base impurities is also restored to the state before etching (FIG. 3 (2-4)).

After that, a polysilicon film 25 is grown on the surface of the substrate by chemical vapor deposition to form an emitter electrode. Subsequently, arsenic ions, which are N-type impurities, are ion-implanted into the entire surface of the polysilicon film 25, and the arsenic ions are introduced into the intrinsic base region 22B located in the lower layer of the emitter contact portion, which is thinner than other regions. Is injected (FIG. 3 (2-5)).

When the implantation of arsenic ions into the polysilicon film 25 is completed, the arsenic ions implanted by the heat treatment are diffused into the intrinsic base region 22 to form the emitter region 26 (FIG. 4 (2- 6)). Next, in order to pattern the polysilicon film 25 after the introduction of arsenic ions, a resist is applied to the surface of the polysilicon film 25 and patterned (FIG. 4).
(2-7)).

Using the resist pattern 27 as a mask, the polysilicon film 25 is etched to form an emitter polysilicon electrode 25A. The end of the wiring pattern of the emitter polysilicon electrode 25A formed by this step is 0.5 with respect to the emitter area 26 formed in the previous step.
It is located outside by about [μm].

After the etching process, the external base forming process is performed by implanting ions into the underlying intrinsic base region 22 through the exposed interlayer insulating film 23. The number of boron ions introduced into the intrinsic base region 22 through the interlayer insulating film 23 is on the order of 10 ¹⁵ ions / cm ² . At this time, the resist pattern 27 is still attached to the surface of the emitter polysilicon electrode 25A, and this resist pattern 27 is used as a mask when implanting boron ions (FIG. 4 (2-8)). .

Thus, by implanting boron ions using the resist pattern 27 as a mask, the external base 2
The end of 2A on the emitter side can be formed immediately below the edge portion of the emitter electrode. In the conventional case, since it is necessary to align the mask with the element isolation oxide film as a reference, the distance between the external base 22A and the emitter is formed by the alignment margin, and the base spreading resistance increases. This can reduce this risk.

After the ion implantation process is completed, the resist pattern 27 used for forming the external base 22A is removed, and an interlayer insulating film (boron / phosphorus / silicate glass (BPSG)) having a film thickness of 300 [nm] is removed. 28, the step of covering the entire surface of the substrate is started. Subsequently, a contact window for taking out the base electrode is formed in the interlayer insulating films 23 and 28, and aluminum is vapor-deposited in the formed opening to form the external base 22A.
The extraction electrode 29 is formed on the. As a result, a bipolar transistor having a low base spreading resistance can be obtained (FIG. 4 (2-9)).

As described above, since the mask alignment at the time of ion implantation for forming the external base 22A is unnecessary, the alignment process using the element isolation oxide film 21 is reduced from the conventional two times to one time. As a result, the margin required for alignment is also halved compared to the conventional case, and the emitter region 26 and the external base 22A can be formed closer to each other than in the conventional case. Incidentally, in the case of this example, the end portion of the resist pattern 27 is 0.5 [μm] with respect to the emitter region 26.
Since the outer base 22A and the emitter region 26 are located to the outside, the distance between the outer base 22A and the emitter region 26 can be set to about 0.5 [μm].

According to the above steps, the resist pattern 2 used for forming the emitter polysilicon electrode 25A by processing the emitter contact by dry etching.
By implanting ions for forming the external base using 7 as a mask, it is possible to realize a bipolar transistor having a much smaller transistor size than the conventional one. As a result, the integration degree of the semiconductor integrated circuit can be further increased.

(3) Other Embodiments In the above embodiment, the intrinsic base region 1 is formed after the emitter contact is processed by dry etching.
Although the case of implanting boron ions for compensating the base width of 2 and the impurity profile has been described, the present invention is not limited to this, and can be widely applied to the case of implanting other base impurities.

Further, in the above-mentioned embodiment, the manufacturing method of the NPN type bipolar transistor is described, but the present invention is not limited to this, and may be applied to the manufacturing method of the PNP type bipolar transistor.

Further, in the above-described embodiment, boron ions are added in an amount of 10 ¹³ / when forming the intrinsic base regions 12 and 22.
and implanting the cm ² order Te cowpea, Although the time compensation of the base width of the intrinsic base region 12 and 22 has dealt with the case where implanted Te cowpea boron ions 10 ¹² to 10 ¹³ / cm ² order, the present invention is to Not limited to this, the dose amount may be set to another value. In addition, the emitter polysilicon electrode 1
In the case of forming the external bases 12A and 22A after the formation of 6A and 25A, the case of implanting boron ions with a dose amount of 10 ¹⁵ / cm ² has been described, but the present invention is not limited to this, and the dose amount is also the same. Other values may be used.

Further, in the above embodiment, arsenic ions are added at 10 ¹⁵ / cm ² when forming the emitter regions 17 and 26.
Although the case where the implantation is performed by the dose amount is described, the present invention is not limited to this, and the dose amount may be another value.

Further, in the above-mentioned embodiment, the case where boron ions are implanted into the intrinsic base regions 12 and 22 and arsenic ions are implanted into the emitter regions 17 and 26 has been described, but the present invention is not limited to this. Alternatively, other impurity ions may be implanted to form the P-type region and the N-type region.

Furthermore, in the above-mentioned embodiments, the case where the emitter electrode is formed of polysilicon has been described, but the present invention is not limited to this, and it may be formed of another conductive member.

Furthermore, in the above-mentioned embodiment, the case where the distance between the external base and the emitter is formed to be about 0.5 [μm] has been described, but the present invention is not limited to this, and the design value of the wiring width of the emitter electrode is set. By changing it, the two regions can be shortened to about 0.3 [μm].

[0041]

As described above, according to the present invention, after the step of forming the emitter contact by dry etching, the base impurity is ion-implanted again into the opening to compensate for the decrease in the base width of the intrinsic base region. As a result, it is possible to realize a production method that can easily obtain a bipolar transistor having a small emitter electrode and little characteristic fluctuation.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing an example of a manufacturing process by a method for producing a bipolar transistor according to the present invention.

FIG. 2 is a schematic diagram showing a continuation of the manufacturing process.

FIG. 3 is a schematic diagram showing an embodiment of a manufacturing process by the method for producing a bipolar transistor according to the present invention.

FIG. 4 is a schematic diagram showing a continuation of the manufacturing process.

FIG. 5 is a schematic diagram for explaining a manufacturing process of a conventional bipolar transistor.

[Explanation of symbols]

1, 10, 20 ... Substrate, 2, 12, 22 ... Intrinsic base region, 3, 11, 21 ... Element isolation oxide film, 4, 1
4, 23, 28 ... Interlayer insulating films 5, 13, 15, 1
8, 24, 27 ... Resist pattern, 6 ... Emitter contact, 12A, 22A ... External base, 16, 2
5 ... Polysilicon film, 16A, 25A ... Emitter polysilicon electrode, 17, 26 ... Emitter region, 29 ...
… Extraction electrode.

Claims (3)

[Claims] 1. A method for producing a bipolar transistor, comprising the step of, after forming an emitter contact by dry etching, ion-implanting a base impurity to compensate the characteristics of an intrinsic base region immediately below the emitter contact. 2. The ion implantation amount of the base impurity is 10
^The method for producing a bipolar transistor according to claim 1, wherein the order is ¹² to 10 ¹³ pieces / cm ² . 3. A first step of ion-implanting a base impurity after the formation of an emitter contact by dry etching to compensate for the characteristics of an intrinsic base region immediately below the emitter contact, and after the first step, A second step of forming an emitter area by implanting an emitter impurity into the intrinsic base region directly below the emitter contact; and a third step of forming an emitter electrode on the emitter area after the second step. A fourth step of implanting a base impurity into an intrinsic base region located outside the emitter region using the resist pattern used when forming the emitter electrode as a mask to form an external base in the intrinsic base region. A method for producing a bipolar transistor characterized by the above.