JPH07146342A - Address control memory circuit - Google Patents

Abstract

PURPOSE:To enable a function tester to freely generate an arbitrary pattern memory address and to generate a long and large pattern in a pseudo-executing way. CONSTITUTION:An address counter 1 starts counting operations from '0' and sends a pattern memory address 11. A comparator 3 compares a branching address value 12 from a branching address memory 2 with the address 11. When the value 12 coincides with the address 11, a branched address value 14 from a branched address memory 4 is loaded into the counter 1 and a pointer counter 5 counts a pointer address 15 and outputs the next pointer address 15. The counter 1 can easily generate an arbitrary address by starting the counting operations from the branched address value 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a function tester, and more particularly to an address control memory circuit for generating an address of a pattern memory.

[0002]

2. Description of the Related Art A function tester for testing a function of a semiconductor integrated circuit package composed of logic circuits has a pattern memory, and a test pattern composed of logical values is read from the pattern memory. The read test pattern is input to the device under test, and the output pattern of the device under test at that time is compared with the expected pattern that would be obtained if the device under test operates correctly, and the test pattern is tested. The device is tested for proper operation.

Reading of the pattern memory is performed by inputting an address from the address control memory circuit to the pattern memory. FIG. 2 is a block diagram of a conventional address control memory circuit. The address control memory circuit includes an address counter 1, an address generation memory 7, and a controller 6 for writing data in the address generation memory 7.

This address control memory circuit is
A pattern memory address value to be generated in the address generation memory 7 is written by the controller 6, read sequentially by the address counter 1, and an arbitrary pattern memory address synchronized with the clock is transmitted.

[0005]

In the conventional address control memory circuit, since the pattern memory address value to be sent is written to the address generation memory as it is, an enormous memory capacity and a multi-stage counter are required, and data writing by the controller is required. There was a problem that time also increased. However, in reality, it is impossible to prepare a huge memory capacity. Further, the test pattern length in the function tester is limited by the capacity of the mounted pattern memory. Therefore, the conventional function tester cannot test a package that requires a long pattern.

However, in the test pattern used for the function tester, a large number of the same pattern sequences appear, so that
If the same address can be repeatedly generated for the pattern memory, a pseudo long pattern can be generated.

An object of the present invention is to provide an address control memory circuit which enables generation of repeated patterns, which is a feature of function tester test patterns, with a small capacity memory.

[0008]

SUMMARY OF THE INVENTION An address control memory circuit of the present invention comprises an address counter for counting addresses and generating a pattern memory address, and a branch source address in an address generator of a pattern memory used in a function tester. A branch source address memory that stores a value, a comparator that compares the pattern memory address with the branch source address value, a branch destination address memory that stores a branch destination address value, the branch source address memory, and the branch destination address memory And a controller for previously writing data to the branch destination address memory and the branch source address memory.

[0009]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of an address control memory circuit according to the present invention.

This address control memory circuit is
An address counter 1 that counts addresses and generates a pattern memory address, a branch source address memory 2 that stores a branch source address value, a comparator 3 that compares a pattern memory address with a branch source address value, and a branch destination address value A branch destination address memory 4, a pointer counter 5 that counts pointers in the memories 2 and 4, and a controller 6 that writes data in advance to the branch source address memory 2 and the branch destination address memory 4.

Comparator 3 outputs "L" when the comparison is successful.
If the comparison at the (Low) level does not match, "H (H
When the load pulse 13 is “L”, the address counter 1 loads the branch destination address from the branch destination address memory 4. The pointer counter 5 rises the load pulse 13. Count up with.

Next, the general operation of this embodiment will be described.

Data is previously written in the branch source address memory 2 and the branch destination address memory 4 by the controller 6. That is, a branch source address value for repeating the pattern is written in the branch source address memory 2, and a branch destination address value is written in the branch destination address memory 4.

The address counter 1 is set to 0 by the clock.
The count value is sequentially incremented from and the count value is sent as the pattern memory address 11. The comparator 3 compares the sent pattern memory address 11 with the branch source address value 12 output from the branch source address memory 2,
The load pulse 13 is output to the address counter 1 and the pointer counter 5. As described above, the load pulse 13 becomes "L" when the comparisons match and "H" when the comparisons do not match.

The address counter 1 has a load pulse 13
Becomes "L", the branch destination address value 14 is loaded from the branch destination address memory 4, and the value of the loaded branch destination address value 14 is sequentially counted up.

At this time, the comparison in the comparator 3 is not coincident, and the load pulse 13 becomes "H". The initial value of the pointer counter 5 is set to 0, and the pointer is counted up at the rising edge of the load pulse 13,
The next pointer address 15 is output to the branch source address memory 2 and the branch destination address memory 4. The branch source address memory 2 and the branch destination address memory 4 are read by the pointer address 15 output from the pointer counter 5 and output the next address value. That is, the branch destination address memory 4 sends the branch destination address value 14 to the address counter 1, and the branch source address memory 2 sends the branch source address to the comparator 3.

By repeating the above operation, the address control memory circuit can easily send an arbitrary pattern memory address.

A specific example will be described in detail below.

Example 1: When the address counter 1 repeatedly outputs the address values 5 to 8 as pattern memory addresses three times, the controller 6 controls the branch source address memory 2 and the branch destination address memory 4 by the controller 6. The data shown in is written in advance. That is, the value 8 is written in the addresses 0, 1, 2 of the branch source address memory 2 and the value 5 is written in the addresses 0, 1, 2 of the branch destination address memory 4. The initial values of the address counter 1 and the pointer counter 5 are set to 0 in advance.

As shown in FIG. 4, the address counter 1
Sequentially counts up from 0 at the rising edge of the clock and outputs the count value as the pattern memory address 11. On the other hand, the pointer counter 5 sequentially counts from 0 at the rising edge of the load pulse 13.

The comparator 3 compares the value output from the address counter 1 with the value at address 0 of the branch source address memory 2. When the value output from the address counter 1 reaches 8, it is determined that the comparator 3 agrees with the value 8 at address 0 of the branch source address memory 2, and the load pulse 13
Changes from "H" to "L". As a result, the address counter 1 reads and loads the value 5 at address 0 of the branch destination address memory 4. The address counter 1 counts up from the loaded value 5. That is, the address counter 1 branches from the value 8 to the value 5.

In the comparator 3, the address counter 1
The value 5 output from the above is compared with the value 8 at the address 0 of the branch source address memory 2, and the load pulse 13 is returned to "H" because they do not match. By this rise, the pointer counter 5 is incremented to 1, and the pointer addresses to the branch source address memory 2 and the branch destination address memory 4 become 1.

In the address counter 1, when the value 5 loaded from the branch destination address memory 4 is counted up to 6, 7, 8 and the value 8 is output as the pattern memory address 11, the same operation as described above is performed. , The value 5 at address 1 of the branch source address memory 4 is loaded, and the same operation is repeated twice.

As described above, according to this embodiment, the address counter 1 repeatedly outputs the address values 5 to 8 as pattern memory addresses three times.

Example 2: When the address counter 1 outputs the address values 3 to 5 twice as the pattern memory address and subsequently outputs the address values 6 to 8 twice, the same address is repeatedly generated. In advance, the controller 6 writes the data shown in FIG. 5 in the branch source address memory 2 and the branch destination address memory 4 in advance. That is, the value 5 is written to the addresses 0 and 1 of the branch source address memory 2, the value 8 is written to the addresses 2 and 3, and the value 3 is written to the addresses 0 and 1 of the branch destination address memory 4. And the value 6 is written in address 3.

By repeating the same operation as in Example 1,
The address counter 1 uses a pattern memory address as
Address values 3 to 5 are output twice, followed by address values 6 to
8 can be output twice.

Example 3: When repeating a 99-bit pattern memory address, in order to repeatedly generate the same address, the branch source address memory 2 and the branch destination address memory 4 are shown in FIG. Such data is written in advance. That is, the value 100 is assigned to the address 0 of the branch source address memory 2, the value 99 is assigned to the address 1, the value 101 is assigned to the address 2, and the value 99 is assigned to the address 3.
The value 102 is written in the fourth address, the value 99 is written in the fifth address, and the value 103 is written in the sixth address. Further, the value 1 is assigned to the address 0 of the branch destination address memory 4, the value 101 is assigned to the address 1, the value 1 is assigned to the address 2, the value 102 is assigned to the address 3, and the value 1 is assigned to the address 4.
The value 103 is written in the address 5, and the value 1 is written in the address 6.

The operation of this example will be described with reference to the generated pattern memory address of FIG.

When the address counter 1 counts up from 0 and outputs the count value 100, the comparator 3
Sets the load pulse to "L". As a result, the address counter 1 branches to the count value 1 and counts up. When the count value 99 is output, the comparator 3 sets the load pulse to "L". As a result, the address counter 1 branches to the count value 101. The comparator 3 sets the load pulse to "L". As a result, the address counter 1 branches to the count value 1 and counts up. When the count value 99 is output, the comparator 3 sets the load pulse to "L". As a result, the address counter 1 branches to the count value 102. The comparator 3 sets the load pulse to "L". This allows
The address counter 1 branches to the count value 1 and counts up. When the count value 99 is output, the comparator 3 sets the load pulse to "L". As a result, the address counter 1 branches to the count value 103. The comparator 3 sets the load pulse to "L". As a result, the address counter 1 branches to the count value 1 and counts up to the count value 99.

As described above, in this example, the 99-bit pattern memory address can be repeatedly generated.

[0031]

As described above, according to the address control memory circuit of the present invention, the capacity of the memory required for one iteration is one address, and the occurrence of the repeated pattern which is a characteristic of the function tester test pattern. It is possible to use a small-capacity memory, and there is an effect that a test with a function tester can be realized even in a package that requires a long pattern that could not be tested with a conventional function tester.

[Brief description of drawings]

FIG. 1 is a block diagram of an address control memory circuit of the present invention.

FIG. 2 is a block diagram of a conventional address control memory circuit.

FIG. 3 is a diagram showing values written in a branch source address memory and a branch destination address memory.

FIG. 4 is a timing chart for explaining the operation of Example 1;

FIG. 5 is a diagram showing values written in a branch source address and a branch destination address.

FIG. 6 is a diagram showing values written in a branch source address and a branch destination address.

FIG. 7 is a diagram showing a repeat pattern memory address in Example 3;

[Explanation of symbols]

 1 Address Counter 2 Branch Source Address Memory 3 Comparator 4 Branch Destination Address Memory 5 Pointer Counter 6 Controller 7 Address Generation Memory 11 Pattern Memory Address 12 Branch Source Address 13 Load Pulse 14 Branch Destination Address 15 Pointer Address

Claims (3)

[Claims] 1. An address control memory circuit of a pattern memory used in a function tester, an address counter for counting addresses to generate a pattern memory address, a branch source address memory for storing a branch source address value, said pattern. A comparator for comparing a memory address with the branch source address value; a branch destination address memory for storing a branch destination address value; and a pointer counter for counting pointers of the branch source address memory and the branch destination address memory, The comparator causes the address counter to load the branch destination address value from the branch destination address memory when the pattern memory address and the branch source address value match, and when the pattern memory address and the branch source address value do not match. When the pointer counter is counted up, the address control memory circuit, characterized in that. 2. The address control memory circuit according to claim 1, wherein when the branch destination address value is loaded, the address counter counts up from the branch destination address value. 3. An address control memory circuit of a pattern memory used in a function tester, an address counter which counts up from 0 to generate a pattern memory address, and a branch source address memory which stores a branch source address value. A comparator that compares the pattern memory address with the branch source address value; a branch destination address memory that stores the branch destination address value; a counter address that counts up from 0 and points to the branch source address memory and the branch destination address memory And a comparator for causing the comparator to load the branch destination address value from the branch destination address memory by setting the output to “L” when the pattern memory address and the branch source address value match. Memory address and above When 岐元 address value and becomes mismatched, raised to "H" output, the address control memory circuit, characterized in that, to count up the pointer by the rising.