JPH0862301A - High speed pattern generator - Google Patents

Abstract

PURPOSE: To provide a high speed pattern generator capable of testing at a high speed a device to be measured, such as a flash memory, in which test flow is fluctuated. CONSTITUTION: A sequence control part 11 for outputting data to an operation control memory 12 is provided with a save register 300 for storing branching destination data branched in accordance with match signals from a logical comparator. An inhibiting gate 500 for inhibiting generation of an initial clock from an initial clock generation part in accordance with the match signal is provided to constitute a high speed pattern generator. The save register 300 stores output data of an incrementor 200 which adds 1 to an output match data of a sequencer 113, and imparts stored data to a selector 414 which selects data to be loaded on the sequencer 113.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test pattern generator for testing a device under test, and more particularly, it requires a plurality of operations for writing and erasing, like a flash memory, and the number of operations is The present invention relates to a high-speed pattern generator capable of testing a device under test whose test flow is not constant but fluctuates at high speed.

[0002]

2. Description of the Related Art Generally, in a semiconductor test apparatus, it is necessary to measure various devices under test at high speed, and it is necessary to generate a test pattern for that purpose.

FIG. 4 shows an example of the configuration of a semiconductor test apparatus for testing the quality of a device under test. FIG. 4 shows an example in which the device under test is a memory. Address, data, and control signals are supplied from the pattern generator 1 to the waveform shaper 2 for the memory under test. And the waveform shaper 2
Then, these signals are shaped, given to the memory under test 3 and written.

Next, the data read from the memory under test 3 is compared with the expected value signal output from the pattern generator 1 in the logical comparator 4. The output of the logical comparator 4 indicates whether the expected value and the output of the memory under test match, and is called a match signal. This match signal is fed back to the pattern generator 1 and gives a condition for defining the next generation pattern.

The fail memory 5 receives the fail signal equivalent to the match signal output from the logical comparator 4 and the FM address signal supplied from the pattern generator 1,
Fail information for each address is stored. The above series of operations are all performed in synchronization with the clock applied from the timing generator 6 to each unit.

FIG. 5 shows a block diagram of a conventional pattern generator. The operation control memory 12 is accessed by the data output from the sequence control unit 11. The output of the arithmetic control memory 12 is the address generator 13 and the data generator 1.
4. It is applied to the control signal generator 15 to generate an address signal, data, an expected value signal, and a control signal, respectively.

The sequence control unit 11 decodes the data stored in the sequence control memory 111 into the decoding unit 1.
The sequencer 113 performs decoding by 12, and increments, holds, loads data read from the register 115, and newly loads data read from the sequence control memory 111.
Is being applied to. The arithmetic control memory 12 is accessed by the output data of the sequencer 113, and arithmetic control of addresses, pattern data, etc. is performed.

In the pattern generator 1, the device under test 3
It is necessary to generate at high speed the address, pattern data, and control signal applied to the.

The reason why the high speed operation is required will be described, for example, in the case of address generation. FIG. 6 shows a block diagram of the address generator 13. The address generator 13
It is composed of an X address generation unit 131, a Y address generation unit 132, an address conversion unit 133, and the like. Each of the X and Y address generators performs an operation according to an instruction output from the operation control memory 12. Further, the X address and the Y address can be linked, and the Y address generating unit 132 is also controlled by the carry from the X address generating unit 131.
The address generated by each of the X and Y address generation units enters the address conversion unit 133, where the logical address is converted into the physical address and the converted address is output.

Since it is difficult to perform the above-mentioned series of operations within one test cycle, it is common to employ a pipeline structure of a plurality of stages and perform the preceding processing. FIG. 7 shows an example of division of operations by the pipeline structure. As shown in FIG. 7, the address operation is divided into a plurality of cycles for processing. In this case, since a plurality of cycles are required to generate an address to be applied to the device under test 3, the address calculation is performed by performing the preceding processing for that cycle.

When the device under test 3 is a device whose test flow varies, such as a flash memory, the above-described preceding process cannot be performed for the following reason. FIG.
A flowchart of the flash memory test for sequentially writing / reading addresses is shown in FIG. As shown in FIG. 8, in the case of a flash memory, the subsequent test flow changes depending on whether the verification result is pass or fail. In other words, in the case of flash memory,
Unlike the standard uniform test flow device, the sequence of pattern generation changes depending on the output result of the device under test, so that the preceding process cannot be performed.

Therefore, when measuring such a device under test whose test flow fluctuates, the following special processing is performed. (1) The sequencer 113 holds the output of the device under test 3 in the cycle of an instruction for checking the match between the output and the expected value (hereinafter referred to as a match instruction). (2) The device under test is read after the number of pipeline stages in the pattern generator, and the result, that is, the match signal, determines the branch destination of the sequencer. That is, in FIG. 8, the test flow is determined whether to proceed to the next address after the verification or to write to the same address again. (3) When the match signal returns to the pattern generator, the start / stop control unit 16 uses the match restart signal from the timing generator to start the initial clock generator 161 in the same manner as when starting from the system bus. To generate the initial clock. (4) The pipeline is refilled with the initial clock and the following pattern is applied to the device under test 3.

FIG. 3 shows a timing chart of the conventional pattern generator. In this way, at the time of a match instruction, even if the match signal is "0", the match signal is "
Even if it is 1 ", the operation rate must be slowed down in order to always perform the initialization of the pipeline, and there is a drawback that the test time becomes long.

[0014]

SUMMARY OF THE INVENTION The object of the present invention is to eliminate these drawbacks, and requires a plurality of operations for writing and erasing, such as a flash memory, and the number of times is not constant, and the test flow It is an object of the present invention to provide a high-speed pattern generator capable of testing a device under test whose fluctuations occur at high speed.

[0015]

In a pattern generator for testing a device under test, a logic comparator 4 is added to a sequence controller 11 which outputs data to an arithmetic control memory 12.
A save register 300 is provided for storing branch destination data that is branched according to the match signal from. Then, a high-speed pattern generator is configured by providing a prohibition gate 500 that does not generate the initial clock from the initial clock generation unit 161 according to the match signal.

The save register 300 stores the output data of the incrementer 200 which adds 1 to the output match data of the sequencer 113, and provides the stored data to the selector 414 which selects the data to be loaded into the sequencer 113. You may.

Further, the inhibit gate 500 applies the match restart signal from the timing generator 6 to one input terminal, applies the match signal to the other input terminal, and outputs the output to the initial clock generating section 161. It may be composed of an AND gate (500).

[0018]

According to the present invention, when the sequence control section 11 executes a match instruction, the sequencer 11 at that time
The output value of 3 plus the data of 1 is stored in the save register 300. Next, the sequencer 113 repeatedly executes the loop of the match instruction, that is, the program and the verify, assuming that the match cannot be obtained. Next, verification is performed after the number of pipeline stages in the pattern generator.
When the result is unmatched, the match signal is "0", and the AND gate 500 prohibits the match restart signal from the timing generator 6, so that the start / stop control unit 16 generates the initial clock. It will not be done. Next, when the result of the match is pass, the AND gate 500 takes the AND of the match restart signal and the match signal, and the start / stop control unit 16 generates an initial clock.
Refill the pipeline. Next, in the sequence controller 11, when the match signal is “1”, the data stored in the save register 300 is loaded into the sequencer 113 via the selector 414, and the match instruction loop is exited. To execute.

In this way, when no match is found, the pipeline generator is not initialized and the pattern generator operating clock is generated once. Then, the pipeline is initialized only when a match is found. Therefore, the test time can be shortened as compared with the conventional case.

[0020]

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a pattern generator showing an embodiment of the present invention. As shown in FIG. 1, the sequence control unit 11 is provided with an incrementer 200 that adds 1 to the output data of the sequencer 113 in the match cycle. Then, a save register 300 for storing the output data of the incrementer 200 is provided. Then, the output data of the save register 300 is set to the sequencer 113.
A selector 414 is provided for loading.

The start / stop control section 16 is provided with a prohibition gate which does not generate an initial clock from the initial clock generation section 161 when the match signal is "0". Therefore, an AND gate 500 that applies the match restart signal from the timing generator 6 to one input terminal and applies the match signal to the other input terminals is provided. Then, the output of the AND gate 500 is given to the initial clock generator 161. Thus, the pattern generator according to the present invention is constructed.

The operation is as follows. (1) When the sequence control unit 11 executes the match instruction, it stores the data of the output value of the sequencer 113 plus 1 at that time in the save register 300. This plus 1
The address of indicates the branch destination when the match signal is 1. (2) The sequencer 113 repeatedly executes the loop of the match instruction, that is, the program and the verify, assuming that the match cannot be obtained. Therefore, unlike the conventional case, the result of the verification performed after the number of pipeline stages in the pattern generator is not waited. (3) Verify is performed after the number of pipeline stages in the pattern generator. When the result is unmatched, the match signal is “0”, so the AND gate 500
Since the match restart signal from the timing generator 6 is prohibited, the start / stop control unit 16 does not generate an initial clock. Therefore, the next instruction is executed as it is. In this case, since the sequencer does not hold, the pipeline is full of instructions when a match cannot be obtained. (4) When the match result is a pass, the AND gate 500 takes the AND of the match restart signal and the match signal, the start / stop control unit 16 generates an initial clock, and the pipeline is refilled. . (5) In the sequence controller 11, the match signal is "1"
At this time, the data stored in the save register 300 is loaded into the sequencer 113 via the selector 414, the loop of the match instruction is exited, and the next instruction is executed.

FIG. 2 shows a timing chart according to the present invention. According to the present invention, in the test of a flash memory or the like, when no match is found, the pipeline generator is not initialized and the pattern generator operation clock is generated once. Then, the pipeline is initialized only when a match is found. Therefore, the test time can be shortened as compared with the conventional case.

[0025]

Since the present invention is configured as described above, it has the following effects. It is possible to provide a high-speed pattern generator, such as a flash memory, that requires multiple operations for writing and erasing, and the number of times is not constant, and that allows devices under test with varying test flows to be tested at high speed. It was

[Brief description of drawings]

FIG. 1 is a block diagram of a pattern generator showing an embodiment of the present invention.

FIG. 2 shows a timing chart according to the present invention.

FIG. 3 shows a timing chart of a conventional pattern generator.

FIG. 4 shows a configuration example of a semiconductor test apparatus for testing the quality of a device under test.

FIG. 5 shows a block diagram of a conventional pattern generator.

FIG. 6 shows a block diagram of an address generator 13.

FIG. 7 shows an example of division of operations by a pipeline structure.

FIG. 8 shows a flowchart of a flash memory test when addresses are sequentially written / read.

[Explanation of symbols]

 1 pattern generator 2 waveform shaper 3 memory under test 4 logical comparator 5 fail memory 6 timing generator 11 sequence controller 12 arithmetic control memory 13 address generator 14 data generator 15 control signal generator 16 start / stop controller 111 Sequence control memory 112 Decoding unit 113 Sequencer 114, 414 Selector 115 Register 161 Initial clock generating unit 200 Incrementer 300 Save register 500 AND gate

Claims (3)

[Claims] 1. A pattern generator for testing a device under test branches to a sequence control section (11) which outputs data to an operation control memory (12) in response to a match signal from a logical comparator (4). The save register (300) for storing the branch destination data is provided, and the inhibition gate (500) that does not generate the initial clock from the initial clock generation unit (161) according to the match signal is provided. The featured high-speed pattern generator. 2. The save register (300) stores the output data of the incrementer (200) for adding 1 to the output match data of the sequencer (113), and a selector (for selecting data to be loaded into the sequencer (113) ( The high-speed pattern generator according to claim 1, which is a save register (300) for giving stored data to 414). 3. The inhibit gate (500) applies the match restart signal from the timing generator (6) to one input terminal and applies the match signal to the other input terminal, and outputs the output to the initial clock generator. The high-speed pattern generator according to claim 1 or 2, which is an AND gate (500) given to (161).