JPH0714913Y2 - Frequency counter device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a frequency counter device for counting the frequency of a signal output from, for example, a wireless device.

(Prior Art) As is well known, a frequency counter device is used to count the frequency of a signal output from a radio device or the like.

FIG. 2 shows a conventional frequency counter device.
This frequency counter device has input terminals 11 and 12 to which two systems of signals Sa and Sb are input, a switch 13 that switches between these input terminals 11 and 12, an amplifier 14 that amplifies a signal input through this switch 13, A frequency divider circuit 15 for dividing the frequency of the signal output from the amplifier 14 into 1 / N, which is composed of a counter 16 for counting the output signal of the frequency divider circuit 15. The count value of the counter 16 is multiplied by N. The frequency of the input signal is obtained by.

(Problems to be Solved by the Invention) By the way, when measuring a high frequency of, for example, 1000 MHz by the conventional frequency counter device, sufficient isolation is obtained even when a high frequency relay or a coaxial switching device is used as the switch 13. You can't get it. Therefore, when the input signal Sa is selected by the switch 13, when the input signal Sb is also supplied, the input signal Sb is mixed with the input signal Sa,
It causes a miscount. This is particularly noticeable when the level of the unselected signal is large compared to the selected signal.

This invention solves the above-mentioned conventional problems, and an object thereof is to provide a frequency counter device capable of sufficiently securing isolation of a plurality of input signals and preventing miscounting. It is the one we are trying to provide.

[Means for Solving the Problems] (Means for Solving the Problems) In order to solve the above problems, the present invention divides a plurality of input signals and converts a plurality of input signals into logical levels. A selection circuit for selecting the signals output from these frequency dividing circuits and a counter circuit for counting the signals selected by the selection circuit.

(Operation) That is, in the present invention, since the plurality of input signals are respectively divided by the plurality of frequency dividing circuits, and the input signals are converted into the logical level and then selected by the selecting means, the input signals are high frequency signals. However, the isolation can be sufficiently ensured by the simple and inexpensive selection means, and the miscount can be prevented.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, a high frequency signal of, for example, about 30 mV to 1 V is supplied to the input terminal 21. A high frequency signal of about 10 W is supplied to the input terminal 22. This input terminal 22 is the output terminal 23
The antenna 24 is connected to the output terminal 23. The input terminal 21 is connected to an amplifier 25,
The input terminal 22 is connected to the amplifier 27 via the attenuator 26. The attenuator 26 attenuates the signal supplied to the input terminal 22 to the same level as the signal supplied to the input terminal 21.

The output terminals of the amplifiers 25 and 26 are frequency dividing circuits 28 and 29, respectively.
The frequency of the signals output from the amplifiers 25 and 26 is divided into 1 / N by the frequency dividing circuits 28 and 29. Further, the input signal is divided into 1 / N by these frequency dividing circuits 28 and 29, so that, for example, ECL (Emit
ter Coupled Logic) etc. and converted into a pulse signal of a logic level. The signal divided by 1 / N and converted into a logic level such as ECL is supplied to a gate circuit 30 as a selection means, and one signal is selected by the gate circuit 30. The signal selected by the gate circuit 30 is supplied to the counter circuit 31 and counted. This count value is multiplied by N to obtain the frequency of the input signal.

According to the above-described embodiment, the plurality of frequency dividing circuits 28 and 29 respectively divide the plurality of input signals and convert the input signals into a logic level such as ECL, and then select them by the gate circuit 30. Therefore, since the signal selected by the gate circuit 30 has a logic level, sufficient isolation can be ensured by a simple and inexpensive circuit, and the counter circuit
It is possible to prevent the miscount in 31.

Further, in the above-mentioned configuration, the number of amplifiers and frequency dividing circuits is increased as compared with the conventional one, but since these circuits are integrated circuits and are inexpensive, when an expensive high-frequency relay or the like is used as in the conventional case. Compared with the above, the manufacturing cost of the device can be reduced.

In the above embodiment, the case where the input signal has two systems has been described, but the present invention is not limited to this, and it is possible to have two or more systems.

In addition, it goes without saying that various modifications can be made without departing from the scope of the invention.

[Advantages of the Invention] As described in detail above, according to the present invention, a plurality of frequency dividing circuits respectively divide a plurality of input signals, and the input signals are converted into logical levels and then selected by the selecting means. Therefore, even if the input signal is a high frequency signal, isolation can be sufficiently ensured by a simple and inexpensive selection means, and a frequency counter device capable of preventing miscount can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of a conventional frequency counter device. 21, 22 …… Input terminal, 28, 29 …… Divider circuit, 30 …… Gate circuit, 31 …… Counter circuit.

Claims (1)

[Scope of utility model registration request] 1. A plurality of frequency dividing circuits for respectively dividing a plurality of input signals and converting the input signals into logical levels, a selecting means for selecting signals output from the frequency dividing circuits, and a selecting means. And a counter circuit for counting the signals selected by the frequency counter device.