JPH07154232A - Semiconductor circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] To obtain a semiconductor output circuit capable of preventing generation of excessive shoot-through current and noise accompanying it. [Configuration] One is turned on and the other is turned off according to the input data connected in series between a data input terminal to which input data is added and a high-voltage side power source and a low-voltage side power source, and a connection middle point is a data output An output buffer having a first switching element and a second switching element, which is an end, and is connected between the input terminal and each of the control terminals of the first and second switching elements. Among the switching elements, a control unit that controls to turn off the switching element in the on state first and then turn on the switching element in the off state is configured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI output device and is used for an LSI output circuit.

[0002]

2. Description of the Related Art Recently, LSI is used not only in industrial equipment but also in familiar household appliances, calculators, clocks, etc.
Is being actively developed. It is expected that this trend will become more prominent in the future. Recently, the number of LSIs driven by a built-in battery is increasing. Of the LSIs used in various applications as described above, for example, an LSI that operates at low power / low current consumption in consideration of the life of the built-in battery,
Development of an LSI used for a communication device or the like that realizes reduction of influence of power supply noise caused by a change in current is emphasized.

FIG. 3 shows an example of a semiconductor output circuit used in a conventional LSI. This is the input data D
Is a circuit that outputs or does not output according to the logic “0” or logic “1” of the circuit enable signal EN. This circuit is configured as follows. That is, the data D is the first N
It is input to one input terminal of the AND gate 1. This first
The output end of the NAND gate 1 is connected to one input end of the second NAND gate 2 in the pre-buffer PB and the input end of the inverter 3 at the node N1. The circuit enable signal EN is applied to the other input end of the first NAND gate 1,
It is connected to the other input terminal of the second NAND gate 2. The output of the pre-buffer PB is the output buffer OB of the next stage.
Added to. That is, the first transistor Tr1 and the second transistor Tr2 are connected in series between the high-potential-side and low-voltage-side power supply potentials, and the midpoint thereof is the output terminal 8. The second N is connected to the gate G1 of the first transistor Tr1.
The output terminal of the AND gate 2 is connected. The output terminal of the inverter 3 is connected to the gate G2 of the second transistor Tr2.

Next, the operation of the semiconductor output circuit will be described. In this circuit, the circuit enable signal EN is set to logic "0" when it is not necessary to output data and in the power save state. As a result, the first NA
The output of the ND gate 1 becomes the logic "1", and the second NAND
The output of the gate 2 is logic "1" and the output of the inverter 3 is logic "0". As a result, both the first and second transistors are turned off, and the circuit output OUT becomes indefinite. on the other hand,
When outputting data, the circuit enable signal EN is logic "1"
It is said that As a result, the output of the first NAND gate 1 becomes dependent on the data D, and therefore the second NAND gate 1
The output of the gate 2 and the output of the inverter 3 are also determined by the data D. As a result, the first and second transistors are turned on, off, off, and on, respectively, depending on the data D, and the output data OUT that is the inverted data D is output. More specifically, when the data D is logic “0”, the output of the first NAND gate 1 becomes logic “1”,
The output of the second NAND gate 2 is a logical "0", and the output of the inverter 3 is a logical "0". As a result, the first transistor Tr1 is turned on and the second transistor Tr2 is turned off. As a result, when the data D is the logical "0", the logical "1" is output to the output data OUT. On the other hand, data D
Is logical "1", the output of the first NAND gate 1 is logical "0", the output of the second NAND gate 2 is logical "1", and the output of the inverter 3 is logical "1". As a result, the first transistor Tr1 is turned off and the second transistor Tr2 is turned on. Thus, when the data D is logic "1", the logic "0" is output to the output data OUT.

Now, consider the case where the circuit enable signal EN changes from logic "0" to logic "1" in the circuit of FIG.

As shown in FIG. 4, when the circuit enable signal EN changes from the logic "0" to the logic "1" at time t ₁ , the output data OUT, which has been indefinite until then, becomes the logic "0" of the input data D. Outputs a dependent output, logic "1". Thereafter, when the input data D at time t ₂ is changed to a logic "1" from a logical "0", instantaneously first and second transistors are rendered conductive at the same time, a through current I _OUT flows. This is also true when the input data D at time t ₃ is changed to a logic "0" from logic "1".

[0007]

As described above, in the conventional output circuit, the first and second transistors momentarily become conductive at the same time, and the through current flows. Also, the first
As the second transistor, a transistor having a large transistor size is usually used in order to obtain a sufficient driving capability, and therefore the above-mentioned through current value also becomes extremely large. As a result, not only the power consumption is large, but also the power supply ringing occurs in the LSI due to the shoot-through current, which causes noise.

The present invention has been made in view of the above, and an object thereof is to obtain a semiconductor output circuit which prevents generation of an excessive shoot-through current and accompanying noise in an output circuit of an LSI.

[0009]

A first output circuit of the present invention responds to a data input terminal to which input data is applied and the input data connected in series between a high voltage side power source and a low voltage side power source. Output buffer having a first switching element and a second switching element, one of which is turned on and the other of which is turned off, and a middle point of connection is a data output terminal; and the input terminal and the first and second switching elements Of the first and second switching elements, the control means being connected to the control end of the switching element and turning off the switching element in the on state and turning on the switching element in the off state. To be done. In a second output circuit of the present invention, in the first output circuit, the control means is connected between the input end and one of the control ends of the first and second switching elements, and an input is provided. Only the rising edge that changes the logic "0" of the data according to the data to the logic "1" is delayed and output, and the logic "1" of the data changes according to the input data to the logic "0". The falling edge is connected between the rising edge delay means for outputting the falling edge as it is without delay, and the input end and the other control end of the first and second switching elements,
Logic "1" to logic "0" of the data according to the input data
Falling edge delay that delays and outputs only the falling edge that changes to, and outputs the rising edge that changes from logic "0" to logic "1" of the data according to the input data without delay. And means.

According to a third output circuit of the present invention, in the second output circuit, the rising edge delay means delays and outputs only a rising edge of data according to input data, and the delay circuit. A delay circuit for delaying and outputting only the falling edge of the data according to the input data, and a gate for taking a logic between the output of the circuit and the data according to the input data. ,
It is configured to have a gate that takes the logic of the output of this delay circuit and the data corresponding to the input data.

According to a fourth output circuit of the present invention, in the first output circuit to the third output circuit, the output of the control means and the control terminals of the first and second switching elements in the output buffer are provided. And a pre-buffer for controlling the output buffer by any one of the logic gates.

A fifth output circuit of the present invention is the first output circuit to the fourth output circuit, wherein the first and second switching elements in the output buffer are CMOs.
It is configured as, which is an S structure.

[0013]

The input data applied to the input terminal changes from logic "0" to logic "1" or logic "1" to logic "0".
Change to the first,
The timing is shifted to the second switching element. This prevents the first and second switching elements from turning on at the same time, and prevents a through current from flowing between these switching elements.

[0014]

1 is a circuit diagram of an embodiment of the present invention. This embodiment is a circuit that prevents simultaneous conduction of the first and second transistors to prevent a shoot-through current. The circuit of FIG. 1 is different from the circuit of FIG.
A delay circuit D is provided between the AND gate 1 and the pre-buffer PB.
It is at the point where L is connected. The delay circuit DL is a circuit in which the rising edge delay circuit 6 and the falling edge delay circuit 7 shift the on / off timings of the first and second transistors. The node N1 on the output side of the first NAND gate 1 is directly connected to one input end of the AND gate 4 in the delay circuit DL and is connected to the other input end via the rising edge delay circuit 6. The rising edge delay circuit 6 delays only the rising edge of the input data and outputs the falling edge without delay. That is, the rising edge delay circuit 6 delays the change only when the input data changes from the logic "0" to the logic "1", and the falling edge changing from the logic "1" to the logic "0" is It is a circuit that outputs as it is without delay. On the other hand, the node N1 is directly connected to one input end of the OR gate 5 and is connected to the other input end via the falling edge delay circuit 7. The falling edge delay circuit 7 delays only the falling edge and outputs the rising edge without delay. That is, the falling edge delay circuit 7 delays the change only when the input data changes from the logic "1" to the logic "0", and delays the rising edge changing from the logic "0" to the logic "1". It is a circuit that outputs without change.

The delay circuit DL having such a configuration is connected to the pre-buffer PB. That is, the output P1 of the AND gate 4 is applied to one input terminal of the second NAND gate 2. On the other hand, the output P2 of the OR gate 5 is applied to the input terminal of the inverter 3.

Since the circuit is the same as the circuit of FIG. 3 except for the above-mentioned configuration, the same components are designated by the same reference numerals and the description thereof will be omitted.

Next, the operation of the circuit shown in FIG. 1 will be described. The circuit as can be seen from the time chart of FIG. 2, the first transistor T at time t ₂ in the input data D when changes to a logic "1" from a logical "0" First time t ₂
r1 second transistor Tr2 is turned on is turned off and the time t _3, whereas, the time t input data D from a logic "1" to ₄ at time t ₄ when changes to a logic "0" second transistor T
This is a circuit for preventing a shoot-through current by turning off r2 and turning on the first transistor Tr1 at time t ₅ .

The details will be described below with reference to the timing chart. That is, when the circuit enable signal EN changes to logic "1" at time t ₁ , the output data OUT changes according to the input data D. At time t ₂ , when the input data D changes from the logical “0” to the logical “1”, the first NA
The output of the ND gate 1 becomes a falling signal of logic "1" to logic "0". This falling signal is input from node N1 to delay circuit DL. That is, the first NAND gate 1
The output from is input to one input end of the AND gate 4, is also input to the other input end via the rising edge delay circuit 6, and is also input to one input end of the OR gate 5. At the same time, it is input to the other input terminal via the falling edge delay circuit 7. Data that is input to the AND gate 4, because it is not delayed by the rising edge delay circuit 6, the output P1 of the AND gate 4 changes to the time t ₂ from the logic "1" to a logic "0". As a result, the output of the 2NAND gate 2 changes to a logic "1" from a logical "0" at time t _2. On the other hand, since the data input to the OR gate 5 is delayed by the falling edge delay circuit 7, the output signal P of the OR gate 5 is output.
2 is changed to a logic "0" from logic "1" at time t _3. As a result, the output of the inverter 3 changes to a logic "1" from a logical "0" at time t _3. Therefore, time t
_{At 2} the gate G1 of the first transistor Tr1 is logic "0"
From the logic "1" to the second transistor Tr
The second gate G2 changes from logic “0” to logic “1” at time t _3.
Changes to. This, after the first transistor Tr1 is turned off at time t _2, the second transistor Tr2 is the time t
Turn on at ₃ . Therefore, since the first and second transistors do not conduct at the same time, no through current flows. Also, at time t ₄
At time t ₂ , the data D changes from the logic "1" to the logic "0", and the output of the first NAND gate 1 becomes a rising signal of the logic "0" to the logic "1". This rising signal is input to the delay circuit DL. At this time, since the signal input to the AND gate 4 is delayed by the rising edge delay circuit 6, the AND gate 4
Output P1 of the changes in time t ₅ from the logic "0" to a logic "1". As a result, the output of the 2NAND gate 2 changes to a logic "0" from logic "1" at time t _5.
On the other hand, since the signal input to the OR gate 5 is not delayed by the falling edge delay circuit 7, the OR gate 5
The output of the P2 is changed to a time t ₄ from the logic "0" to a logic "1". As a result, the output of the inverter 3 is time t ₄
Changes from logic "1" to logic "0". Therefore, after the gate G2 of the second transistor Tr2 at time t ₄ is changed to a logic "0" from logic "1", logic "from logic" 1 "the gate G1 of the first transistor Tr1 is at time t ₅ 0 It changes to ". This, after the second transistor Tr2 is turned off at time t _4, the first transistor Tr
1 turns on at time t ₅ . Therefore, since the first and second transistors do not conduct at the same time, no through current flows. In this way, it becomes possible to prevent a through current from flowing.

According to the embodiment of the present invention, the delay circuit DL is used to shift the output timing of the pre-buffer PB so as to prevent simultaneous conduction of the first and second transistors. Can be prevented.
Note that the interval between the times t ₂ and t ₃ and the interval between the times t ₄ and t ₅ can be shortened to speed up the confirmation of the data. At this time, even if the distance between them is made too short and a through current flows, there is no problem as long as the current value is within the allowable range . Further, the interval between the times t ₂ and t ₃ may not be equal to the interval between the times ₄ and t ₅ . By reducing the through current in this manner, power supply noise can be suppressed and power consumption can be suppressed. In addition, since the newly required circuit is only the delay circuit DL, it is possible to suppress the increase of the circuit pattern area as much as possible. From the above, this embodiment can be applied to all LSI circuits.

[0020]

According to the present invention, even if the level of the input data at the input end changes, those changes are transmitted to the first and second switching elements with a shifted timing. The through current flowing through the second switching element can be suppressed as much as possible.

[Brief description of drawings]

FIG. 1 is a semiconductor output circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart of the semiconductor output circuit of FIG.

FIG. 3 is a conventional semiconductor output circuit.

FIG. 4 is a timing chart of the semiconductor output circuit of FIG.

[Explanation of symbols]

 1 1st NAND gate 2 2nd NAND gate 3 inverter 4 AND gate 5 OR gate 6 rising edge delay circuit 7 falling edge delay circuit 8 output terminal DL delay circuit PB pre-buffer Tr1 first transistor Tr2 second transistor

Claims (5)

[Claims] 1. A data input terminal to which input data is added, and one of which is turned on and the other of which is turned off according to the input data connected in series between a high-voltage side power source and a low-voltage side power source An output buffer having a first switching element and a second switching element, which is a data output terminal, is connected between the input terminal and respective control terminals of the first and second switching elements, and the first, Among the second switching elements, a control unit that controls to turn off the switching element in the on state first and then turn on the switching element in the off state, the output circuit. 2. The control means is connected between the input end and one of the control ends of the first and second switching elements, and has a logic "0" to a logic "0" depending on input data. Only the rising edge that changes to 1 "is delayed and output, and the falling edge that changes from logic" 1 "to logic" 0 "of the data according to the input data is output as it is without delay. The delay means is connected between the input end and the other control end of the first and second switching elements, and the falling edge of the data changes from logic "1" to logic "0" according to the input data. Falling edge delay means for delaying and outputting only the edge and outputting the rising edge of the data corresponding to the input data changing from the logic "0" to the logic "1" without delay as it is. The output circuit of claim 1, wherein the obtaining. 3. The rising edge delay means delays and outputs only the rising edge of the data corresponding to the input data, and a gate that takes the logic of the output of the delay circuit and the data corresponding to the input data. The falling edge delay means delays and outputs only a falling edge of data corresponding to input data, and a logic of an output of the delay circuit and data corresponding to the input data. The output circuit according to claim 2, further comprising: 4. A logic gate connected between the output of the control means and the control ends of the first and second switching elements in the output buffer, and the output buffer is provided by any one of the logic gates. The output circuit according to claim 1, further comprising a pre-buffer for controlling the output signal. 5. The first and second output buffers
The output circuit according to claim 1, wherein the switching element has a CMOS structure.