JPH07154355A - Line multiplexing method and circuit - Google Patents

Abstract

(57) [Summary] [Object] To realize a line multiplexing method and apparatus capable of multiplexing both data signals without limitation on the phase difference between the two data signals respectively input from the two lines. [Structure] Two variable delay circuits for delay insertion / removal 1
Two data signals input from one line are delayed by an arbitrary number of bits, respectively, and two delayed data signals obtained by inserting / removing an arbitrary amount of delay are used as two velocity conversion elastic stores. Each of them is written into the memory 2 and read out at a speed twice as fast as that of writing, and two read data signals are multiplexed by the multiplexing selection circuit 3 to obtain a desired output multiplexed signal. By the phase control circuit 4,
Based on the phase information of the two data signals and the phase information of the output multiplexed signal, the delay amount of the variable delay circuit for delay insertion / removal 1 is adjusted and the delay insertion / removal is performed, and the write phase and the read of the elastic store memory 2 for speed conversion Control the phase and
It enables multiplexing without limitation on the phase difference between two data signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a circuit multiplexing circuit,
The present invention relates to a circuit multiplexing circuit in a receiving circuit of a high speed digital subscriber line transmission system.

[0002]

2. Description of the Related Art In a conventional line multiplexing circuit, as shown in FIG. 2, first and second data signals a and b input via two lines are based on respective phase information signals c and d. First and second speed conversion elastic store memories 2-1 and 2-2, which perform writing in a writing phase and perform reading at a speed twice that of writing based on the phase information signal d of the second data signal b. And a multiplexing selection circuit 3 for multiplexing two data signals read from the first and second velocity conversion elastic store memories 2-1 and 2-2.
And a phase control circuit 4 for controlling the read phase pulse of the first and second velocity conversion elastic store memories 2-1 and 2-2 based on the phase information d of the second data signal b. , A phase conversion elastic store memory 7 for obtaining an output multiplexed signal f having a required phase from the multiplexed signal, and a phase adjustment for avoiding a collision between writing and reading in the phase conversion elastic store memory 7. A delay circuit for delay insertion / removal 5, a delay insertion / removal switching selection circuit 6,
And a delay insertion / removal control circuit 8.

In this conventional line multiplexing circuit, the first and second elastic store memories 2-1 for speed conversion are provided.
The read phase of the data from 2-2 is the first and the second velocity conversion elastic store memories 2-1 and 2-2.
In order to avoid a collision of writing and reading in the inside, it is determined by the writing phase of data, but the output of the first speed conversion elastic store memory 2-1 and the second speed conversion elastic store memory 2-2 In order to match the phase of the output of the first speed conversion elastic store memory 2-1 based on the phase information d of the second data signal b.
And the read phase of the second velocity conversion elastic store memory 2-2 are determined. These first and second elastic store memories for speed conversion 2-
Since the phases of the output data from 1 and 2-2 are in agreement with each other, they are multiplexed by the multiplexing selection circuit 3 without phase shift. Finally, the elastic store memory 7 for phase conversion,
A desired output phase is obtained by the delay insertion / removal delay circuit 6, the delay insertion / removal switching circuit 6, and the delay insertion / removal control circuit 8.

[0004]

In the conventional line multiplexing circuit, the write phases of the first and second speed conversion elastic store memories 2-1 and 2-2 are the same as those of the first and second data. Although it is based on the phase information c and d of the signals a and b, respectively, but the read phase is based only on the phase information d of the second data signal b, so the first velocity conversion elastic store memory is used. There is no correlation between the write phase and the read phase of the read phase of 2-1 and there is a fear of collision between write and read in the first velocity conversion elastic store memory 2-1. In order to avoid this danger, there is a problem that the range of the phase difference between the first data signal and the second data signal to be multiplexed is limited.

[0005]

According to the present invention, first and second data signals respectively transmitted at a constant speed via two lines are multiplexed to multiplex signals at a double speed. In the line multiplexing method for obtaining the above, the first and second data signals from the two lines are respectively delayed and added / removed to form first and second delayed data signals having the same phase, The first and second delayed data signals are written to the first and second memories as first and second stored data signals with a constant write phase, and the first and second memories are used to write the first and second memories. The second stored data signal is read as the first and second read data signals at the double speed and at the read phase that does not collide with the write phase, and the first and second read data signals are read. Multiplexes the read data signal line multiplexing method characterized by making the multiplexed signal is obtained.

Further, according to the present invention, the first and second data signals respectively transmitted at a constant speed through the two lines are multiplexed to obtain a multiplexed signal having a double speed. In the line multiplexing circuit, the first and second data signals from the respective lines are respectively input, and delay and delay insertion / removal are applied to the respective lines to produce first and second delayed data signals in phase with each other. First and second variable delay circuits for delay insertion and removal, and first and second delayed data signals are written respectively as first and second stored data signals with a constant write phase to store the first and second stored data signals. First and second speeds at which the data signal is read as the first and second read data signals at the double speed and the read phase that does not collide with the write phase. And the changeover Hellas Thich store memory,
A multiplexing selection circuit that multiplexes the first and second read data signals and outputs the multiplexed signal, phase information of each of the first and second data signals, and a phase of the output multiplexed signal. Based on the information, the delay amount adjustment and delay insertion / removal of the first and second delay insertion / removal variable delay circuits, and the write phase and the read phase of the first and second speed conversion elastic store memories are performed. A line multiplexer provided with a phase control circuit for controlling.

[0007]

The present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. The line multiplexing circuit according to the present embodiment receives the first and second data signals a and b from the respective lines as input and delays and delays the signals into and outputs them from the first and second phase-matched circuits. First and second variable delay circuits for delay insertion / removal 1-1 and 1-2 for producing delayed data signals, and these first and second delayed data signals are fixed as first and second stored data signals, respectively. Writing with the write phase of, and reading the first and second stored data signals as the first and second read data signals at the double speed and with the read phase that does not collide with the write phase. First and second velocity conversion elastic store memories 2-1, 2-2, and multiplexing for multiplexing the first and second read data signals and outputting the multiplexed signal Based on the selection circuit 3, the phase information c and d of the first and second data signals a and b, and the phase information e of the output multiplexed signal, the first and second delay insertion / removal variable delays. The delay amounts of the circuits 1-1 and 1-2 are adjusted, the delay insertion / removal is controlled, and the write phase and the read phase of the first and second velocity conversion elastic store memories 2-1 and 2-2 are controlled. And a phase control circuit 4.

First data signal a and second data signal b
Are the first and second variable delay circuits 1 for delay insertion and removal, respectively.
-1, 1-2 are input. In the first and second variable delay circuits 1-1 and 1-2 for delay insertion / removal, the phase of the first data signal a is changed by the first and second delay control signals g and h from the phase control circuit 4. And the second data signal b are delayed so that the two signals have the same phase, and the first and second elastic store memories 2-1 and 2-2 for speed conversion are provided.
The first and second delayed data signals are created by delaying the first data signal a and the second data signal b in a phase such that write and read collisions in each of the two do not occur. These first and second delayed data signals are converted into first and second velocity conversion elastic store memories 2-1 and 2-2.
Then, by the first and second memory write pulses i, j from the phase control circuit 4, they are stored as write first and second stored data signals, respectively. First and second velocity conversion elastic store memories 2-1, 2-2
Then, the first and second stored data are read at a double speed by the first and second memory read pulses k and l from the phase control circuit 4, and the first and second delay data are read. A first read data signal and a second read data signal are generated by speed conversion of the signal and phase conversion into a required output phase, and output to the multiplexing selection circuit 3. The multiplexing selection circuit 3 multiplexes the first and second read data signals and outputs them as an output multiplexed signal f. In the phase control circuit 4, the phase information c of the first data signal input from the first line, the phase information d of the second data signal input from the second line, and the phase information of the required output multiplexed signal. By e
First and second variable delay circuits for delaying / inserting 1-1, 1-
The first and second delay control signals g and h for controlling the delay amount of 2 are generated, and the write phases of the first and second velocity conversion elastic store memories 2-1 and 2-2 are First and second memory write pulses i, j and first and second memory read pulses k, l for controlling the read phase are generated.

[0010]

As described above, the present invention can adjust the delay between two lines based on the phase information of the first and second data signals received from the two lines and the phase information of the output multiplexed signal. Since the configuration is such that the speed phase conversion is performed thereafter, there is an effect that multiplexing can be performed without limitation on the phase difference between the received first data signal and second data signal.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a line multiplexing circuit of the present invention.

FIG. 2 is a block diagram of a conventional multiplexing circuit.

[Explanation of symbols]

1-1 First Delay Insertion / Extraction Variable Delay Circuit 1-2 Second Delay Insertion / Extraction Variable Delay Circuit 2-1 First Velocity Phase Conversion Elastic Store Memory 2-2 Second Velocity Phase Conversion Elastic store memory 3 Multiplexing selection circuit 4 Phase control circuit 5 Delay insertion / extraction delay circuit 6 Delay insertion / extraction switching selection circuit 7 Phase conversion elastic store memory 8 Delay insertion / extraction control circuit a First data signal b Second data signal c Phase information signal of first data signal d Phase information signal of second data signal e Phase information signal of output multiplexed signal f Output multiplexed signal g First delay amount control signal h Second Delay amount control signal i First memory write pulse j Second memory write pulse k First memory read pulse l Second memory read pulse m Delay insertion / removal switching control signal

Claims (2)

[Claims] 1. A circuit multiplexing method for multiplexing a first and a second data signal respectively transmitted at a constant speed through two lines to obtain a multiplexed signal having a double speed, The first and second delay data signals from the two lines are respectively delayed and inserted into and removed from each other to form first and second delay data signals having the same phase, and the first and second delay data signals are generated. Are written to the first and second memories as the first and second stored data signals with a constant write phase, and the first and second stored data signals are doubled from the first and second memories. At the same speed and with a read phase that does not cause a collision with the write phase, the first and second read data signals are read, and the first and second read data signals are multiplexed. Line multiplexing method characterized by making the multiplexed signal Te. 2. A line multiplexing circuit for multiplexing a first and a second data signal respectively transmitted at a constant speed through two lines to obtain a multiplexed signal having a double speed, First and second delays for inputting the first and second data signals from the respective lines and applying delay and delay insertion / removal to each to produce first and second delayed data signals in phase with each other A variable delay circuit for insertion / removal, and the first and second delayed data signals are written as the first and second stored data signals with a constant write phase, and the first and second stored data signals are doubled as described above. First and second velocity conversion elastics for reading as the first and second read data signals at a read phase that does not collide with the write phase at the speed of A memory, a multiplexing selection circuit for multiplexing the first and second read data signals and outputting the multiplexed signal, phase information of the first and second data signals, and the output multiplexing Adjustment of the delay amount of the first and second variable delay circuits for delay insertion / removal and delay insertion / removal according to the phase information of the signal, and write phase and read of the first and second speed conversion elastic store memories And a phase control circuit for controlling the phase.