JPH0715547B2 - Flash photography device with automatic and manual dimming - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic flash light emitting device (hereinafter, referred to as a flash device) whose light emission amount can be controlled automatically and manually, and particularly to a camera or a flash device in which the flash device is incorporated. The present invention relates to a flash device in which a control mode is switched according to the state of a connected camera, and a flash photography system including such a camera and a flash device.

2. Description of the Related Art A so-called automatic light control function, which measures the reflected light of a subject illuminated by light from a light emitter and stops the light emission of the light emitter when the integrated value reaches a predetermined level, and the function of the automatic light control Stop and let the light emitting part emit light to the end, that is, until the main capacitor is fully used up (full light emission), or according to the manual setting, the light emitting part emits 1/2 or 2/3 of the total light emission amount.
There is known a flash device having a manually adjusted light emission function of making only the light emission. Such a flash device is provided with automatic exposure control, that is, automatic control of aperture value and shutter speed,
Used with a camera capable of three kinds of control, that is, automatic control of shutter speed based on aperture value and automatic control of aperture value based on shutter speed, and manual exposure control, that is, control of manually setting aperture value and shutter speed. In this case, the following problems occur. That is, when the camera is set to the manual exposure control mode, the photographer often intentionally selects such a mode in anticipation of a special exposure effect. It is considered that automatic dimming or manual dimming light emission mode is set under a specific intention. However, when the camera is set to the automatic exposure control mode, the photographer leaves it to the camera to determine the exposure, and if the flash device fires a manually set amount regardless of the exposure control of the camera, It is likely that overexposure will occur by the amount of time, and such overexposure is more likely when the photographer inadvertently forgets to switch the flash device from manual to automatic than was intended by the photographer. .

It is an object of the present invention to prevent shooting of improper exposure due to carelessness of the photographer as described above when using a flash device capable of automatic / manual flash control with a camera capable of automatic / manual exposure control. Another object of the present invention is to provide a flash photography system and a flash device used in the system.

In order to achieve the above object, in the present invention, a mode in which the camera automatically controls the aperture value and the shutter speed, a mode in which the shutter speed is automatically controlled based on the aperture value, a mode in which the aperture value is automatically controlled based on the shutter speed, and a manual The camera outputs a signal indicating which one of the modes in which the aperture value and the shutter speed are determined by the flash device, the flash device detects this signal, and the signal is automatically output from the previous three types. When the mode for controlling the exposure is shown, the light emission amount is automatically controlled even if the flash device is set to the manual adjustment light emission mode.

Here, when the flash device is ready to emit light (for example, when charging of the main capacitor is completed or when the power switch is closed), a ready signal is output, and the camera side responds to this signal for flash photography. If the exposure control mode is set, more appropriate exposure control can be performed by linking the camera and the flash device.

First Embodiment FIG. 1 is a block diagram showing the overall configuration of a flash photography system to which the present invention is applied. In this figure and the following circuit diagrams and block diagrams, thick lines indicate a plurality of signal lines,
The thin line indicates one signal line. (V) is an interchangeable-lens single-lens reflex camera body.
Connector for electrical connection to flash unit (CN
9) and (CN3) are provided. The connector (CN9) is provided on a hot shoe (not shown) on the top of the camera, and when an electronic flash light emitting device (hereinafter referred to as a flash device) is attached to the camera through the hot shoe, it is electrically connected directly to the circuit of the flash device. Connected to. The connector (CN3) is provided on the bottom of the camera, and is electrically connected to the flash device via the flash controller (IV) described later, and the flash device is electrically connected directly to the camera via the connector (CN3). There is no. Further, the camera body (V) is provided with a connector (CN1), and this connector (CN1) is provided at a mounting position of an interchangeable lens such as a seat plate of a lens mount, and the interchangeable lens (VI) is provided. When it is attached to the camera, it is bonded to the connector (CN2) of the interchangeable lens (VI) and various data from the lens circuit (LEC) is taken in by the camera body (V).

(IV) is a flash controller that controls the flash device connected to it, and is electrically connected to the connector (CN3) at the bottom of the camera body via the connector (CN4). The flash controller (IV) is further provided with connectors (CN5) and (CN7), and the connector (CN5)
Has four electrical terminals and the connector (CN7) has two electrical terminals. The flash device connected to the connector (CN5) exchanges signals with the flash controller (IV) to exchange data and control the amount of light emission, and becomes the flash device connected to the connector (CN7). Only transmits the light emission start signal from the flash controller (IV).

(I) is a two-flash type flash device. In the example of FIG. 1, the flash controller (IV) is connected to the connector (CN5),
It is connected via (CN6). (II) is a one-flash type flash device, and is electrically connected via a connector (CN9) provided on the hot shoe of the camera body (V) and a connector (CN10). (III) is a single-flash type flash device having the same configuration as the flash device (II). In this example, the flash controller (IV) is connected to the connector (CN).
It is electrically connected via 7) and (CN8).

FIG. 1 shows an example of how to connect the camera body (V) to the flash controller (IV) and the flash devices (I), (II) and (III). To the camera body (V) where the connection positions of (II) are switched to each other, the flash device (III) is not attached, or either the flash device (I) or (II) is attached only to the hot shoe position. Install the flash controller (IV) and install either the flash device (I) or (II) only at the connector (CN5) position, or the flash device (I) or (II) at the hot shoe position. It is also possible to attach the flash unit to the flash controller (IV) attached to the camera body (V) without attaching the flash unit. Furthermore, a flash controller (IV) is attached, and the flash unit (I) or (I
I) may be attached, or the flash controller (IV) may be attached only to the camera body (V), and the camera can be operated without attaching the flash device anywhere. Note that when only the flash controller (IV) is attached to the camera body (V), the flash device is not used, and stationary light photography is performed. In addition, a general-purpose flash device or a non-dedicated flash device that does not have the functions necessary for the system of the present invention is mounted at the position of the hot shoe of the camera body (V) and the connector (CN5) of the flash controller (IV). In this case, the flash photography according to the present invention is not performed, and the attached general-purpose or non-dedicated flash device only emits light. Further, the flash photography according to the present invention is performed whether the flash device mounted at the position of the connector (CN7) of the flash controller (IV) is a dedicated device or a general-purpose device or a non-dedicated device.

The inside of the camera body (V) will be described below.

(BA1) is a power supply battery, and (MS1) is a main switch.
(S1) is an immediate light switch that is closed by the first step of pressing the release button (not shown), and (S2) is a release switch that is closed by the second step of pressing the release button (not shown). , The closing signal of the photometric switch (S1) is the interrupt terminal (i) of the microcomputer (hereinafter referred to as the microcomputer) (MC1).
t) and input terminal (i1), and release switch (S
The closing signal of 2) is input to the input terminal (i2) of the same microcomputer (MC1). (S4) is released when the exposure control operation is completed,
Exposure control mechanism (not shown) such as shutter mechanism and aperture mechanism
This is a reset switch that is closed when the charging of is completed, and the signal according to the opening and closing of this reset switch (S4) is input to the input terminal (i3) of the microcomputer (MC1). (D
O) is a circuit that outputs data corresponding to set values such as exposure control mode film sensitivity, exposure time, and aperture value, that is, measured data, and signals of the set data to the input terminal (IP1) of the microcomputer (MC1). You are typing. Note that the film sensitivity value is set by a film container (not shown) instead of manual setting.
It is also possible to automatically read the film speed data marked above and use it as the setting data. (LM)
Is a photometric circuit, and the output of the photometric circuit (LM) is input to the analog input terminal (ANI) for A / D conversion of the microcomputer (MC1), and the reference voltage source ( The output of the figure is input to the reference voltage input terminal (VRI) for AD conversion of the microcomputer (MC1).

(AF) is an automatic focus adjustment circuit that detects the focus adjustment state of the taking lens and drives the taking lens to the in-focus position.
This automatic focus adjustment circuit (AF) operates according to commands transmitted from the microcomputer (MC1) through the data bus (DB), and the direction and amount of deviation of the subject image formed by the taking lens from the planned focal plane. To detect. Then, based on the data of the detected shift amount and the data from the interchangeable lens (VI), the moving amount of the taking lens (actually, the moving amount of the focusing lens system of the taking lens that moves for focus adjustment). ) Is calculated, the lens is moved by the amount of movement, and the focus adjustment state of the photographing lens is displayed. (RL) is a release circuit for starting the operation of the exposure control mechanism, and operates by a "High" signal from the terminal (O2) of the microcomputer (MC1). (DP) is a display circuit, which displays an exposure control value (planned aperture value to be controlled, exposure time value, etc.), exposure control mode, film sensitivity, flash unit status, and the like. This display circuit (DP) is a microcomputer (MC1)
Display based on the data from the output terminal (OP2) of. (ECC) is a circuit for exposure control, and the output terminal (OP
The shutter and diaphragm aperture are controlled based on the data of the exposure time and the number of diaphragm steps from 1). Transistor (BT
1) is a power supply transistor, and when the terminal (O1) of the microcomputer (MC1) becomes "High", the transistor (BT1) becomes conductive through the inverter (IN1) and the power supply line (+ V). Is supplied. This line (+
From (V), circuits (LM), (AF), (ECC), (RL), (F
Power is supplied to the ST) and lens circuit (LEC).

The switch (Sx) is a synchro switch that is closed when traveling of the shutter front curtain is completed, and the signal of the synchro switch (Sx) is transmitted via the line (l1) to the flash device (II), flash controller (IV), It is transmitted to the flash device (I). (FST) is a light emission amount control circuit for controlling the light emission amount of the flash device, a concrete example of which is shown in FIG. (IOC) is an input / output controller that controls the exchange of signals between the camera body (V) and the interchangeable lens (VI), flash unit (II), and flash controller (IV), a specific example of which is shown in FIG. It is shown in.

The terminal (CKO) of the microcomputer (MC1) outputs a clock pulse from the inside of the microcomputer, and this pulse (φ1) is an automatic focus adjustment circuit (AF), setting data output circuit (DO), exposure control circuit (ECC). ), Display circuit (DP), release circuit (R
L) are supplied as their reference clocks. The terminal (ANO) of the microcomputer (MC1) outputs a signal obtained by performing DA conversion on the film sensitivity for controlling the light emission amount of the flash device. The terminals (SCK), (SOU), (SIN) are terminals for serial input / output of data. When there is an instruction for serial input / output, eight clock pulses are output from the terminal (SCK), Data is output bit by bit from the input / output register in the microcomputer (MC1) to the terminal (SOU) in synchronization with the rising edge of this clock pulse, and in synchronization with the falling edge of the clock pulse from the terminal (SCK). Data to SIN) are sequentially taken into the I / O register. (O3) is "High" when exchanging data with the interchangeable lens (VI)
(O4) is a terminal that becomes "High" when data is exchanged with either or both of the flash device and flash controller, and (O5) is a signal that indicates the operating status of the camera to the flash device and flash controller. Is a terminal for transmitting data from the flash device and / or flash controller to the camera body during a predetermined period T1 (for example 90 μsec).
During a predetermined period T2 (for example, when outputting a “High” pulse from the camera body to the flash device and / or the flash controller).
A “High” pulse is output for 150 μsec), and a “High” pulse is output for a predetermined period T3 (for example, 210 μsec) when the camera body starts the exposure control operation. The terminal (O6) is a terminal that becomes “High” when either or both of data is transferred from the camera body to the flash device and the flash controller.

(LEC) is a circuit provided in the interchangeable lens (VI) and is fed from the power line (+ V) of the camera body.
Then, when the terminal (O3) of the microcomputer (MC1) becomes "High", the line (L1) becomes "High" and the circuit inside the lens is in the operating state. Then, based on the clock pulse sent from the line (L2), the data fixedly stored in the in-lens circuit (LEC) is sequentially output in series from the line (L3). As the fixedly stored data, the maximum aperture value,
Maximum aperture value, focal length, shooting distance, various data for automatic focus adjustment, for checking (whether or not an interchangeable lens compatible with the system of the present embodiment is attached, There is data such as (data for confirming whether or not the device is mounted).

(L1) is a signal line to which the closing signal of the synchro switch (Sx) is transmitted as described above. In (l2), when data is exchanged between the camera body and either or both of the flash controller and flash unit, serial data from either or both of the flash unit and flash controller and serial data from the camera unit are transmitted. Function as a bidirectional data bus. Then, when the flash device emits light, a "Low" signal is output from the flash device for a certain period of time (a period longer than the time required for all flashes of the flash device, for example, 2.5 msec).
A "High" signal is output for a certain period of time (for example, 1 msec), and then a "Low" signal is output for a certain period of time (for example, 5.5 msec) required for all the two lights to sequentially emit light. When the flash device is in the charging completed state except when data is transmitted / received and light is emitted, it is set to “High”, and when it is not in the charging completed state, it is set to “L”.
The signal of "ow" is output. In addition, "Low", "Hig
The h "and" Low "signals are signals for controlling the amount of light emission, as will be described later. The line (l3) is a terminal (SCK for exchanging data between the camera body and the flash unit / flash controller). ) Is output from the camera body, and a signal from the terminal (O5) indicating the operating status of the camera body is also output from line (l3). A light emission stop signal is output from the control circuit (FST).

Next, the inside of the flash device (I) will be described. (BA3)
Is a power supply battery, and (MS3) is a main switch. (FLC
Reference numeral 1) is a control circuit, which has functions such as data transmission / reception, display operation, and light emission control. The specific internal configuration is shown in FIG. 9, FIG. 10, FIG. 11, FIG. Fig. 13, Fig. 14
It will be described later with reference to the drawings. (FDP1) is the display of the emission modes (parent-child emission, first or second emission in sequential emission, simultaneous emission, single emission) described later, indication of bounce status, aperture based on data sent from the camera body. Value, film sensitivity, display of focal length, display of set irradiation angle when irradiation angle of flash device is variable, and based on aperture value and film sensitivity data and light emission amount data sent from the camera body, In the automatic light control mode, the interlocking range (the range of the automatic light control) is set, and in the mode in which a manually set amount of light is emitted (in the following manual setting mode), the appropriate exposure range is set. indicate. (CHC1) is a transistor (BT2) and a booster circuit (D) in response to signals from the charge completion detection circuits (CHD1) and (CHD2).
It is a boost control circuit that controls the operation of D1). The booster circuit (DD1) operates when the transistor (BT2) is energized to boost the voltage of the power supply (BA3) to the required voltage (for example, 300V),
This output is fed through a diode (D1) to a capacitor (C
In 1), the capacitor (C2) is charged through the diode (D2). Then, the charge completion detection circuit (CHD1), (CH
D2) outputs a "High" signal (hereinafter, this signal is called a completion signal) when the charging voltage of the capacitors (C1) and (C2) is charged to a voltage capable of compensating the maximum light emission amount of the flash device. Step-up control circuit (CHC1) is connected to both detection circuits (CH
When the fill signal is output from D1) and (CHD2), the transistor (BT2) is deactivated and the operation of the booster circuit (DD1) is stopped. If the fill signal is not output from at least one of the detection circuits, the transistor (BT2) is made conductive and the booster circuit (DD1) is operated.

(FLO1) and (FLO2) are light emitting units, and signals (ST1), (SP1), (ST2), and (ST1) from the control circuit (FLC1) are used.
Light emission is controlled by (SP2). The light emitting part (FLO2) has a variable irradiation direction. When only the flash device (I) is directly connected to the camera body (V) as a flash device or through the flash controller (IV), if the light emitting unit (FLO2) faces front ( (Hereinafter referred to as front light condition), only this light emitting unit (FLO2) emits light, and if the light emitting unit (FLO2) faces in a direction other than the front (hereinafter referred to as bounce state), the light emitting unit (FLO2) first
2) emits only about 2/3 of the proper exposure, and then the light emission part (FLO1)
Emits only about 1/3 of the proper exposure (hereinafter, such a light emission mode is referred to as a parent-child light emission mode). On the other hand, as shown in FIG. 1, when two or more flash devices including the flash device (I) are electrically connected to the camera body (V), the light emitting unit (FLO2) is in front. In the light state or bounce state, only the light emitting part (FLO2) emits light, and (FLO1) does not emit light. Light emitting part (FLO1), (FL
O2) starts emitting light when the terminals (ST1) and (ST2) become "High". Also, since the capacity of the capacitor (C1) is much smaller than the capacity of the capacitor (C2), the maximum light emission amount of the light emitting unit (FLO1) is
It is much smaller than the maximum light emission of 2).
Therefore, the maximum light emission amount of the light emitting unit (FLO2) is, for example, 40 as a guide number, whereas the maximum light emission amount of (FLO1) is 8, for example, as a guide number. Further, the light emitting part (FLO2) has a variable irradiation angle, whereas the light emitting part (FLO1) has a fixed irradiation angle. Terminals (SP1), (SP2) are terminals for stopping light emission, and terminals (SP
When the "High" signal is output from 1), the light emission unit (FLO1) stops emitting light, and when the "High" signal is output from the terminal (SP2), the light emission unit (FLO2) stops emitting light. .

Next, the flash device (II) will be described. (BA
5) is the power battery, (MS5) is the main switch. (FL
C3) is the control circuit (FLC) of the flash unit (I)
This is a control circuit that performs the same function as 1), sending display data to the display unit (FDP3), and for the light emitting unit (FLO4), a light emission start signal to the terminal (ST4) and light emission from the terminal (SP4). Output a stop signal. This control circuit (FLC
3) will be described later based on FIG. 15, FIG. 16 and FIG. The step-up control circuit (CHC3) responds to the charge completion signal from the detection circuit (CHD4) by the transistor (BT
4) Control the operation and non-operation of the boost circuit (DD3). The light emitting unit (FLO4) is switched between the front light state and the bounce state, and the irradiation angle is also variable. Flash device (II
I) has the same structure as the flash device (II).

Next, the flash controller (IV) will be described. (BA2) is a power supply battery, and (MS2) is a main switch. (CNC) is a processing circuit that reads the data from the flash units (I) and (II) based on the clock pulse from the camera body (V) to determine the mounting state of the flash unit and the internal state of the flash unit. The light emitting mode is determined, the light emitting mode is determined, and the light emitting mode signal is sent to the flash device based on the clock pulse from the camera. Then, based on the clock pulse from the camera body, a signal indicating the light emission mode and the state of the flash device is sent to the camera. Furthermore, it is decided whether to make the flash unit (III) emit light according to the determination result of the light emission mode,
To emit light (sequential light emission mode), a light emission start signal is output to the terminal (l21) after light emission of the two flash devices. A concrete example of this processing circuit (CNC) is shown in FIG.

Next, the light emission modes of various combinations will be described. If only the flash unit (I) is connected to the camera body directly via the hot shoe or via the flash controller (IV) and the light emitting unit (FLO2) is in the front light state, the light emitting unit (FLO2) Only the single light emission mode is activated, and the interlocking range is displayed based on the maximum light emission amount of the light emission unit (FLO2). If the light emitting unit (FLO2) is in the bounce state, the light emitting unit (FLO2) emits only 2/3 of the proper exposure, and then the light emitting unit (FLO1) emits only 1/3 of the proper exposure in the parent-child emission mode. The interlocking range is displayed based on the maximum light emission amount of the light emitting unit (FLO1).

When only the flash unit (II) is electrically connected to the camera body (V) via a hot shoe or a flash controller, the light emitting unit (FLO4) emits light until proper exposure regardless of the front light condition or the bounce condition. FLO4) is the one-flash mode in which the light is emitted. In this case, the interlocking range is not displayed when the light emitting unit (FLO4) is in the bounce state, and the interlocking range based on the maximum light emission amount of the light emitting unit (FLO4) is displayed in the front light state.

Next, a case where the flash device is attached to each of the hot shoe and the flash controller will be described. At this time, if one or both flash devices are of the type (I), the light emitting unit (FLO1) does not emit light even if the light emitting unit (FLO2) is in the bounce state or in the front light state (FLO2). Only light is emitted. When the flash controller (IV) selects the simultaneous mode, the two flash devices emit light at the same time, and at the same time when the combined light emission amount reaches the proper exposure, the light emission is stopped. In this case, the interlocking range is displayed based on the maximum light emission amount of each light emitting unit, and is not displayed if the light emitting unit is in the bounce state. When the flash controller (IV) selects the sequential flash mode, the flash unit mounted on the flash controller (IV) first emits only 2/3 of the proper exposure, and then the camera body (V) hot The flash unit attached to the shoe emits only 1/3 of the proper exposure. The interlocking range at this time is not displayed by the flash device that emits light first, and the interlocking range based on the maximum light emission amount of this flash device is displayed by the flash device that emits light later.

Further, as shown in the figure, when the flash device is attached to each of the hot shoe and the flash controller, and further, the flash device is attached to the connector (CN7) of the flash controller, the following light emission mode is set. When the flash controller (IV) selects the simultaneous mode, the light emission start signal is not output from the terminal (l21), and the flash device (III) does not emit light. When the flash controller (IV) sequential light emission mode is selected, after the two flash devices (II) and (I) sequentially emit light, a light emission start signal is output from the terminal (l21), and the flash device (III) Emits light. Flash device (II
Since I) is only connected to the ground line (l4) and the light emission start signal is transmitted, the signal from the light emission amount control circuit (FST) on the camera side is not transmitted, and the light emission amount set manually is set. Or the entire light emission is performed in the automatic light control mode. This flash unit (II
Since I) only inputs the light emission start signal, it does not need to be a dedicated flash device and may be a general-purpose flash device. Also, this third flash device (III)
For example, if you set it so that only the background is illuminated,
Even if two lights are continuously emitted to illuminate the main subject, it is possible to remove an unnatural shadow caused by the main subject in the background. The third flash unit (III) emits light after the proper exposure is achieved by the light emission of the first and second flash units (I) and (II), and the camera controls the amount of light emission. Therefore, it is not desirable to illuminate the main subject, and light emission should be performed so as to cover the unnaturalness of the lighting.

Next, FIG. 2, FIG. 3, FIG. 4, FIG. 5, FIG. 6, and FIG.
The operation of the camera body (V) and the operation of the entire system shown in FIG. 1 will be described with reference to FIGS. FIG. 2 is a flow chart for explaining the operation of the microcomputer (MC1) of FIG. The flowchart will be mainly described below. When the main switch (MS1) of the camera body (V) is closed, power supply to the microcomputer (MC1) starts, and the microcomputer (MC1) starts the operation at the start of power supply. First, in steps # 1, the output terminals (O1) to (O6) are set to “Low”, and then data for turning off the display on the display unit (DP) is output.
Then, in the step of # 3, the data for operating the automatic focus adjustment circuit (AF) is not sent from the data bus (DB), and in the step of # 4, the interrupt signal to the interrupt terminal (it) is accepted. The microcomputer (MC1) stops operating.

When the photometry switch (S1) is closed, a "Low" interrupt signal is input to the interrupt terminal (it), the microcomputer (MC1) starts operating, and the operation from step # 10 is performed. In step # 10, the terminal (O1) is set to “High” and the inverter (IN
The transistor (BT1) is turned on via 1), power is supplied from the power supply line (+ V), and power is supplied to circuits other than the microcomputer (MC1) and lens circuit (LEC). In step # 11, the terminal (O3) is set to "High" to start reading data from the lens circuit (LEC).
First, the register BR in the microcomputer (MC1) (also in the following, the register indicated by the reference numeral without parentheses,
Flags and the like are set by a program in the microcomputer. ) Is set to "O", and the operation according to the serial input / output instruction is performed in step # 13. As a result, the data from the lens (LEC) is read into the serial input / output register IOR. The content of the register IOR is taken into the specified register, "1" is added to the content of the register BR, and it is determined whether or not the content of the register BR becomes "N". If it is not "N", the process returns to step ## 13 to read the next lens data, and if it is "N", the process proceeds to step # 17.

Here, reading of lens data will be described with reference to FIGS. 1 and 7. FIG. 7 shows a concrete example of the input control circuit (IOC) shown in FIG. And circuit (AN1), (AN3) when the terminal (O3) of the microcomputer (MC1) becomes "High"
Becomes an active state, and the "High" signal is also given to the lens circuit (LEC) via the line (L1) to be in an operable state. When eight clock pulses are output from the terminal (SCK) of the microcomputer (MC1), these clock pulses are sent to the lens circuit (LEC) via the AND circuit (AN3) and line (L2). And the lens circuit (LE
From C), the first data is sequentially output to the line (L3) in synchronization with the rising edge of this clock pulse. This data is input to the terminal (SIN) of the microcomputer (MC1) via the AND circuit (AN1) and the OR circuit (OR1). This data is sequentially read into the register IOR in synchronization with the falling edge of the clock pulse output from the terminal (SCK).

The lens circuit (LEC) is provided with a ROM that fixedly stores a plurality of data in a predetermined order, an address designating unit that sequentially designates the address of this ROM, and a data output unit that sequentially outputs the data from the ROM in series. There is. Then, the addressing means sequentially updates the address data every time eight clock pulses are input from the line (L2), and outputs the data in the order of the determined data type. Then, the microcomputer (MC1) sets the data in the registers determined in the order of the input data, so that the open aperture value data is stored in a certain register and the maximum aperture value data is stored in a certain register. The data of the specified type is set in each register. That is, the contents of the fixed register in the microcomputer (MC1) are data of the fixed type of the attached interchangeable lens. Among the lens data, in the case of data that changes according to the change of the focal length of the zoom lens, or data that changes according to the shooting distance (lens extension amount), the data according to the set position of the zoom ring and the distance ring is used. An output code plate may be provided, and an address may be designated by a combination of this code plate and data obtained by counting clock pulses from the camera body.

In step # 17, the terminal (O3) is set to "Low" to stop the data acquisition from the lens circuit (LEC), and then it is determined whether or not the flag JF1 is "1". This flag JF1 is "1" when the calculation of the exposure control data is completed, and is "0" when the calculation is not completed. And JF
If 1 is “0”, the calculation has not been completed, and the process proceeds to step # 25. On the other hand, if the calculation is completed, then the release switch (S2) is closed and the input terminal (i2) goes to "Lo.
Determine whether it is w ". And terminal (i2)
If is not "Low", move to step # 25. On the other hand, if the terminal (i2) is "Low", the release switch (S2) is closed. Then, in step # 20, the reset switch (S4) is closed and the input terminal (i3). Determine whether is "Low". At this time, if charging of the exposure control mechanism is not completed and the switch (S4) is opened and the terminal (i3) is "High", the process proceeds to step # 25. On the other hand, the charge of the exposure control mechanism is completed, the switch (S4) is closed, and the terminal (i3) is set to “Lo”.
If it is "w", the exposure control operation from step # 80 is performed.

In step # 25, it is determined whether the check data is input from the data captured from the lens.
This check data is the data that is common to all interchangeable lenses at the specified ROM address (for example, "1010101
0 ") is stored and indicates this data. If this data is not input, the lens is not attached, and if it is input, it is attached. If so, of the data captured from the lens in step # 26, the data related to auto focus adjustment is sent to the auto focus adjustment circuit (AF) via the data bus (DB), and the operation of this circuit (AF) Let me do # 27
Go to step. On the other hand, if there is no check data, the lens is not attached and the automatic focus adjustment circuit (A
F) remains inoperative and moves to step # 27.

In the step of # 27, the terminal (O4) is set to "High" to enable the data exchange with the flash device and the flash controller. Then, the terminal (O5) is connected for a predetermined period T1.
Set to “High” for (90μsec). This signal is line (l
It is transmitted to the flash unit and flash controller via 3) and (l13). Then, the flash device and the flash controller determine that the mode is a mode for transmitting data from the flash device and the flash controller to the camera body (hereinafter referred to as FC mode).
Then, by the operation according to the serial input / output command, first,
When the clock pulses are transmitted to the flash device via the lines (l3) and (l13), the flash device synchronizes with the rising edge of the clock pulse to generate the line (l3).
6-bit data is output via 2) and (l12), and this data is taken in by the flash controller in synchronization with the falling edge of the clock pulse. Then, the flash controller determines the light emission mode according to the read data and the light emission mode (sequential light emission mode, simultaneous light emission mode) set by the flash controller at that time, and the data corresponding to this result is converted into 2 bits. In line (l2), (l1
2) output via. At this time, the microcomputer (MC1) uses the input / output register IOR to capture the data output to the line (l2) at this time in synchronization with the falling edge of the clock pulse, but the microcomputer (MC1) does not use this signal. Next, in step # 30, eight clock pulses are output to the lines (l3) and (l13) by the serial input / output command again. At this time, if the flash device is installed via the flash controller and the hot shoe is also installed, the flash device does not output data to the lines (l2) and (l12), and the line (l2) , (L12) are set to an open state so as not to affect the signal transmission, and the data determined by the data read by the flash controller from the two flash devices before that and the set emission mode are used as the clock pulse. Output from the flash controller in synchronization with the rising edge. If the flash device is attached via the flash controller and the hot shoe is not attached, the flash controller outputs the data read from the flash device to the line (l2). At this time, the flash device similarly outputs data to the line (12), but this data is blocked by the flash controller. When the flash unit is attached only to the hot shoe,
After the data is output in synchronization with the clock pulse in step # 29, the same data is output again in synchronization with the clock pulse in step # 30. Even if the flash controller is installed in the camera body, if the flash device is not installed at the connector (CN5) position of this flash controller, the flash controller opens the line (l2) to affect the signal transmission. Do not give.

Next, the data transmitted and received based on 16 clock pulses will be described. The first data of the clock pulse is b0 bit, the second data is b1 bit, hereafter b
2, b3, ..., b14, b15 bits. First, Table 1 shows the data contents of each bit and the states of the camera body, the flash device, and the flash controller.

For the 6 bits b0 to b5, the flash device outputs the data shown in Table 1 based on the clock pulse from the camera, and the controller sequentially reads this data. The bit of b0 outputs a "High" signal if the power switch of the flash device is closed. The bit of b1 is set to "Low" if the upper flash unit (the one with the maximum maximum flash amount) is bounced by the above-mentioned parent-child strobe and is in the parent-child flash mode, and is set to "High" otherwise. Become. The bit of b2 outputs a signal of "High" when the main capacitor of the flash device is in a full state, and outputs a signal of "Low" when it is not in a full state. The bit of b3 outputs a "Low" signal when dimming display is performed by the flash device, and outputs a "High" signal when dimming display is not performed. b4 bits are reserved,
In consideration of future system development, for example, when a light emitting unit for auxiliary light for automatic focus adjustment is provided, it may be possible to output a "High" signal when the light emitting unit is ready to emit light. To be The bit of b5 is data for identifying the system of the present embodiment, and a flash device compatible with the system of the present embodiment always outputs a "Low" signal. This is because the flash device currently on the market always displays “Hig
There is a device that outputs the signal of "h". When such a flash device is attached, the flash controller and the camera body all read the signal of "High", and the flash device of this embodiment and this embodiment This signal is used to distinguish it from the flash device of the system.

For bits b6 and b7, the flash device line (l2 ), (L12). The mounting signal read by the flash controller (IV) and the signal of the actual light emission mode determined from the set light emission mode are displayed on lines (l2), (l1
It is output to 2). Table 2 shows signals in this light emission mode.

When the flash device reads the light emission mode signal shown in Table 2, the flash device performs the operation according to the light emission mode signal thereafter.

The flash device outputs data up to bits b0 to b5 and reads data at bits b6 and b7. By the way, a cable may be used to connect the flash controller connector (CN5) to the flash unit and the camera's hot shoe position connector (CN9) to the flash unit. The signal line (l2) in this cable, There is a parasitic capacitance and impedance component between (l3) and ground. Therefore, when the "High" signal is output at the timing of bit (b5) and the flash controller is not installed, there is no discharge circuit, so the charge remains stored in the parasitic capacitance and bit b6, b7
As a result, the flash device reads the "High" signal. In other words, if the flash unit is a single light source that is only connected to the hot shoe of the camera body via a cable, and outputs a "High" signal at bit b5, this signal remains stored in the parasitic capacitance. So bit b
At 6, b7, for example, a signal indicating the simultaneous light emission mode or the sequential light emission mode is read by the flash device, and a malfunction occurs. Therefore, in this system, the bit b5 is used to output the discrimination signal "Low" so as to prevent the parasitic capacitance from being discharged due to a short circuit and malfunction.

For bits b8 to b15, if the flash device is only connected to the hot shoe of the camera body, the flash device outputs the data shown in Table 1 and the camera body reads it. If the flash unit is connected to the camera body via the flash controller sends to the camera body through the intact flash controller signals b ₈ ~b ₁₅ from the flash device, that this signal is the camera body reads However, in this case, there are the following problems. That is, if a cable is provided between the flash controller and the flash device, the signal is delayed by this cable and the circuitry within the flash controller. Therefore, first, the clock pulse sent from the camera body to the flash device is delayed, and there is a time difference between when the clock pulse rises in the camera body and when it rises in the flash device. Then, the flash device detects that the clock has risen and outputs the data. This data is sent to the camera body via the cable and flash controller, but is delayed as in the case of the clock. Then, it is read at the falling edge of the clock on the camera body. But,
If the total delay time of the clock delay time and the data delay time is longer than the time from the rise to the fall of the clock in the camera body, the camera body will read erroneous data. Therefore, in this system, the data from the flash device is once read by the flash controller, and then the data is sent from the flash controller to the camera body.

If the flash controller is connected to the camera body and the flash device is not attached to the connector (CN5) of this controller, the flash controller is b8 to b15.
During the bit of, the signal is not output to the line (l2), and the high impedance state is set so that the data sent from the flash device connected to the hot shoe to the camera body is not adversely affected. Also, if a flash device is attached to the hot shoe and flash controller, the data "11", "10", which indicates that multiple flashes are emitted, is indicated by bits b6 and b7 from the flash controller.
Any one of "01" is input to the flash device, and the flash device does not output data to the lines (l2) and (l12) during the bits b8 to b15, and is in a high impedance state. Then, the data read by the flash controller from both flash devices and the data based on the set flash mode are set to b8.
It outputs with the bit of b15, and the camera body (V) reads this data.

Next, the data of bits b8 to b15 will be described. The bit of b8 is a mounting signal, and when the flash device outputs, a "High" signal is output when the power switch is closed. If the flash controller outputs, the "High" signal is output if at least one of the flash devices inputs the "High" signal with the bit of b0. The bit of b9 is a signal for distinguishing the system of this embodiment, and if the flash device outputs, a signal of "Low" is output, and the flash controller outputs "Low" by the bit of b5 from at least one of the flash devices. If the signal of "" is read, the signal of "Low" is output. b10
The bit of is a signal indicating whether it is in the sequential light emission mode,
When the flash device outputs data, it outputs a "Low" signal if the flash device is in the parent-child emission mode, and otherwise outputs a "High" signal. On the other hand, if the flash controller outputs data, it is "Low" in the sequential emission mode and "High" in other emission modes.
The signal of is output. The bit of b11 outputs a completion signal. When the flash unit outputs, a "High" signal is output if it is in the full state. When the flash controller outputs, a mounting signal is input from two flash devices, and bit b2 is input from the two flash devices.
If the "High" signal indicating the full state is input in both, the bit b11 outputs the "High" signal. Therefore, when the "High" signal is input only from one of the flash devices, the "Low" signal is output. The bit of b12 is a photo taken by flash device (flash shooting)
Is a so-called FDC signal that indicates that dimming has been performed so that proper exposure can be obtained. When the flash device outputs, a "Low" FDC signal is displayed while the flash device is performing dimming completion display. Is output. When the flash controller outputs, if at least one of the flash devices inputs the "Low" FDC signal in bit b3, it outputs the "Low" FDC signal. Bits b13, b14, b15 are spare data, even when the flash device outputs,
It also outputs a "Low" signal when the flash controller outputs. When the data transfer described above is completed, the flash unit and flash controller enter a mode (hereinafter called waiting mode) for waiting for a pulse to be input from lines (l3) and (l13). l2 is "High" when the flash is fully charged and "L" when it is not charged
ow ".

On the other hand, in the camera body, the data of bits b8 to b15 read from the flash device or flash controller to the register IOR in the step # 31 in FIG. 2 is set in a predetermined register, and the terminal (O4) is set to “Low”. To do. next,#
In step 33, various setting data (exposure control mode, set exposure time apex value Tv) to the input terminal (IP1)
s, apex value Avs of the set aperture value, apex value Sv of the film sensitivity on the film container or set, etc.) are fetched into registers corresponding to respective data. Next, in step # 34, the output Bv-Avo (Bv is the subject brightness, Avo is the apex value of the open aperture value) of the photometric circuit (LM) is A-D converted and this data is set in a predetermined register. And
In steps # 35 to # 37, as in steps # 18 to # 20, it is determined whether the exposure control operation is to be performed. If the exposure control operation is to be performed, go to the step # 80, and otherwise. Go to step # 38.

A concrete example of step # 38 is shown in the flowchart of FIG. First, when it is determined in step # 210 that the FDC signal is being input, the state of FDC display is set, the charging completion display is reset, and the process proceeds to step # 40. On the other hand, if the FDC signal is not input, the FDC display is reset and it is determined whether the fill signal is input. If the charge signal is input, the charge display is set, and if not, the charge display is reset and the process proceeds to step # 40.

In step # 40, check data “10” from the interchangeable lens.
It is determined whether or not "1010 10" is input. If the check data is input, the calculation of steps # 41 and # 42 is performed, and if it is not input, the calculation of steps # 43 and # 44 is performed. The stationary light calculation I of 41 is calculated according to the flowchart shown in Fig. 4. First, # 101
In the step of, (Bv-Avo) + Avo + Sv = Ev (1) is calculated. However, Ev is the exposure value Apex value, so-called Ex
It is a posure value. Next, the exposure control mode is determined in step # 102, and the P mode (program exposure mode)
If so, the process proceeds to steps # 103 and 104, and the calculation of p · Ev = Av (2) Ev-Av = TV (3) (0 <p <1) is performed. Where Av is the aperture value to be controlled, Tv is the apex value of the exposure time to be controlled, p is a program constant, and the distribution for dividing the exposure value Ev into the aperture value and the exposure time value. It is for determining the ratio, which determines the program diagram. The value of p can be determined at the time of design or manually set to a desired value. When it is determined in step # 105 that Av <Avo, Ava = Avo is set in step # 106, and # 1
At step 07, Ev-Ava = Tv (5) is calculated. And if it is TvoTv, Tv of equation (5) is Tv
Do not warn as a. On the other hand, if Tvo> Tv, Tvo is set as Tva and the underexposure warning is performed. Here, Tvo corresponds to the maximum exposure time that can be controlled by the camera body. If Av calculated by equation (2) is AvAvo, then A
Determine if v ≤ Av _M. If Av> Av _M , the process proceeds to step # 114, Ava = Av _M is set, and in # 115, the equation (5) is calculated. If TvTv _M , Tv calculated by the equation (5) is set as Tva, and a warning is issued. on the other hand,
If Tv> Tv _{M in} step # 116, Tv _M is set as Tva and the overexposure warning is performed. Here, Tv _M corresponds to the shortest exposure time that can be realized by the camera body.

If it is determined in step # 113 that AvAv _M , warning is not given and Av calculated by equation (2) is the aperture value Ava for stationary light imaging, Tv of equation (3) is stationary light imaging. Exposure time Tva, and in step # 163, calculate Ava-Avo = dAva (4), and use the calculated dAva as the number of apertures for constant-light imaging, and set the data of Ava, dAva, and Tva in prescribed registers. Set to.

If it is determined in step # 102 that the mode is not the P mode, then it is determined in step # 115 whether the mode is the S mode.
When the exposure control mode is S mode (exposure time priority / aperture automatic control mode), set the exposure time Tvs in step # 126.
Ev−Tva = Av (6) with Tva as Tva. Then, in the step of # 128, if Av <Avo, Avo is set as Ava and the under-warning is performed, while if Av> Av _{M in} the step of # 131, Av _M is set as Ava and the over-warning is performed. Also, Av <Av
If neither o nor Av> Av _M , Av calculated by the equation (6) in # 134 is set as Ava, and the warning is not issued, and the process proceeds to step # 163.

If it is determined in step # 125 that the mode is not the S mode, it is determined in step # 140 that the mode is A mode. When the exposure control mode is A mode (aperture priority exposure time automatic control mode), the set aperture value Avs is set in step # 141.
Is calculated as the aperture value Ava for stationary light photography, and the calculation of equation (5) is performed. Then the If step in Tvo> Tv of # 143 Tvo a state where underexposure warning is performed as Tva, a state in which overexposure warning is performed as Tva the Tv _M <Tv if Tv _M in step # 146. If neither Tvo> Tv or Tv _M <Tv, Tv calculated by the equation (5) is set as the exposure time Tva for stationary light imaging and no warning is given, and the process proceeds to step # 163. If it is not SP or A mode, it is M mode (manual setting exposure control mode). At this time, Avs and Tvs set at step 155 are set as Ava and Tva, respectively.
Further, the operation of Ev- (Tva + Ava) = dv is performed, and a constant value k
For (allowable exposure error of film), under warning when dv <-k, over warning when dv> k, -kdv
If k, it is determined that no warning is given and the process proceeds to step # 163. In the step of # 163, the constant light photographing aperture step number dAva = Ava-Avo is calculated from the constant light photographing aperture value Ava and the maximum aperture value Avo, and the process shifts to the step 42 of the flash light photographing calculation I.

A specific example of step # 42 is shown in the flowchart of FIG. 5, and will be described below based on this flowchart. First, in the P mode, when Avo <3 (corresponding to FNO.2.8), Avc1 = 3, when Avo3, Avc1 = Avo, and in step # 174, Avc2 = 6 + (Sv-5) ... The calculation of (7) is performed. Here, 6 corresponds to FNO.8 and 5 corresponds to ISO10.
Equivalent to 0. Then, if Avc2> Av _M , Av _M is set to Avc2, and if Avc2Av _M, Avc2 is left as the value obtained by the equation (7) and the process proceeds to step # 177.

Next, the calculation of Ev + 1-6 = Av (8) is performed. Then, Av calculated by the equation (8) is the result of determination of # 178 Av <A
When vc2, Avf = Avc2. And Avf + 6E
When v is set, Tvf = 6, and Avf + 6 <Ev. Data from the flash device sequentially emit light (parent-child emission mode).
If not, Tvf = 7. On the other hand, if the signals of the sequential light emission mode are input, Tvf = 6 is maintained even if Avf + 6 <Ev. And Av calculated by equation (8) is Avc1Av
If it is Avc2, this Av is set as the aperture value Avf for flash photography and the exposure time Tvf for flash photography is 6, and the process proceeds to step # 204.

If it is determined in step # 170 that the mode is not the P mode, it is determined in step # 187 whether or not the signal of the sequential light emission mode (parent-child light emission mode) is input from the flash device (flash controller), and the sequential light emission mode is determined. If so, the tuning limit exposure time Tvl is set to 6 (1/60 sec), and if it is not the sequential emission mode, Tvl is set to 7 (1/125 sec) and the process proceeds to step # 190.

When it is determined in step # 190 that the mode is the A mode, the set aperture value Avs is set to Avf and Tvl is set to Tvf, and the process proceeds to step # 204. If it is determined in step # 190 that the mode is not the A mode, the set exposure time Tvs is Tvs> Tvl
If so, Tvf = Tvl, and if TvsTvl, Tvf = Tvs. Then Step determines whether S mode # 197, performs calculation of if S mode Ev + 1-Tvf = AV ... (9), Av <Avo if the Avo Avf, Av> Av _M if Av
_{If M} is Avf and AvoAvAv _M, then Av calculated by equation (9) is Av
The process proceeds to step # 204 as f. If the mode determined in step # 196 is the M mode, Avs is set to Avf, and the process proceeds to step # 204 to set dAvf = Avf-Avo.

Specific examples of the steady light calculation II in step # 43 and the flash light calculation II in step # 44 when the lens is not attached are shown in the flowchart of FIG. The description will be given below based on the flowchart of FIG. First, in step # 220, Bv-Avn + Sv = Tv (10) is calculated. Where Bv−Avn is the photometric output,
Is not controlled by the system of this embodiment,
It corresponds to the aperture value of an interchangeable lens intermediate ring, a bellows, a pinhole photographic adapter, etc., which is either manually set by itself or has a specific aperture opening fixed in advance.

Next, in step # 221, it is determined whether the mode is M mode or another mode. Then, in the M mode, the set exposure time Tvs is set as the control exposure time Tva, and Tva-Tv (T in the equation (10) is used.
v) = dv is calculated. When dv <-k, an over-warning is given, when dv> k, an under-warning is given, and when -dvkdv, no warning is given, and the process proceeds to step # 238.

When it is determined in step # 221 that the M mode is not set, in this case, Tv calculated by the equation (10) is TvoTvTv _M
If Tv calculated by equation (10) is Tva, no warning is given, if Tv <Tvo, Tv is Tva, an under warning is given, and if Tv> Tv _M, Tv _M is Tva, and an over warning is given. It is in a state to be performed. Then, in step # 238, dAva = 0 is set, warning data is set as Ava so that a warning that the lens is not attached is issued, and the process proceeds to step # 240.

When it is determined that the P mode is selected in step # 240, if Tv calculated by equation (10) is Tv6 (1/60 sec), Tvf = 6, and when Tv> 6, sequentially If it is not the mode, Tvf = 7 (1/125 sec), if it is the sequential mode, Tvf = 6 and # 253.
Go to step.

If it is determined in step # 240 that the mode is not the P mode, it is determined in step # 245 whether the mode is the sequential mode. And in the sequential mode, the tuning limit exposure time Tvl = 6,
If it is not the sequential mode, Tvl = 7 is set and the process proceeds to step # 248. In step # 248, it is determined whether the mode is the A mode. If the mode is the A mode, Tvf = Tvl is set and the process proceeds to step # 253. On the other hand, if it is not in A mode, set exposure time Tv
Determine if s is TvsTvl and if TvsTvl, Tvs to Tv
If f, Tvs> Tvl, Tvl is set as Tvf and the process proceeds to step # 253. Then, in step # 253, dAvf is set to 0, and warning data is set as Avf so that a warning that the lens is not mounted is issued, and the process proceeds to step # 45. In the sequential flash mode, up to three flash units will fire, so the shortest exposure time is after the shutter is released after the time required for the X contacts (Sx) to close and the three lights to fire sequentially. If the curtain shows Tv = 6 (1/60 sec) and the flash mode is not sequential, the shortest exposure time is the shutter after the time required for one lamp to fire with the X contact (Sx) closed. Tv = 7 (1/125 sec) when the second curtain appears.

When the above arithmetic operation is completed, the process proceeds to step # 45, and it is determined whether or not the charging completion signal is input from the flash device. If the full charge signal is input, flash photography is performed. Therefore, a signal indicating the aperture value Avf for flash photography, the exposure time Tvf, and the state of the flash device (charge complete, dimming display) is displayed on the display unit (DP ) Sent to.
On the other hand, if the charging signal is not input, the constant light photographing is performed, so the aperture value Ava for constant light photographing, the exposure time Tva, and the warning data are sent to the display unit (DP). And # 48
In steps # 50 to # 50, it is determined whether to shift to the exposure control operation as in steps # 18 to # 20. If it shifts to the exposure control mode, shift to the step # 80. Go to step.

In step # 55, the terminal (O4) of the microcomputer (MC1),
Set (O6) to "High". As a result, the NAND circuit (NA1) and AND circuit (AN11) in FIG. 7 become active, and the data from the camera body is transferred to the lines (l2) and (l12).
The data is transmitted to the flash device via the. And, to the terminal (O5) for a predetermined period T2 (for example, 150μsec)
Outputs a "High" signal, and this signal is output from lines (l3), (l
It is determined that the mode is a mode in which data is transmitted from the camera to the flash device by being transmitted via 13) to the flash device and the flash controller (hereinafter referred to as CF mode). Then, the microcomputer (MC1) sets the aperture value Avf for flash photography in the serial input / output register IOR and outputs this data in series. Next, the film sensitivity Sv and the mode data are set in the register IOR and the data are output in series. Next, the focal length fv of the interchangeable lens is set and the data is output in series. Then, in step # 63, the terminal (O
4), (O6) is set to "Low" and the process proceeds to the next step # 64.

Next, the exchange of data between the flash unit and the camera body will be described with reference to FIG. First, in the FC mode, the terminal (O6) becomes "Low", the output of the NAND circuit (NA1) becomes "High", and the output of the AND circuit (AN11) becomes "Low".
Transistors (BT15) and (BT17) are non-conductive. Therefore, the terminal (l2) is open. When a clock pulse is output from the terminal (SCK),
This clock pulse is AND circuit (AN5), OR circuit (O
R3), and when the clock pulse is "High", the inverter (IN3) causes the transistor (BT1
When (1) is turned on, a "High" signal is output to line (l3), and the clock pulse goes to "Low", the inverter (IN
5) makes the transistor (BT13) conductive, and the line (l
A “Low” signal is output to 3). In this FC mode, serial data is input from the flash unit, but at this time the transistors (BT15) and (BT17) are non-conducting, so when the line (l2) becomes "High", the transistor (BT19) becomes Conductor is turned on and the output of the inverter (IN7) is "High".
When the line (l2) goes low, the transistor (BT1
9) becomes non-conductive, and the output of the inverter (IN7) is "Low".
become. The output of this inverter (IN7) is the OR circuit (OR
It is read into the microcomputer (MC1) from the serial input terminal (SIN) of the microcomputer (MC1) via 1).

In the CF mode, the terminal (O6) becomes "High" and the NAND circuit (NA1) and the AND circuit (AN11) are in the active state. Then, when the data from the serial output terminal (SOU) is output through the AND circuit (AN9) and the "High" signal is output, the output of the NAND circuit (NA1) becomes "Low", and the transistor ( BT15) conducts, line (l2)
Becomes “High”. On the other hand, when the output of the AND circuit (AN9) becomes "Low", the output of the AND circuit (AN11) becomes "High", the transistor (BT17) becomes conductive, and the line (l2) becomes "Low".

Returning again to the flowchart of FIG. 2, the microcomputer (MC1)
The operation of will be continuously described. Since the preparation for exposure control is completed in step # 64, the content of the discrimination flag JF1 is set to "1", and it is determined whether or not to shift to the exposure control operation as in steps # 19 and # 20. If the exposure control operation is to be performed, the process proceeds to step # 80, and if the exposure control operation is not to be performed, the process proceeds to step # 70. # 70
In the step of, the photometric switch (S1) is closed and it is determined whether the input terminal (i1) is "Low". If "Low", the operation returns to step # 11 and the above-mentioned operation is repeated.
If it is gh ", the automatic focus adjustment circuit (AF) is performed in step # 71.
Stop the operation, turn off the display on the display (DP), and
JF1 is set to “0”, the interrupt signal from the terminal (it) can be accepted, the terminal (O1) is set to “Low”, and the transistor (BT
The power supply from the power supply line (+ V) is stopped by making 1) non-conductive, and the microcomputer (MC1) stops operating.

When performing the exposure control operation, the operation from step # 80 is performed. Automatic focusing circuit (AF) in step # 80
Stop the operation of. Next, set the terminal (O4) to "High" and keep the terminal (O5) for a predetermined time T3 (for example, 210 μsec).
Output a "High" signal and set the terminal (O4) to "Low".
The flash unit and flash controller read this signal to determine that the exposure control operation is performed (hereinafter referred to as ES mode), and the closing signal of the X contact (Sx) of the camera body is output from the line (l1). Wait for input. Next, in step # 84, it is determined whether or not the fill signal is input from the flash device, and if it is input, the exposure control values Tvf and dAvf for flash photography are controlled via the output terminal (OP1). Send to the circuit (ECC), exposure control value for continuous light shooting if no fill signal is input
Tva and dAva are output control circuit (EC
Send to C). Then, at the time of flash photography, it is determined in step # 86 whether or not the signal of the sequential emission mode is input, and if it is the sequential emission mode, the film sensitivity Sv
The analog signal corresponding to is output from the terminal (ANO), and if it is not the sequential light emission mode, the analog signal corresponding to Sv-0.5 is output from the terminal (ANO). The meaning of the analog signal from this terminal (ANO) will be described later with reference to FIG.

In step # 90, the display (DP) is turned off,
Next, set the terminal (O2) to "High". As a result, the release circuit (RL) operates and the exposure control operation starts.
Then, the diaphragm aperture is controlled, the reflecting mirror is raised, and when the raising is completed, the shutter front curtain starts running. Then, when the traveling of the shutter front curtain is completed, the X contact (Sx) is closed, and in the case of flash photography, flash light emission is performed. The control of the flash emission amount will be described later with reference to FIG. When the exposure time determined as described above elapses after the front curtain starts traveling, the shutter rear curtain starts traveling, and when the rear shutter shutter has completed traveling, the reflecting mirror descends and the aperture stops. Is open. Since the switch (S4) is opened when the above exposure control operation is completed, the microcomputer (MC1) uses this switch (S4).
4) is released and the input terminal (i3) goes "High".
Wait in 92 steps. And the input terminal (i3) is "High"
In step # 93, the terminal (O2) is set to "Low", the photometric switch (S1) is closed, and the input terminal (i1) is set to "Low".
Determine whether or not. Then, if it is "Low", it moves to the step of # 11, and if it is "High", it moves to the step of # 95 and sets the flag JF1 to "0" to interrupt the terminal (it). The signal can be received, the terminal (O1) is set to "Low", the power supply from the power supply line (+ V) is stopped, and the microcomputer (MC1) stops operating.

Next, the light emission amount control operation of the flash device will be described based on a specific example of the light emission amount control circuit (FST) shown in FIG.
In FIG. 8, (PD) is a light receiving element arranged at a position for receiving the light reflected by the film surface after passing through the photographing lens and diaphragm of the camera, and the output current of this light receiving element (PD) is a diode ( It is logarithmically compressed by D11). The analog output terminal (ANO) outputs Sv in the sequential emission mode and Sv-0.5 signal in the sequential emission mode, so the operational amplifier (OA) outputs the flash emission during the flash emission. It has information of reflected light intensity from the subject, control aperture value and film sensitivity, and Qv + Sv
-Avf or Qv + (Sv-0.5) -Avf. Where Q
v is a value obtained by logarithmically compressing the reflected light intensity from the subject under flash illumination. The output of this operational amplifier (OA) is logarithmically expanded as its collector current by the transistor (BT29), and this collector current is integrated by the capacitor (C11). Accordingly, the integration voltage on the capacitor will ^{2 S v · ∫2 Q vdt /} 2 A vf or ^{2 Sv-0.5 · ∫2 Q vdt} / 2 A vf that it.

The terminal (O2) is a terminal that becomes "High" when the exposure control operation starts. When this terminal (O2) becomes "High", the AND circuit (AN13) becomes active and the output becomes "High". . Also, the "High" signal from the terminal (O2) is the delay circuit (D
After being delayed by L1), a T flip-flop (TF
1) and the reset terminal of the D flip-flop (DF1), and the reset state of these flip-flops (TF1) and (DF1) is released to enable the operation. Therefore, at this point, the Q outputs of both the flip-flops (TF1) and (DF1) are "Low" and the outputs are "High". Terminal (I
NT) is the output of the inverter (IN7) in FIG. 7, which is the signal from the flash unit through line (l2). And this line (l2) is "High" until the flash starts when the flash is full in ES mode,
When the X contact (Sx) is closed, it becomes “Low” for 2.5 msec.
Next, it becomes “High” for 1 msec, then becomes “Low” for 5.5 msec, and then becomes “High”. Therefore, the delay circuit (D
When the output of L1) becomes “High”, the AND circuit (AN1
The output of 5) is "Low", and the output of the inverter (IN9) is "Hig".
h ", the output of the NAND circuit (NA3) is" High ", the output of the NAND circuit (NA4) is" Low ", and the transistor (BT21) and transistor (BT27) are conducting. Therefore, the comparator (AC1) The non-inverting input terminal is at a level that is made up of a resistor (R2 / 3) and a constant current source (CI1), and these resistors (R2 / 3)
The resistance value and the constant current value are set so as to generate a potential of 70% of the proper exposure level.

Next, the light emission amount control operation will be described from the case where the sequential light emission mode is not set. When the flash emission starts, the AND circuit (AN1
The output of 3) becomes "Low", the output of the NAND circuit (NA4) becomes "High", the transistor (BT27) becomes non-conductive, and the collector current of the transistor (BT29) is integrated by the capacitor (C11). In this case, analog output terminal (AN
O) outputs a signal of Sv−0.5, so 2 ^S v ・ ∫ 2 ^Q vdt / 2 ^A vf ・ 2 ^0.5 ≈ 07 ・ 2 ^S v ・ ∫ 2 ^Q v ・ dt / 2 ^A vf ＝ R2 / 3 = 0.7K (11) (K; constant corresponding to proper exposure) When the output of the comparator (AC1) is inverted to "High", the one-shot circuit (OS1) outputs a "High" pulse. This pulse is output, and this pulse is output to the line (13) through the circuit of FIG. 7 to stop the flash emission. Equation (11) is Therefore, the flash emission will be emitted until the proper exposure is achieved. After that, the circuit of FIG. 8 performs the operation described later based on the signal from the terminal (INT), but since it is not in the sequential light emission mode, it does not affect the flash light emission.

In the sequential light emission mode, the operation of the first light emission is performed in the same manner as described above. However, at this time, since the Sv signal is being output from the analog output terminal (ANO), Therefore, the light emission amount ∫ 2 ^Q vdt is 70% of the proper exposure amount. When the terminal (INT) rises from "Low" to "High", the T flip-flop (TF1) inverts the output and the Q output becomes "Hig".
h ", the output becomes" Low ". On the other hand, the D flip-flop (DF1) takes in the output of the comparator (AC1) at this time, and if the light emission amount of the first lamp reaches 70% of the proper exposure, Q The output becomes “High” and the Q output becomes “Low.” If the light emission of the first light does not reach 70% of the proper exposure, the output of the comparator (AC1) remains “Low”, so the D flip-flop (DF1 ) Q output is “Low”, and the output remains “High.” When the light emission of the first lamp reaches 70% of the proper exposure, the output of the NAND circuit (NA3) is “High”. Since the output of the NAND circuit (NA4) remains “Lo” at a certain time after the terminal (INT) becomes “High” until the delay circuit (DL3) is ready.
w ", the transistor (BT27) is energized and the integrated charge of the capacitor (C11) is discharged. On the other hand, if the light emission of the first light does not reach 70% of the proper exposure, the NAND circuit (NA
The output of 3) is inverted to "Low". Therefore, the delay circuit (DL
Even when the output of 3) is inverted to "High", the output of the NAND circuit (NA4) remains "High", the transistor (BT27) does not conduct, and the integrated charge of the first lamp by the capacitor (C11) is retained. It remains as it was.

When the amount of light emitted from the first lamp reaches 70% of the proper exposure, the output of the AND circuit (AN15) becomes "High", the output of the inverter (IN9) becomes "Low", and the transistor (BT23) becomes conductive. The level of the non-inverting input terminal of the comparator (AC1) is the resistance (R
1/3) and constant current source (CI1) will be the level. The resistance value of this resistor (R1 / 3) produces a potential of 30% of the proper exposure with the constant current of the constant current source (CI1). On the other hand, when 70% of the proper exposure is not reached, the output of the NAND circuit (NA3) becomes "Low" and the transistor (BT25) becomes conductive. As a result, the level of the non-inverting input terminal of the comparator (AC1) becomes the level that can be set by the resistor (R1) and constant current source (CI1), and the resistance value of the resistor (R1) becomes constant current source (CI
With the current of 1), the potential of the level corresponding to the proper exposure is generated. Therefore, the voltage corresponding to the proper exposure level is applied to the non-inverting input terminal of the comparator (AC1). Then, the terminal (INT) falls to "Low" when the second light emission starts, and when the first light reaches 70%, the transistor (BT27) becomes non-conductive again and the transistor (BT29). The collector current of the capacitor (C1
It is integrated again in 1). On the other hand, when the exposure amount of the first light emission does not reach 70% of the proper exposure, the transistor (BT27) remains non-conducting, so the capacitor (C11) is integrated by the first light emission. Integration is performed so that the integrated charge of the second light is added to the charge. And if the exposure from the first light emission reaches 70% of the proper exposure, Under this condition, the light emission stop signal is output and the light emission amount of the second light is 30% of the proper exposure. In this case, the ratio of the light emission amount of the first light and the second light is 7: 3, and the sum of both light emission amounts is The proper exposure is obtained. On the other hand, if the amount of light emitted from the first light does not reach 70% of the proper exposure, Then, the light emission stop signal for the second light is output. Therefore, in this case, the ratio of the light emission amounts of the two lights cannot be suppressed to 7: 3, but the proper exposure is compensated by the two flashes.

In addition, when three lights continuously emit light, after the time required for the second light to start emitting light and the second light to fully emit light (2.5 msec.
After) The third light emits light. At this time, the pin (INT) is "Low"
As it is, the integration by the capacitor (C11) is continued and, for example, when the proper exposure is not reached by the light emission of the two lights, the light emission stop signal may be output to the line (l3) by the light emission of the third light. However, this light emission stop signal is not transmitted to the third flash device as shown in FIG. 1, and the third flash device emits light in an amount that can be used by the flash device. Also, the first and second flash units have a flash unit that receives the light emission stop signal only for 2.5 msec after the light emission of the second light starts for FDC signal output and that emits light for controlling the light emission amount. Start emitting light
Since the light emission stop signal is accepted only for 2.5 msec, the light emission stop signal by the light emission of the third light is the first light or the second light.
It does not cause a malfunction by acting on the flash device of the lamp.

Next, FIG. 9 shows a specific example of the flash unit (I) of FIG.
This will be described with reference to FIGS. 10, 11, 12, 13, and 14. FIG. 9 shows a concrete example of the control circuit (FLC1). When the pulse (width of FC mode, CF mode, ES mode, clock pulse for data transfer, pulse for light emission stop) is input from the terminal (l3) and the terminal (l3) becomes "High", the transistor (BT31 ) Becomes conductive and the inverter (IN
The force (p3) of 11) becomes "High". Mode discrimination circuit (TI
C) controls the operation of the flash device by detecting the "High" width of this pin (p3).

Next, the discrimination operation will be described based on a specific example of the mode discrimination circuit (TIC) shown in FIG. The terminal (p1) becomes "High" when the X contact (Sx) is closed and the line (l1) becomes the ground potential, and the transistor (BT39) shown in the lower left of Fig. 9 becomes conductive. It is a terminal, and it is "Low" when the pulse of width showing FC mode, CF mode, ES mode and the clock pulse for data transfer are input, and the output of the inverter (IN19) is "High". There is. When the pin (p3) goes high, the AND circuit (AN4
The output of 3) rises to "High", a "High" pulse is output from the one-shot circuit (OS3), and the counter (CO
1) After it is reset by the microcomputer (MC2)
The reference clock pulse (φ2) from the terminal (CKO) of is counted. Further, flip-flops (FF1) to (FF7) are set by the pulse from the one-shot circuit (OS3). The terminals (τ1), (τ2), (τ3) of the decoder (DE0) that inputs the signal from the counter (CO1),
From (τ4), 60μsec and 120μ from the start of counting respectively.
A pulse is output after sec, 180 μsec, and 240 μsec. Therefore, the flip-flop (FF1) is 60 from the start of counting.
Set state for μsec, (FF3) for 120μsec, (FF5)
Is set for 180 μsec and (FF7) is set for 240 μsec. Therefore, the AND circuit (AN45) is 60μsec ~ 120μ
Active state for sec, (AN47) is active for 120 μsec to 180 μsec, and (AN49) is active for 180 μsec to 240 μsec. And the one-shot circuit (OS5) is the terminal (p3)
Since the "High" pulse is output at the fall of the potential of, the pulse from the one-shot circuit (OS5) will be the AND circuit (AN4 if the potential of the terminal (p3) falls in 90μsec.
It is output from 5), the flip-flop (FF9) is set, and the terminal (FC) becomes "High". Meanwhile, the terminal (p3)
If it falls in 150μsec, one shot circuit (OS5)
The pulse from is output from the AND circuit (AN47), the flip-flop (FF11) is set, and the terminal (CF) becomes "Hi".
gh ". Furthermore, if the terminal (p3) falls in 210 μsec, the signal from the one-shot circuit (OS5) is output from the AND circuit (AN49), the flip-flop (FF13) is set, and the terminal (ES). Becomes “High.” The clock pulse is output from the AND circuit (AN43), and the pulse is output from the wasshot circuits (OS3) and (OS5). Since it is considerably narrower than 60 μsec, flip-flops (FF9), (FF1
It does not affect the status of 1) and (FF13).

When the terminal (FC) becomes "High", the reset state of the counter (CO3) is released and the decoder (DE1) becomes ready for output. Then, the counter (CO3) counts the falling edge of the signal obtained by inverting the data transfer clock pulse from the terminal (p3) by the inverter (IN21), that is, the rising edge of the clock pulse. Then, the decoder (DE1) outputs a "High" signal to the terminals (f0) to (f15) every time the content of the counter increases by "1". That is, counter (CO3)
If the output is "0001" (f0) is "High", and if it is "0010" (f
If 1) is "High" or "1000", (f7) is "High" or "1001"
If (f8) is "High", if "1111" (f14) is "High",
If "0000", (f15) becomes "High". This signal is used for gate control for data transfer. Furthermore, the terminal (f1
When 5) becomes "High", the AND circuit (AN44) becomes active and the signal from the inverter (IN21) is output. Then, the rise of the output of the inverter (IN21), that is, FC
A pulse is output from the one-shot circuit (OS4) at the falling edge of the 16th clock pulse in the mode, the one-shot circuit (OS6) is triggered at the falling edge of this pulse, and a pulse is output, and the flip-flop (FF9 ) Is reset, the pin (FC) becomes “Low” and the device enters standby mode. Further, when the standby (CF) becomes "High" to enter the CF mode, the reset state of the counter (CO4) is released and the decoder (DE2) becomes ready for output. The counter (CO4) counts the clock pulse from the inverter (IN21), and when it counts 24 (3 bytes) clocks, its output becomes "11000", and the terminal (g23) of the decoder (DE2) becomes "High". "become. And the AND circuit (AN46) becomes active and the inverter (IN21)
Is output from the one-shot circuit (OS8) at the falling edge of the 24th clock pulse, that is, the rising edge of the AND circuit (AN46), and the one-shot circuit (OS10) is output at the falling edge of this pulse. Outputs a pulse. Then, the flip-flop (FF11) is reset by the pulse from the one-shot circuit (OS10), the terminal (CF) becomes “Low”, and the CF mode is changed to the waiting mode. In the ES mode, in which the terminal (ES) becomes "High", when the shutter rear curtain of the camera body completes running and the X contact (Sx) is opened, the transistor (BT39) in Fig. 9 is displayed.
Becomes non-conductive, the terminal (p1) is "Low", and the inverter (IN1
The output of 9) becomes "High" and the one-shot circuit (OS7)
Outputs a pulse. As a result, the flip-flop (FF13) is reset, the terminal (ES) becomes "Low", and the standby mode is set.

Returning to FIG. 9, (FTC1) shown in the lower right corner is a light emission amount control circuit, and a specific example of this circuit (FTC1) will be described later with reference to FIG. Also, (MC2) is a microcomputer, and the operation of this microcomputer (MC2) is shown in Figs.
It will be described later based on the flowchart of the figure. In the waiting mode, the mode discrimination circuit (TIC) terminals (FC), (C)
F) and (ES) are all "Low", and the terminal (f0)
Since ~ (f15) is also "Low", the outputs of the NOR circuits (NO3) and (NO5) are "High". As will be described later, the output (INS) of the light emission control circuit (FTC1) is
When the X contact (Sx) is closed in the full state, it remains "Low" until 2.5msec has elapsed, then becomes "High" for 1msec, and then "Low" for 5.5msec. Then, it becomes “High” for 2 msec and remains “Low” after that. The signal from this terminal (INS) is the X contact (S
X) is closed and the output of the AND circuit (AN24) is forcibly set to "Low" even after it is fully charged. OR circuit (OR2)
It is output via the AND circuit (AN21) and OR circuit (OR5), and is output from the AND circuit (AN18) and AND circuit (AN19). The terminal (l2) is connected to the terminal (INS) by the transistors (BT35) and (BT37). ) Is output. In the waiting state, the AND circuit (AN24) outputs a "High" signal if the AND circuit (AN33) output is "High" when the battery is fully charged, and outputs a "Low" signal if it is not charged. Is output. And if it is full, a transistor (BT83),
(BT35) becomes conductive, a "High" signal is output to the line (l2), and if not charged, the transistors (BT81) and (BT37) become conductive and a "Low" signal is output.

When in FC mode, the mode discrimination circuit (TIC) pin (FC)
Becomes "High" and the output of the NOR circuit (NO5) and the output of the AND circuit (AN21) become "Low". When the terminal (f0) of the mode discrimination circuit (TIC) becomes "High", this signal sets the outputs of the OR circuits (OR7) and (OR5) to "High" and the terminal (l
Output a “High” signal to 2). This signal is shown in Table 1 above.
It becomes the signal of the bit b0, that is, the mounting signal. When the terminal (f1) of the mode discrimination circuit (TIC) becomes "High", the AND circuit (AN29) becomes active and the light emitting part (FLO2) of the flash unit (I) in Fig. 1 is in the bounce state. For example, if the switch (SB1) is closed and the signal is not in the "Low" signal bounce state, the switch (SB1) is opened and the "High" signal is output from the AND circuit (AN29).

Therefore, when the "High" signal is output from the AND circuit (AN29), the output of the AND circuit (AN18) becomes "High" and the output of the AND circuit (AN19) becomes "Low", and the transistor (BT83), (BT35) is turned on and "Hi" is added to line (l2).
gh "signal is output. On the other hand, when the" Low "signal is output from the AND circuit (AN29), the output of the AND circuit (AN18) is" Low "and the output of the AND circuit (AN19) is" High ". Then, the transistors (BT81) and (BT37) are turned on and a "Low" signal is output to the line (l2).
It becomes the parent-child signal of bit b1 of. Mode discrimination circuit (TIC)
When the terminal (f2) of is "High", the AND circuit (AN31) becomes active. As a result, the signal from the AND circuit (A33) is output. The AND circuit (AN33) is composed of two main capacitors (C) of the flash unit (I) shown in FIG.
1) When the charging voltage of (C2) reaches a predetermined value and the outputs of the charging completion detection circuits (CHD1) and (CHD2) both become "High", a "High" signal is output. The output of this AND circuit (AN33) is bit b2 in Table 1, that is, the line (l
It is output to 2). Mode discrimination circuit (TIC) terminal (f3)
When becomes "High", the AND circuit (AN35) becomes active, and the FDC signal from the dimming completion display circuit (INF) (details of which will be described later based on FIG. 12) is sent to the line (l2) in Table 1. It is output as a signal of bit b3 of. When the terminals (f4) and (f5) of the mode discrimination circuit (TIC) become "High", the terminals (f4) and (f5) are not connected to any other, so the output of the OR circuit (OR5) "Low", AND circuit (AN1
The output of 9) is "High" and the AND circuit (AN18) is "Low", the transistors (BT81) and (BT37) are conducting, and the signal of "Low" is output to the line (l2). This is, as shown in Table 1, bit b4 is a preliminary timing and bit b5 is a discrimination signal indicating that this system is used.

Mode discrimination circuit (TIC) terminals (f6) and (f7) are "High"
During this period, the output of the NOR circuit (NO3) becomes "Low", and the outputs of the AND circuits (AN18) and (AN19) both become "Low". Therefore, transistors (BT35) and (BT
37) becomes non-conductive, and the transistor (BT33) becomes conductive / non-conductive according to the signal input from the line (l2). Then, at this timing, as described in Table 1, the light emission mode signal determined by the flash controller is input. Line (l2) is "Hig
When it becomes "h", the transistor (BT33) becomes conductive and the output of the inverter (IN13) becomes "High". When the line (l2) becomes "Low", the transistor (BT33) becomes non-conductive and the inverter (IN13) becomes Output becomes “Low.” Mode discrimination circuit (TI
While the terminal (f6) of C) is "High", the AND circuit (AN25) becomes active and the clock pulse (7) from the terminal (p3).
The second pulse) is output, and the falling edge of this pulse causes the D flip-flop (DF3) to output the bit b from the terminal (p2).
6 Latch the signal. And when the terminal (f7) of the mode discrimination circuit (TIC) is "High", the AND circuit (AN27) becomes active, the eighth pulse is output from the terminal (p3), and the D flip-flop (DF5) becomes Latch the signal of bit p7 from pin (p2). Flip-flop (DF
The data latched in 3) and (DF5) is the microcomputer (MC
It is sent to the input terminals (i11) and (i12) of 2) and the light emission state according to the light emission mode is determined. If a flash device is installed in addition to this flash device (I),
As described in Table 1, since at least one of bits b6 and b7 is "High", the output of the OR circuit (OR8) becomes "High" and the output of the AND circuit (AN23) becomes the mode determination circuit. The output of the (TIC) terminals (f8) to (f15) is "Hi".
It is "High" during "gh" and the output of the NOR circuit (NO3) is "L".
No signal is output to line (l2) at ow ". In this case, as described above, the flash mode is the simultaneous flash mode or the sequential flash mode, and the signals of bits b8 to b15 are sent from the flash controller to line (l2). Then, the transistors (BT35) and (BT7) remain non-conducting during the time when they are read by the camera body and do not interfere with the data transfer between the flash controller and the camera body.

If the signals latched in the flip-flops (DF3) and (DF5) are both "Low", it means that only one flash unit is connected to the camera body. In this case, the output of the OR circuit (OR8) and AND circuit (AN23) becomes "Low", and the output of the NOR circuit (NO3) becomes "High".
8) and AND circuit (AN19) are active, line (l2)
Is ready to output data to. When the terminal (f8) of the mode discrimination circuit (TIC) becomes "High", this "High" signal is output through the OR circuit (OR9), and in the same manner as above, "High" is output to the line (l2). "Signal is output. This is the mounting signal of bit b8 shown in Table 1. When the terminal (f9) becomes “High”, the OR circuit (O
Since the output of R9) is "Low", the line (l2) becomes "Low". This is the discrimination signal of bit b9 shown in Table 1. When the terminal (f10) of the mode discrimination circuit (TIC) becomes "High", the signal indicating the open / closed state of the switch (SB1) is turned on by the AND circuit (A
N37), is output from the OR circuit (OR9) and is output to the line (l2). This is the sequential light emission signal of bit b10 in Table 1, and if the light emission unit (FLO2) is in the bounce state, it will be in the sequential light emission mode (parent-child light emission mode), so line (L2) becomes "Low" It is determined that the main body is in the sequential light emission mode (parent-child light emission mode). When the terminal (f11) of the mode discrimination circuit (TIC) becomes "High", the AND circuit (A
The charge completion signal from N33) is output to the line (l2) via the AND circuit (AN39) and the OR circuit (OR9).

By the way, the flip-flop (FF2) is a mode discrimination circuit (T
It is reset by the pulse output from the one-shot circuit (OS2) when the terminal (FC) of IC) becomes "Hihg". Then, in the single-lamp emission mode, when the transistor (BT35) is turned on as a completion signal by bit b11, the transistor (BT33) is turned on and the terminal (p2) goes "High".
become. In this case, the AND circuit (AN20) remains "Low" and the flip-flop (FF2) remains in the lincset state. Therefore, the output of the NAND circuit is "High" and the AND circuit (A
N22) is activated, and the light emission start signal from the terminal (p1) is transmitted to the light emission control circuit (FTC1). On the other hand, when charging is not completed, the transistor (BT37) becomes conductive and the line (l2) becomes "Low".
33) becomes non-conductive and the terminal (p2) becomes "Low". As a result, the flip-flop (FF2) is set and the output of the NAND circuit (NA5) becomes "Lo" when the terminal (ES) becomes "High".
Even if the AND circuit (AN22) becomes disabled and the light emission start is output from the terminal (p1), the flash will not fire. Therefore, based on the charge completion signal sent to the camera body by bit b11. The system does not malfunction because it determines whether the flash device itself emits light and the camera body determines whether to perform flash light photography based on the charge completion signal sent by bit b11.

When in multi-light mode, the flash unit will use bits b8 to b15
Signal is not output, but as will be described later by the flash controller, “High” if both flash devices are in a full state, and “Low” if at least one of them is in a full state.
The signal of is output to the line (l2). Then, this signal is read by the camera body as a full signal, and also in the flash device, it is read by the flip-flop (FF2) to determine whether or not to emit light.

Also, the output to the line (l2) of the flash unit is "Hig
The output current when outputting the "h" signal is less than the input current when outputting the "Low" signal. That is, there is a difference in the impedance. It operates as follows. It has such a configuration in order to allow it.

A connector for connecting multiple terminals of two or more flash devices in parallel to the camera body in parallel is provided, and a connector for increasing the number of lights for simultaneously flashing each flash device is conceivable. When such a connection is made, the terminal (f11) becomes “High”, and when the charging completion signal is output, at least one flash device is not in the charging completed state, and at least one flash device transistor (BT37) Is conducting and the transistor (BT35) is conducting in other flash devices,
The current from the transistor (BT35) is a constant current circuit (CI10).
Since it is limited to a constant current by the transistor (BT83), even if the transistor (BT35) becomes conductive, this output current will flow into the transistor (BT37) of another flash device that has not been charged yet. Therefore, the transistor (BT33) cannot conduct in any flash device, the flip-flop (FF2) is set, and the flash device connected to the additional light emitting connector cannot emit light.

When the terminal (f12) of the mode discrimination circuit (TIC) becomes "High", the signal from the dimming completion display circuit (INF) changes to the AND circuit (A).
It is output to the line (l2) via the N41) and the OR circuit (OR9). These are the FDC signals indicated by bit b12 in Table 1, which are read by the camera body and used to display the status of the flash unit. Mode discrimination circuit terminals (f13), (f
14) and (f15) are "High", the output of the OR circuit (OR9) is "Low" and the line (l2) remains "Low". It is a spare bit as shown.

Next, the light emission control operation in the ES mode will be described with reference to FIGS. 9 and 11. When the X contact (Sx) of the camera body V in FIG. 1 is closed and the terminal (p1) becomes "High", if the flip-flop (FF2) is in the reset state at this time, the NAND circuit (NA5) becomes "High". ", And the output (FSA) of the AND circuit (AN22) becomes" High "when it is in the full state. As a result, the one-shot circuit (OS9) of FIG. 11 outputs a "High" pulse, and the pulse resets the flip-flop (FF15) via the OR circuit (OR13), and flip-flops (FF17), ( (FF14) is set and the Q output of the flip-flop (FF14) becomes "High", the reset state of the counter (CO5) is released, and the decoder (DE3) becomes ready for output. The terminal (p1) of the decoder (DE3) is "High"
After 2.5 msec has elapsed, a "High" pulse is output, after 3.5 msec, a "High" pulse is output from the terminal (τ6), and when 6 msec has elapsed, a "High" pulse is output from the terminal (τ7).
Pulse is output, and when 9msec has passed, a "High" pulse is output from the terminal (τ8), and when 11msec has passed (τ9)
Outputs a “High” pulse. Therefore, the Q output of the flip-flop (FF15) remains "Low" for 2.5 msec after the terminal (p1) becomes "High" (p1) becomes "H".
It becomes "igh" and "High" for 2.5msec ~ 3.5msec, 3.5msec
It becomes "Low" again during ~ 9msec, becomes "High" again after 9msec, and becomes "Low" again after 11msec. This Q output is input to the OR circuit (OR2) of FIG. 9 through the terminal (INS). At this time, the terminal (p1) is “Hig
By becoming "h", the AND circuit (AN2
The output of 4) becomes "Low" and the signal from the terminal (INS) is output from the OR circuit (OR2). In the ES mode, since the output of the NOR circuit (NO5) is "High", it is directly output from the AND circuit (AN21) and is output to the line (l2) in the same manner as the above signal. This signal is used in the camera body as a signal for controlling the light emission amount described above with reference to FIG. When this flash device is attached to the camera body that does not output the pulse indicating the mode to the line (l3), the terminal (ES) is "Low", so if it is in the full state, the "High" from the terminal (p1) will be It is output to the terminal (FSA) and the light is emitted.

The terminal (O13) of the microcomputer (MC2) in FIG. 9 is a terminal that becomes "High" in the sequential light emission mode and the first light emission mode as described later. The terminal (O11) is a terminal that becomes "High" in the parent-child emission mode. The terminal (O12) is a terminal that becomes "high" in the sequential light emission mode and the post light emission mode.

(O10) is a terminal that becomes “High” in the simultaneous light emission mode or the single-lamp light emission mode. The terminal (O14) is "High" in the automatic dimming mode and "Lo" in the manual setting mode.
In Fig. 9, (FLD) is a circuit that outputs a signal of the amount of light emission in the automatic light control mode and the manual setting mode, and the output terminal (e of this circuit (FLD)
Table 3 shows the relationship between 1), (e2) and the output terminals (d1), (d2), (d3) of the decoder (DE5) in FIG. 11, the light emission mode, and the light emission amount.

As is clear from this table, when only half the total light emission is emitted, the terminal (d2) of the decoder (DE5) becomes "High" and the transistor (BT43) becomes conductive. Then, the light emitting unit (FL
The emitted light of O2) is directly received by the phototransistor (PT1), and the output current of this phototransistor (PT1) is
When the output of the OR circuit (OR21) becomes "High" to make the light emitting unit (FLO2) emit light, the output of the OR circuit (OR20) becomes "Low", and the transistor (BT45) becomes non-conductive. It is integrated by the capacitor (C15). When the integrated voltage of the capacitor (C15) exceeds the potential of the resistors (R5) and (R7), the output of the comparator (AC3) is inverted to “High”, and the one-shot circuit (OS11) outputs “High” pulse. Is output, and the light emission is stopped by this pulse. When only 1/4 of all light is emitted, the terminal (d3) becomes "High" and the transistor (BT41) becomes conductive. Then, the output current of the phototransistor (PT1) is integrated by the capacitor (C13) having half the capacity of the capacitor (C15). Therefore, the light emission stop signal has half the amount of light emitted when the terminal (d2) is "High". In the case of full flash and automatic dimming, the terminal (d1) is "High" and the OR circuit (OR20) is "H".
The transistor (BT45) remains conductive and the one-shot circuit (OS11) does not output a pulse for stopping light emission.

First, the operation in the parent-child emission mode will be described. In this case, the terminal (O11) of the microcomputer (MC2) is "High", and the outputs of the OR circuits (OR15), (OR17), (OR19) are "High". Therefore, at this time, the X contact (Sx) is closed.
The output of the AND circuit (AN51) becomes "High" for 2.5 msec, the output (ST2) of the OR circuit (OR21) becomes "High", and the light emitting unit (FLO2) emits light. During this light emission, if the AND circuit (AN65) is active in the automatic dimming mode, and if a light emission stop signal from the camera body is input through the terminal (p3), that signal will be output. ), OR circuit (OR
25) is output to the terminal (SP2) via the light emitting unit (FLO2)
Stop the flashing of. In the manual setting mode, the AND circuit (AN63) is active and the one-shot circuit (OS1
The light emission stop signal from 1) is output to the terminal (SP2) via the AND circuit (AN63) and the OR circuit (OR25), and the light emission unit (F
Stop the emission of LO2). Next, the output (ST1) of the AND circuit (AN55) becomes "High" and the light emitting unit (FLO1) from the time when 3.5 msec has passed after the X contact (Sx) closed until 6 msec has passed. Emits light. And in the automatic light control mode, if the terminal (O14) of the microcomputer (MC2) is "High",
A light emission stop signal from the terminal (p3) is output from the AND circuit (AN67) to the terminal (SP1), and the light emission of the light emitting unit (FLO1) is stopped. On the other hand, in the manual setting mode, since the terminal (O14) of the microcomputer (MC2) is "Low", the light emission stop signal is not output from the AND circuit (AN67) and the light emission unit (FLO
1) emits all light. In this case, in the automatic light control mode, the second light emission stop signal from the terminal (p3) is output via the AND circuit (AN61), OR circuit (OR23), and AND circuit (AN69). Is input to the dimming completion display circuit (INF) via the terminal (FDS).

In the simultaneous light emission mode or the single light emission mode, the terminal (O10) of the microcomputer (MC2) becomes "High" and the OR circuit (O2)
The output of R17) becomes “High”. Therefore, the output of the AND circuit (AN51) becomes "High" and the output (ST2) of the OR circuit (OR21) becomes "High" for 2.5 msec after the X contact (Sx) is closed. As a result, the light emission part (FLO2) emits light, and in the automatic light control mode, the light emission stop signal input from the terminal (p3) during this light emission is output from the AND circuit (AN65) to the terminal via the OR circuit (OR25). It is output to (SP2) and the light emission of the light emitting unit (FLO2) is stopped. On the other hand, in the manual setting mode, the pulse from the one-shot circuit (OS11)
It is output to the terminal (ST2) via the AND circuit (AN63) and the OR circuit (OR25), and the light emission of the light emitting unit (FLO2) is stopped. In this case, the "High" signal is not output to the terminal (ST1), and the light emitting unit (FLO1) does not emit light. 2.5 ms after the X contact (Sx) is closed in the dimming completion display circuit (INF)
The light emission stop signal input from the terminal (p3) during ec is AND circuit (AN59), OR circuit (OR23), AND circuit (AN
69) is entered via.

In the sequential firing mode and the first firing mode, the terminal (O1
3) becomes "High", and OR circuit (OR15), (OR17),
The output of (OR19) becomes "High" and the terminal (ST2) becomes "High" for 2.5 msec after the X contact (Sx) is closed. As a result, the light emitting unit (FLO2) emits light, and during this light emission, from the terminal (p3) or the one-shot circuit (OS11).
The light emission is stopped by the light emission stop signal from. In addition, after the X contact (Sx) is closed in the dimming completion display circuit (INF)
The light emission stop signal that is input from the terminal (p3) from the time when 3.5msec has elapsed until the 6msec has elapsed after the X contact (Sx) is closed is the AND circuit (AN61), OR circuit (OR
23), and input through the AND circuit (AN69). Therefore,
Even if the first light emission does not reach 2/3 of the proper exposure, if the sum of the first light emission and the second light emission becomes appropriate, the FDC display is performed.

In the post-emission mode, the AND circuit (AN53) becomes active, and 3.5 msec has passed since the X contact (Sx) was closed, and 6 msec has passed since the X contact (Sx) was closed. Until then, the output of the AND circuit (AN53) becomes “High”, the light emitting part (FLO2) emits light, and the terminal (p
3) Or the light emission stop signal from the one shot circuit (OS11) is output to the terminal (SP2), and the light emission of the light emitting unit (FLO2) is stopped. Also, in the dimming completion display circuit (INF),
When 3.5 msec has passed after the X contact (Sx) was closed, X
The light emission stop signal is input from the terminal (p3) that is input within 6 msec after the contact (Sx) is closed. The flash unit (FLO1) is also available in the first and second flash modes.
Does not emit light.

Next, the dimming completion display circuit (INF) will be described with reference to FIG. Output terminal (FDC1) of the light emission control circuit (FTC1)
When the light emission stop signal for indicating the dimming completion is input from S), the flip-flop (FF21) is set. At this time, ES
In the mode, the terminal (E) of the mode discrimination circuit (TIC) in Fig. 9
S) is "High", so the output of the AND circuit (AN71) is "Lo".
The counter (CO7) is in the reset state when it becomes w ". And the terminal (ES) becomes" Low "in the waiting mode.
And the output of the AND circuit (AN71) becomes "High",
The output of the inverter (IN20) becomes "Low" and the FDC signal is output to the AND circuit (AN35). Also, when the output of the AND circuit (AN71) becomes "High", the counter (CO7)
The reset state of is released, and the counter (CO7) starts counting the clock pulse (φ2) from the microcomputer (MC2). An 8 Hz clock pulse is output from the terminal (to) of the counter (CO7), and the light emitting diode (LD1) blinks at 8 Hz by the transistor (BT47). And 3s
When ec elapses, the terminal (t1) becomes "High", the flip-flop (FF21) is reset through the OR circuit (OR27), the counter (CO7) is reset, and the output of the inverter (IN20) becomes "High". It becomes "High" and the light emitting diode (LD1) goes out. Also, when the shooting interval is short, the mode becomes ES mode while the light emitting diode (LD1) is displayed, and the terminal (ES) of the mode discrimination circuit (TIC) in FIG.
When it becomes "igh", the output of the AND circuit (AN71) becomes "Low" and the output of the inverter (IN20) becomes "High". Furthermore, the counter (CO7) becomes reset and the light emitting diode (LD1) becomes The light goes off, and the terminal (ES) goes to “Hig
When it becomes "h", a pulse is output from the one-shot circuit (OS13) and the flip-flop (FF21) is reset.

Next, based on the flowcharts in FIGS. 13 and 14,
The operation of the microcomputer (MC2) in the figure will be described. When the terminal (CF) of the mode discrimination circuit (TIC) becomes "High" in CF mode, a "High" signal is input to the interrupt terminal (it) of the microcomputer (MC2), Start operation. S3
In the step of, the interruption to the terminal (it) of the microcomputer (MC2) is enabled, and the data to the terminal (SIN) is read based on the clock pulse from the terminal (p3) to the terminal (SCK). And this flash photography aperture value data (Av
Set f) to the specified register in the microcomputer (MC2).
Similarly, serial data (film sensitivity value Sv and exposure control mode) is read and set in a predetermined register of the microcomputer (MC2). Further, another 1-byte lens focal length data (fv) is read and set in a predetermined register in the microcomputer (MC2). As described above, the data from the camera body is read. Next, data for counting a fixed value (for example, 10 seconds) is set in the internal counter, and when the counter reaches the set predetermined value, an interrupt is applied. Next, terminals (i13) and (i14) are "High".
If both are “High”, the automatic light control mode is set, and thus the process proceeds to step S15. On the other hand, if at least one of the terminals (i13) and (i14) is "Low", it is determined in step S14 whether the exposure control mode read from the camera body is the M mode. If the mode is the M mode, the mode is the manual setting mode, and the process proceeds to step S18. On the other hand, if it is not the M mode, even if the flash device is set to the manual setting mode, the automatic light control mode is set and the process proceeds to step S15. In step S15, the automatic light control mode is set and the process proceeds to step S15. In step S15, automatic display indicating the automatic light control mode is performed, the terminal (O14) is set to "High", the flag AMF is set to "1", and the process proceeds to step S21. On the other hand, S1
In step 8, the manual display indicating that the manual setting mode is set is performed, the terminal (O14) is set to "Low", the flag AMF is set to "0", and the process proceeds to step S21.

From step S21, terminals (i10), (i11), (i12)
The light emission mode is determined according to the input signal to the. Terminal (i1
If 2) and (i11) are "High", it means the simultaneous flash mode. In step S23, the simultaneous flash mode is displayed.
Set the terminal (O10) to "High", then the terminals (O11), (O12),
(O13) is set to "Low" and the process proceeds to step S34. Then, in the step of S34, it is determined whether or not the terminal (i10) is "High", and if it is "High", the light emitting unit (FLO2) is in the front light state, and the process proceeds to the step of S36. Meanwhile, the terminal (i10)
If is "Low", it means that the device is in the bounce state, so the bounce display is made and the process proceeds to step S60. If the terminal (i12) is "High" and the terminal (i11) is "Low", it is the first light emission. In this case, in step S24, the terminal (O13) is set to "High" to indicate that it is in the first light emission mode. (O10), (O11),
(O12) is set to “Low” and the process proceeds to step S55. If the terminal (i12) is "Low" and the terminal (i11) is "High", it is the post-emission mode, and the terminal (O12) is "High" in the step of S27.
To indicate that it is in the post-flash mode, and the terminal (O1
Set 0), (O11), and (O13) to "Low", and move to the step of S34. When the terminals (i12) and (i11) are "Low", it means that only the flash unit (I) is attached to the camera body directly or via the controller.
Go to step. Terminal (i10) in step S29
Is "High", and if the terminal (i10) is "High", the light emitting unit (FLO2) is in the front light state, the single light emission mode is set, and the single light emission display state is set in step S30. Is displayed, and the process proceeds to step S31. Meanwhile, the terminal (i1
If "0" is "Low", the flash unit (I) 's light emitting part (FLO
2) is in the bounce state and becomes the parent-child flash mode. At this time, the parent-child flash mode is displayed in step S48, and terminal (O11) is set to "High", terminal (O10),
Set (O12) and (O13) to “Low”. Then, the light emitting unit (FL
Based on the maximum light emission amount and the minimum light emission amount of O1), the maximum value and the minimum value Iv _M , Ivm of the light emission amount are set, and the process proceeds to step S41.

In step S36, irradiation angle data (this is the light emitting unit (FLO
The irradiation angle of 2) is variable, and (ZD) outputs data according to this irradiation angle) from the irradiation angle data output circuit (ZD) and displays the irradiation angle. Then, it is determined whether or not the flag AMF is "1". If the flag AMF is "1", the level of the input terminals (i13) and (i14) is determined if the flag AMF is "1" in step S40. Then, in the automatic light control mode or the full light emission mode, the maximum light emission amount of the light emitting unit (FLO2) is Iv _M , and the minimum light emission amount is Ivm. On the other hand, if the total light emission mode is not set, the maximum light emission amount set at that time is set to Iv _M , and the minimum light emission amount set to Ivm, and the process proceeds to step S41. In the step of S41, it is determined whether or not the interchangeable lens is attached to the camera body, and if the lens is not attached, the display without the lens is displayed and the process proceeds to the step of S59. If the interchangeable lens is not attached to the camera body, specific data is input to the flash device as aperture value data Avf, and when the flash determines that this data has been input, the interchangeable lens Determine that it is not installed. If it is determined in step S41 that the lens is attached, the process proceeds to step S43, and Iv _M + Sv-Avf = Dv Ivm + Sv-Avf = Dvm ... Shooting distance Dv _M
And the shortest shooting distance Dvm. Next, the shortest shooting distance D
It is determined whether vm is shorter than the limit shooting distance Dv _M determined by parallax, etc., and when Dvm <Dv _M , the limit shooting distance DV _M is adopted as the shortest shooting distance Dvm, and the process proceeds to step S52. .

In step S52, it is determined whether the flag AMF is "1",
If it is "1" in the automatic light control mode, the interlocking range is displayed from the maximum light emission amount Iv _M and the minimum light emission amount Ivm, and if the flag AMF is "0" and the manual setting mode is based on the maximum light emission amount Iv _M , Displays the shooting distance for proper exposure. Then, after displaying the aperture value based on the flash shooting aperture value data Avf, the focal length based on the interchangeable lens focal length data fv, and the film sensitivity based on the film sensitivity data Sv, step S1
Return to 2 and repeat the operation of fetching setting data, calculation, and display, and the terminal (CF) of the mode discrimination circuit (TIC) is "High".
Then, when the interrupt terminal (it) becomes "High", the operation from step S3 is performed again. In step S55, it is determined whether or not the interchangeable lens is attached as in S41,
If the lens is attached, the process proceeds to step S57, and if not attached, the lens is not attached and the process proceeds to step S59.

The mode in which the interlocking range or the shooting distance for proper exposure is displayed is simultaneous flashing, single-flash flashing, post-flashing mode when the bounce state is not set, and parent-child flashing mode. The interlocking range or shooting distance based on the part (FLO1) is displayed. The interlocking range or the shooting distance is not displayed in the first light emission mode, and when the light emission unit (FLO2) is in the bounce state with simultaneous light emission and post light emission. If the flash is in the bounce state with simultaneous flash emission, post-flash emission, and single-flash emission, after the bounce display is performed in step S35, S
Go to step 60. If the bounce occurs during the post-emission, the probability of being appropriate is low, so a warning is given and the process proceeds to step S55.

In Fig. 14, when power is supplied to the microcomputer (MC2), S
Perform the operation from step 70. First, in step S70, the display (FDP1) is turned off, and the terminal (it) can be interrupted and the terminal (O10) is set to "High" in order to set the simultaneous mode or the single light emission mode. O11), (O1
2) Set (O13) to "Low" and move to the step of S74.

In step S74, the signals from the input terminals (i13) and (i14) are discriminated to determine whether the mode is the automatic light control mode. If it is in the automatic light control mode, the automatic display is performed and the terminal (O1
4) is set to "High", the flag AMF is set to "1", and the process proceeds to step S8.1. In step S74, the manual display is performed to determine that the flash mode is not automatic, and the terminal (O1
4) is set to "Low", the flag AMF is set to "0", and the process proceeds to step S81. In S81 step, Sv equivalent to ISO100
= 5, and in the step of S82, the input terminal (i
Determine the signal from 10) to determine if the light emitting unit (FLO2) is in the bounce state. If it is in the bounce state, the bounce display is performed in step S94, and then the process proceeds to step S95. When it is determined in step S85 that the cup (FLO2) is in the front light state, the process proceeds to step S83, and the irradiation angle data is fetched from the irradiation angle data output circuit (ZD). Then, the irradiation angle is displayed based on the data. Then the flag AMF
When is “1”, it is determined whether it is the automatic light control mode. And
In the automatic light control mode, the maximum light emission amount Iv and the minimum light emission amount Ivm based on the irradiation angle of the light emitting unit (FLO2) are set. Then, Iv + Sv = Gv Ivm + Sv = Gvm is calculated, and the maximum guide number Gv in ISO100
And the minimum guide number Gvm is displayed, and the process proceeds to step S95. On the other hand, if it is determined in step S85 that the AMF is "0" and the mode is not the automatic light control mode, the signal of the set value from the terminals (i13) and (i14) and the light emission amount Iv based on the irradiation angle are set,
Gv = Iv + Sv is calculated, the light emission guide number Gv based on the set value is displayed, and the process proceeds to step S95.

In step S95, no lens is displayed to indicate that the lens data is not sent from the camera body, ISO100 is displayed, and the process proceeds to step S97. Steps S97, 98, 99 repeat whether or not the setting state of the external setting means has changed, and if the setting state has changed, the process returns to step S70 to perform the above-mentioned operation again to switch the display state.

An interrupt signal from the terminal (CF) to the interrupt terminal (it) is input,
For a certain period of time (for example, after enabling the counter interrupt)
If the interrupt signal is not input from the terminal (CF) within 10 seconds, the internal counter of the microcomputer (MC2) will interrupt and the operation from step S70 will be performed. Therefore, the data from the camera body is no longer input and 10se
During the period between c, the display is performed based on the data from the camera body, and after 10 seconds, only the data that can be displayed with the value set by the flash device will be displayed.

Next, the flash device (II) or (III) will be described with reference to FIGS. FIG. 15 shows a specific example of the control circuit (FLC2) or (FLC3) of FIG. 1, only the portions different from FIG. 9 are shown, and the corresponding terminals are given the same reference numerals as in FIG. (See FIG. 9 for parts that are the same as each other). In the case of this flash device, the light emitting unit has only one (FLO3) or (FLO4) and does not enter the parent-child light emitting mode. Therefore, in the FC mode, it is not necessary to output a signal indicating the parent-child mode in bits b1 and b10, so the terminals (f1), (f10) of the mode discrimination circuit (TIC)
Are output to the OR circuits (OR7) and (OR9) as they are, and "High" signals are output as the bits b1 and b10. Further, the microcomputer (MC3) is not provided with a terminal (O11) for outputting a "High" signal indicating the parent-child light emission mode. Furthermore, the emission control circuit (FTC2) and the microcomputer (MC
The operation of 3) is different from that of the flash device (I), but different parts will be described with reference to FIG.

FIG. 16 shows only parts different from FIG. 11 (refer to FIG. 11 for the same parts). First, in the simultaneous or single light emission mode, the terminal (O10) of the microcomputer (MC3) in FIG.
The output of the OR circuit (OR31) becomes "High".
Therefore, from the terminal (ST4), the X contact (S
x) is closed and 2.5 msec has passed, “Hig
Q of flip-flop (FF17) (see Fig. 11) that becomes h "
The output is output from the terminal (ST4) via the AND circuit (AN75) and the OR circuit (OR35), and the light emitting unit (FLO shown in FIG. 1 is shown.
3) or (FLO4) emits light. Then, during the light emission, in the automatic dimming mode, the light emission stop signal from the terminal (p3) passes through the AND circuit (AN83) and the OR circuit (OR39) to the terminal (SP
4) and is also sent to the dimming completion display circuit (INF) via the AND circuit (AN87) to stop the light emission of the light emitting unit (FLO3) or (FLO4) shown in FIG. Then, the dimming completion is displayed. In the manual setting mode, the pulse from the one-shot circuit (OS11) (see FIG. 11) is output through the AND circuit (AN85) and the OR circuit (OR39) to stop the light emission. In the first flash mode, the microcomputer (MC
The terminal (O13) of 3) becomes “High” and the OR circuit (OR3
1), (OR33) output becomes “High”. Then, the Q output of the flip-flop (FF17) is output via the AND circuit (AN75) and the OR circuit (OR35), and the light emitting unit (FLO3) or (FLO4) emits light immediately when the X contact is closed. Also in this case, the light emission is stopped by the light emission stop signal input during the light emission. On the other hand, the dimming completion display circuit (IN
If the automatic dimming mode is selected for F), "Hig" will be applied for 2.5 msec after 3.5 msec has passed since the X contact (Sx) was closed.
The Q output of the flip-flop (FF19) which becomes h "is output from the AND circuit (AN81) and the OR circuit (OR37), and the light emission stop signal input from the terminal (p3) is input during this period. For example, the terminal (O12) becomes "High", the output of the OR circuit (OR33) becomes "High", and it becomes "High" for 2.5msec after 3.5msec has passed from the time when the X contact was closed. The Q output of the flip-flop (FF19) is output through the AND circuit (AN79) and the OR circuit (OR35) to start the light emission, and the terminal (p3) or the one-shot circuit (OS11) input during this light emission. The light emission is stopped based on the light emission stop signal of No. 2. At this time, in the automatic dimming mode, the stop signal input from the terminal (p3) during light emission is sent via the AND circuit (AN87) to the dimming display unit (INF). Sent to.

FIG. 17 is a flowchart of the operation of the microcomputer (MC3) shown in FIG. 15, showing only the portions different from the flowchart of FIG. 13, and the same portions as those of FIG. 13 will be described with reference to FIG. .

From S21, the light emission mode is determined by looking at the output states of terminals (i11) and (i12) as in FIG. Terminal (i12), (i1
If both 1) are "High", it means the simultaneous flash mode.
In step S105, the simultaneous flash mode is displayed. In step S105, terminal (O10) is set to "High" and terminals (O12), (O
13) is set to "Low", the process proceeds to step S34, and it is determined whether or not it is in the bounce state. If the terminal (i12) is "High" and the terminal (i11) is "Low", it is in the first-flash mode. In step S102, the first-flash mode is displayed, and the terminal (O13) is "High", the terminal (O10). , (O12) are set to “Low” and the process proceeds to step S55 in FIG. The terminal (i12) is "Low" (i1
If 1) is "High", the post-emission mode is displayed, and terminal (O12) is "High" and terminals (O10) and (O13) are "Low".
Go to step S34. If both terminals (i12) and (i11) are "Low", the single-lamp emission mode is displayed in step S104, and the process proceeds to step S105.

Figure 18 shows the internal circuit (CN) of the flash controller (IV).
It is a figure which shows the specific example of C).

(TIC) is a mode discriminating circuit, which is the same as the mode discriminating circuit in FIG. 9 showing a concrete example in FIG. 10 and is denoted by the same reference numeral. First, the operation in the FC mode will be described.
First, the terminals (f0) to (f5) of the mode discrimination circuit (TIC) are "H".
The output of NOR circuit (NO11), (NO15) is "Low" during "igh"
Then, AND circuits (A2), (AG64), (AG1), (A
G65) becomes disabled and data from lines (l2) and (l12) are read. And the signal from the line (l2) is a transistor (BT53) and an inverter (IN27).
The signal from the line (l12) is output to the terminal (r21) via the transistor (BT69) and the inverter (IN31). The signals of the bits b0, b2, b3, b5 from the terminal (r21) are latched by the D flip-flops (DF11), (DF13), (DF15), (DF17). On the other hand, the signals of bits b0, b1, b2, b3, b5 from the terminal (r22) are D flip-flops (DF19), (DF21), (DF2
3), (DF25), (DF27). The switch (SS) is opened when the sequential light emission mode is selected and closed when the simultaneous light emission mode is selected. D flip-flops (DF11) and (DF19) are both Q
If the output is "High", it means that two flash devices are installed, and the output of the AND circuit (AG47) is "High". On the other hand, if the Q output of at least one of the D flip-flops (DF11) or (DF19) is "Low", it means that the two flash units are not installed, and the output of the AND circuit (AG47) is "Low". The output (α0) of the AND circuit (AG45) and the output of the AND circuit (AG59) are both "Low". D flip-flop (DF
17) and (DF27) are flip-flops that latch the distinguishing signal at bit b5, but when both are inputting a "Low" signal, both flash devices are compatible with this system. At this time, the AND circuit (AG63) outputs a "High" signal. On the other hand, if at least one of the two flash devices is of a type that outputs only a "High" signal to the terminal (l2), an AND circuit (AG63)
Output goes low. Then, the AND circuit (AG61) is a flash device both of which are adapted to this system, and the output of the AND circuit (AG61) becomes "High" when the sequential mode is selected. On the other hand, if at least one of the flash devices is not suitable for this system, the mode is sequentially selected and the output of the AND circuit (AG61) is "Low" even if the switch (SS) is opened. And
And circuit (AG47) with two flash devices installed
Is "High" and the output of the AND circuit (AG61) is "High", the light emission modes are sequentially set, and the output (α0) of the AND circuit (AG45) becomes "High". Meanwhile, AND circuit (AG47)
If the output of the AND circuit (AG61) becomes "Low" even if the output of the AND circuit becomes "High", the output of the AND circuit (AG59) becomes "High".
It becomes a simultaneous mode.

In the sequential mode, the mode discrimination circuit (TIC) terminal (f
When “6” is “High”, “Low” from AND circuit (AG59)
Signal is AND circuit (AG41), OR circuit (OR47),
It is output to the line (l2) via (OR43), (OR41), the AND circuit (AG1), and the transistor (BT57). Then, when the terminal (f7) of the mode discrimination circuit (TIC) becomes "High", the "High" signal from the AND circuit (AG47) causes the AND circuit (AG43), OR circuit (OR47), (OR43), (OR4).
1), is output to the line (l2) via the AND circuit (AG2) transistor (BT55). Therefore, the flash device directly connected to the hot shoe of the camera body is "01",
That is, a signal indicating the post-emission mode is sent. On the other hand, when the terminal (f6) is "High", "H" from the AND circuit (AG47)
The signal of "igh" is AND circuit (AG55), OR circuit (OR5
1), AND circuit (AG64), and transistor (BT65) to output to line (l2). Then, when the terminal (f7) of the mode discrimination circuit (TIC) becomes "High", the "Low" signal from the AND circuit (AG59), AND circuit (AG57), OR circuit (OR51), AND circuit (AG65), It is output to the line (l12) via the transistor (BT67). Therefore, a signal of "10", that is, the first light emission mode is input to the flash device directly connected to the flash controller.

In simultaneous emission mode, AND circuit (AG47), (AG5
The outputs of 9) are both "High". Therefore, from the AND circuits (AG41), (AG43), (AG55), (AG57), when the terminals (f6) and (f7) are "High", A "High" signal is output and is sent to both flash devices.
That is, the simultaneous flash mode signal of "11" is sent to both flash devices. When neither the sequential mode nor the simultaneous mode, that is, when the flash device is not installed or only one is installed, the output of the AND circuit (AG47) becomes "Low", and the AND circuit (AG59) outputs The output also goes "Low". Therefore, as for it b6 and b7, the signal of "00" is output to the lines (l2) and (l12), and the flash device that read this signal determines that only the read flash device itself is attached to the camera. To do.

Next, data transfer while the terminals (f8) to (f15) of the mode discrimination circuit (TIC) are "High" will be described. First, D
When the output of the flip-flop (DF19) is "High", that is, when the mounting signal is not input from the line (l12), the terminal (α3) becomes "High", and the output of the OR circuit (OR46) during this period. Is high, the output of the AND circuit (AG13) becomes high. Therefore, the NOR circuit (N
The output of O11) becomes "Low", and AND circuit (AG2), (AG
1) is disabled and line (l2) is in a high impedance state. When the mounting signals are input from both lines (l2) and (l12), the output of the AND circuit (AG47) is "High".
And the AND circuit (AG21) becomes active. First, the "High" signal at the terminal (f8) is sent from the OR circuit (OR49) through the AND circuit (AG21), OR circuits (OR43), (OR41), the AND circuit (AG2), and the transistor (BT55) to the line (l).
It is output to 2). This is the mounting signal of bit b8 shown in Table 1. The terminal (f9) of the mode discrimination circuit (TIC) is "H".
When it becomes "igh", D flip-flop (DF27), (DF17)
OR circuit (OR55) output (α6)
The inverted signal is output from the AND circuit (AG33) and output to the line (l2). Output of OR circuit (OR55) (α
In 6), if at least one of the flash devices compatible with this system is installed, it becomes "High", and this is inverted and output, so that at least one of the flash devices compatible with this system is installed. And “Lo
The signal of w "is output from the line (l2). This is the discrimination signal shown by bit b9 in Table 1. When the terminal (f10) of the mode discrimination circuit (TIC) becomes" High " A signal obtained by inverting the output (α0) of the AND circuit (AG45) is output from the AND circuit (AG35).
Becomes "High" in the sequential light emission mode. Therefore, this signal is the sequential signal shown by bit b10 in Table 1. When the terminal (f11) of the mode discrimination circuit (TIC) becomes "High", the output (α2) of the AND circuit (AG49) is output from the AND circuit (AG37) and is output to the line (l2). The AND circuit (AG49) is a D flip-flop (DF1
3), Q output of (DF23) is input, and each flip-flop latches the completion signal sent from the flash device by bit b2. Therefore, the AND circuit (AG49) becomes "High" when both flash devices are in the full state, and this signal becomes the full signal shown by bit b11 in Table 1. When the terminal (f12) of the mode discrimination circuit (TIC) becomes "High", the AND circuit (AG39) becomes active, and the output signal of the output (α5) of the OR circuit (OR53) is output to the line (l2). It The OR circuit (OR53) receives the outputs of the D flip-flops (DF15) and (DF25) as inputs, and the flip-flops (DF15) and (DF25) latch the FDC signal at the bit b3 from the respective flash devices. Therefore, when at least one of the flash devices outputs the FDC signal at bit b3, the output of the OR circuit (OR53) becomes "High", which is inverted to "Low" and output to the line (l2). This signal is F of bit b12 in Table 1.
It becomes a DC signal. Mode discrimination circuit (TIC) terminal (f13),
Line (l2) when (f14) and (f15) become "High"
Remains "Low", which is a spare bit as shown by bits b13, b14, b15 in Table 1.

The mounting signal is input from the line (l12), and the Q output (α1) of the D flip-flop (DF19) becomes “High”,
If the mounting signal is not input from the line (l2) and the Q output of the D flip-flop (DF11) is "Low", the output of the AND circuit (AG51) becomes "High" and the AND circuit (A
G19) becomes active. First, when the terminal (f8) of the mode discrimination circuit (TIC) is "High", this signal is directly OR circuit (OR45), AND circuit (AG19), OR circuit (OR43),
It is output from (OR41) and output to line (l2). This is the mounting signal for bit b8. When the terminal (f9) becomes "High", the Q output (α8) of the D flip-flop (DF27)
Is output from the AND circuit (AG27). This signal is the discrimination signal of bit b5, and this signal is output to the line (l2) and becomes the discrimination signal of bit b9. Terminal (f10) is “Hig
When it becomes h ", the Q output of the D flip-flop (DF21) (α
4) is output from the AND circuit (AG27). This signal is "Low" when the flash unit mounted on the line (l12) side is in the parent-child emission mode, and is "High" when it is in the single-lamp emission mode. This signal is
The terminal (f10) of the mode discrimination circuit (TIC) is output to the line (l2) at the timing of "High", and the sequential light emission mode signal shown by bit b10 in Table 1 is obtained. When the terminal (f11) of the mode discrimination circuit (TIC) becomes "High", the AND circuit (A
From the G29), the Q output of the D flip-flop (DF23) (α
3) is output. This signal is the completion signal bit b2 from the line (l12), and the terminal (f11) is output to the line (l2) at the "High" timing to become the completion signal of the bit b11 shown in Table 1. . When the terminal (f12) of the mode discrimination circuit (TIC) becomes "High", the D flip-flop (DF25)
Q output (α7) is output from the AND circuit (AG31). This flip-flop (DF25) is an FDC signal input from the line (l12) by bit b12, and this signal is input to the line (l2) at the timing when the terminal (f12) of the mode discrimination circuit (TIC) becomes "High". ), It becomes the FDC signal of bit b12. While the mode discrimination circuit (TIC) terminals (f13), (f14), and (f15) are "High", the line (l
2) is "Low" and is a spare bit.

In CF mode, the mode discrimination circuit (TIC) pin (CF)
Becomes high, the NOR circuit (NO11) outputs a low signal and the AND circuits (AG2) and (AG1) are disabled. ) Becomes conductive or non-conductive, and the signal from the line (l2) is output from the output (r21) of the inverter (IN27). Then, the AND circuit (AG53) becomes active when the terminal (CF) becomes "High", and the terminal (r2
Signal from 1) is AND circuit (AG53), OR circuit (OR5
1), AND circuit (AG64), (AG65), transistor (B
It is output to the line (l12) via T65) and (BT67).
Therefore, the data from the camera body is output from the line (l2) to the line (l12) via the flash controller and read by the flash device.

In the ES mode, if the mounting signal is not latched in the D flip-flop (DF19), the output (α3) becomes “Hig
Since the terminal (ES) becomes "High" at h ", the AND circuit (AG1
3) output is “High”, NOR circuit (NO11) output is “Low”
Then, the transistors (BT55) and (BT57) are in the non-conducting state. Q output of D flip-flop (DF19) (α
If (1) is latching the mounting signal, the terminal (ES) is "Hi".
When it goes to gh ", the AND circuit (AG23) becomes active. Therefore, the signal from the flash device that is input to the line (l12) is input through the transistor (BT69) inverter (IN31) and the terminal (r22). This signal is output from the AND circuit (AG23) and output to the line (l2), so that the integral control signal synchronized with the light emission output from the flash device to the line (l12) is output. It is output to line (l2) via the flash controller.

Output of the AND circuit (AG45) (α
0) becomes "High", and the AND circuit (AG11) becomes active. Then, when the X contact (Sx) of the camera body is closed and the line (l1) becomes "Low", the transistor (BT5
9) becomes conductive and the terminal (r1) becomes "High". Since the flip-flop (FF23) is in the reset state at this point, the output of the AND circuit (AG11) becomes "High" when the terminal (r1) becomes "High", and the reset state of the counter (CO11) is released. Counter (CO11) is oscillator (PG)
The clock pulse (φ3) from is counted. Then, when the X contact (Sx) is closed and 6 msec has elapsed, the terminal (re) becomes "High" and the flip-flop (FF23) is set. If both flash devices are fully charged and the terminal (α2) is "High", the output of the AND circuit (AG88) becomes "High", the transistor (BT71) becomes conductive, and the line (l21) becomes "Low". As a result, the flash device (III) shown in FIG. 1 emits light. That is, the flash unit (I) emits light, and then (II) emits light to obtain proper exposure, and then the flash unit (III) emits light. When the flip-flop (FF23) is set, the output of the AND circuit (AG11) becomes "Low" and the counter (CO
11) is reset. Then, the X contact (Sx) is opened and the transistor (BT59) becomes non-conductive, and the terminal (r
When 1) falls to “Low”, the one-shot circuit (OS1
7) A pulse is output from the flip-flop (FF23)
Is reset and returns to the initial state.

When in multi-light mode, the flash unit will use bits b8 to b15
However, if both flash units are fully charged as described above, the flash controller outputs "Hi
gh ", if at least one is not full, output a" Low "signal to line (l2) by bit (b11). And this signal is read by the camera body as a full signal, but in the flash device Is also read by the flip-flop (FF2) and it is determined whether or not to emit light.
In addition, the output of the AND circuit (AG86) outputs "Hig" when it is determined that both flash units are directly connected to the flash controller in the multi-flash mode.
When it becomes "h" and the terminal (f11) becomes "High", the outputs of the AND circuit (AG92) and OR circuit (OR72) become "High".
This signal is output to the line (l12) and sends a signal capable of emitting light to the flash device. On the other hand, if at least one of the flash units is not fully charged, the AND circuit (AG86)
The output of is "Low", so the signal of "Low" is line (l12)
To the flash device, indicating that it should not fire. When the multi-light mode is not in effect, the output of the inverter (IN50) becomes "High", the flash device connected to the controller is fully charged, and if the terminal (α9) is "High", the terminal (f11) becomes "High". When the output of the AND circuit (Ag90) becomes "High", the output of the AND circuit (AG90) becomes "High". Therefore, this "High" signal is output to the line (l12) via the OR circuits (OR72) and (OR51), and is read by the flash device to enable the flash device to emit light. On the other hand, if the flash device is not in the full state, the signal "Low" is latched in the D flip-flop (DF23), and the terminal (α9) is "Low", the line (when the terminal (f11) becomes "High" ( A low signal is output to l12), and the flash device reads this signal and cannot emit light.

The output of the NOR circuit (NO13) is terminals (FC), (CF), (ES)
Is "Low", that is, it becomes "High" in the waiting mode. And, if the flash ground is not installed on the line (l12) side and the terminal (α3) is "High", the output of the AND circuit (AG15) becomes "High" and the NOR circuit (NO11).
Output becomes "Low", and transistors (BT55), (BT5
Both 7) are non-conductive. On the other hand, if the flash unit is installed on the line (l12) side, the terminal (α1) is "High".
Then, the AND circuit (AG17) becomes active. Then, the fill signal input from the line (l12) by the bit b2 is latched in the D flip-flop (DF23) and the terminal (α9)
If is "High", the AND circuit (AG17) is "Hig" during the waiting state.
Therefore, when the flash device on the line (l12) side outputs a charging completion signal, the controller outputs a "High" signal to the line (l2) during the waiting state.

Figure 19 shows the flash control unit (FTC1) of the parent and child strobes (Figure 11).
It is a modified example of. In the first light emission mode, the terminal (O13) becomes "High" and the OR circuits (OR14), (OR16), (OR1
The output of 2) becomes "High", and the AND circuits (AN52), (AN
54) and (AN62) become active. Therefore, the signal that the flip-flop (FF17) becomes "High" for 2.5 msec when the X contact (Sx) is closed is output from the AND circuits (AN52) and (AN54) and from the OR circuits (OR22) and (OR24). Light emitting part (FL
O1), (FLO2), and both emit light at the same time. Then, in the automatic light control mode, a light emission stop signal from the terminal (p3) is output from the AND circuits (AN66) and (AN68), and the two light emitting units stop light emission at the same time. Also, the FDC display circuit (I
The flip-flop (FF17) is X for the emission stop signal to NF).
The signal that becomes “High” for 2.5 msec from the time 3.5 msec has elapsed after the contact (Sx) was closed is the AND circuit (AN6
2), is output from the OR circuit (OR26), and the terminal (p
3) The light emission stop signal input from the AND circuit (AN7
0) to the FDC display circuit (INF). In addition,
If it is not in the automatic light control mode, the light emission part (FLO2) receives the light emission stop signal from the one-shot circuit (OS11).
64), sent through the OR circuit (OR28) and emits light up to the set light emission amount, but is not transmitted to the light emitting unit (FLO1) and emits all light.

In the post-emission mode, the terminal (O12) becomes "High" and the OR circuit (OR18) and (OR12) become "High".
N58), (AN60), (AN62) become active. Therefore, when the flip-flop (FF19) is set, two light emitting parts emit light at the same time, and both light emission is stopped by the light emission stop signal input to the terminal (p3) during this light emission, and this light emission stop signal is displayed by FDC. Sent to the circuit. The terminal (O10) becomes "High" and the OR circuits (OR14) and (OR16) become "High" in the simultaneous flash mode and the single flash mode (AN5
4), (AN56) becomes active. Therefore, when the flip-flop (FF ₁₇ ) is set, the two light emitting parts emit light at the same time, and the light emission of both light emitting parts is stopped based on the light emission stop signal input to the terminal (p ₃ ) during light emission. Together with FD
This light emission stop signal is also input to the C display circuit (INF).

In the parent-child emission mode, the terminal (O ₁₁ ) becomes “High”, the output of the OR circuits (OR ₁₆ ), (OR ₁₈ ), and (OR ₁₂ ) becomes “High”, and the AND circuit (AN ₅₂ ), (AN ₆₀ ), (A
N ₆₂ ) becomes active. First, when the flip-flop (FF17) is set, the light emitting unit (FLO2) starts emitting light, and during this period, the light emitting unit (FLO2) stops emitting light by the light emission stop signal input from the terminal (p3). Next, when the flip-flop (FF19) is set, the light emission part (FLO1) starts to emit light, and the light emission stop signal that is input during this time stops the light emission of the light emission part (FLO1). Is FD
Sent to the C display circuit (INF).

In the case of this modified example, both light emitting units emit light at the same time except in the parent-child light emitting mode, and therefore the interlocking range needs to be displayed based on the total amount of light emitted from both light emitting units.

The flash photographing system to which the present invention is applied has been described above. Next, a modified example of this system will be described. When shooting multiple flashes, when one flash unit is in the automatic light control mode and the other is in the manual setting mode, the flash unit in the automatic light control mode and the camera body display FDC, but The FDC display is not displayed on the flash device. In order to prevent this, the following modifications are possible.

1. Sequential flash mode (“01”, “10”) and simultaneous flash mode (“11”) signal bits b6 and b7
Even if it is in the manual setting mode, it will be in the automatic light control mode.
That is, if multiple lights are emitted, the manual setting mode is prohibited.

2. First, using bits b4 and b5 that are spares, bit b
At 4 the flash device outputs a signal indicating the automatic light control mode or the manual setting mode, and the flash controller reads it. Then, the flash controller determines that multiple flashes are being emitted, and if only one of the flash units is in the manual setting mode, an inhibit signal is sent to the flash unit in the manual setting mode with bit b15. send. Then, the flash device that has read this prohibition signal enters the automatic light control mode. That is, when multiple lights are emitted, only one is prohibited from being in the manual setting mode, and both are allowed to be in the automatic light control mode or the manual setting mode.

3. The flash controller outputs the FDC signal at bit b15 when the FDC signal is input from both flash devices in the case of multi-flash emission.

Further, it is determined that the camera main body (V) has attached all the signals of "High" as the data from the flash, that is, the flash device of the conventional type which does not have the function suitable for the system of the present embodiment. With the camera body, the display and exposure control for flash photography may not be performed but the display and exposure control for natural light photography may be performed, so that a flash device that does not conform to this system may not be used.

Or, if the flash unit reads all "High" signals, the exposure time is fixed at 1/60 sec and the aperture value is fixed at F5.6 regardless of the mode of the camera body, and only the minimum flash shooting is guaranteed. You may do it.

In addition to this, the signal of whether or not each flash unit should emit light in the fully charged state is transferred to the camera body in the release state, and the terminal (ES) of the mode discrimination circuit (TIC) is set to "Hig".
When "h" is reached, a timing signal for outputting a fill signal and a read timing signal are produced by each flash device and the controller, and whether to emit light based on the read fill signal based on the timing signal The decision may be made.

In the above embodiment, the power-on reset operation when the power is turned on is omitted for the sake of simplicity of the description and the drawings, but those skilled in the art can easily add it.

Effect According to the present invention as described above, even if the photographer accidentally takes a picture with the camera in the automatic exposure control mode while keeping the flash apparatus in the manual adjustment flash mode, the flash apparatus is automatically dimmed and the photographer It can cover erroneous operation.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of a flash photography system to which the present invention is applied, FIG. 2 is a flow chart for explaining the operation of the microcomputer (MC1) in FIG. 1, and FIG.
FIG. 4 is a flow chart showing a concrete example of the flash state display set in step # 38 of FIG. 2, FIG. 4 is a flow chart showing the operation for the stationary light calculation I of step # 41 in FIG. 2, and FIG. Step # 2 in Figure 2
FIG. 6 is a flow chart showing the operation for the flash light calculation of 42, FIG. 6 is a flow chart showing the operation of the steady light calculation II and the flash light calculation II in steps # 43 and # 44 of FIG. 2, and FIG. Input / Output Controller (IOC)
FIG. 8 is a circuit diagram showing a concrete example of the light emission amount control circuit (FST) of FIG. 1, and FIG. 9 is a control circuit in the flash unit (I) of FIG. FL
FIG. 10 is a circuit diagram showing a concrete example of the mode discrimination circuit (TIC) in FIG. 9, and FIG. 11 is a concrete example of the light emission amount control circuit (FTC1) in FIG. 12 is a circuit diagram showing a concrete example of the dimming completion display circuit (INF) shown in FIG. 9, and FIGS. 13 and 14 are diagrams for explaining the operation of the microcomputer (MC2) shown in FIG. Flowchart for the 15th
FIG. 16 is a circuit diagram showing a specific example of main parts of the control circuits (FLC2) and (FLC3) in the flash units (II) and (III) of FIG. 1, and FIG. 16 is a light emission control circuit (FTC2) of FIG. FIG. 17 is a circuit diagram showing a specific example of the main part of FIG.
FIG. 18 shows the first part of a flowchart showing the main part of the operation of 3).
FIG. 19 is a circuit diagram showing a specific example of the internal circuit (CNC) of the flash controller shown in FIG. V: Camera body, I, II, III: Flash device, IV: Flash controller, LM: Photometric circuit, FST: Flash emission control circuit, IOC: Input / output control circuit, FLC1, FLC2, FLC3: Control circuit, FLO1, FLO2 , FLO3, FLO4: Light emitting part, C1, C2, C
3, C4: Main capacitor, CHD1, CHD2, CHD3, CHD4: Charge completion detection circuit, MC1, MC2, MC3: Microcomputer, l1: Synchro switch closing signal transmission line, l2: Data transfer line, l3: Clock pulse transmission Line, l4: ground line, TIC: mode discrimination circuit,

Front page continued (72) Inventor Takanobu Takamaki 2-30 Azuchi-cho, Higashi-ku, Osaka City, Osaka Prefecture Osaka International Building Minolta Camera Co., Ltd. Minamata Camera Co., Ltd. , B2)

Claims (5)

[Claims] 1. A camera and a flash device built in or connected to the camera. The camera has a first mode for automatically controlling an aperture value and a shutter speed, and a second shutter speed automatic control based on the aperture value. Third mode for automatic aperture value control based on shutter speed and mode
Exposure control means capable of exposure control in the fourth mode in which the aperture value and shutter speed are manually determined, selection means for selecting each of the above modes, and exposure control mode selected by the selection means The flash device includes a light emitting device, a light control device for controlling the light emission amount of the light emitting device, and a light control device for controlling the light emission amount of the light emitting device. Setting means for selecting an automatic mode for performing the above and a manual mode for not performing control by the dimming means, and when the identification signal identifies that the first to third modes are selected in the camera, A flash photography system comprising a light emission mode control means for operating the light control means even when the manual mode is selected in the flash device. 2. The flash device includes means for generating a ready signal indicating that the flash device is ready to emit light, and the exposure control means of the camera is responsive to the ready signal for exposure control suitable for flash photography. The flash photographing system according to claim 1, further comprising a flash exposure unit for performing the above. 3. The camera, when the shutter is operating, measures the light of a subject that has passed through the taking lens and is reflected by the film surface, and produces a light output corresponding to the light measurement value; and the output of the light measurement means is integrated, and Integration means for outputting a light emission stop signal for stopping light emission to the flash device when the integrated value reaches a predetermined level, and the dimming means of the flash device responds to the light emission stop signal of the light emitting device. Patent with the light emission stop means for stopping the light emission, and the light emission mode control means for the flash device having the signal transmission control means for permitting or blocking the transmission of the light emission stop signal to the light emission stop means according to the mode of the camera and the flash device. The flash photographing system according to claim 2. 4. A first control for automatically controlling an aperture value and a shutter speed.
Mode, a second mode in which automatic shutter speed control is performed based on the aperture value, a third mode in which automatic aperture value control is performed based on the shutter speed, and a fourth mode in which the aperture value and shutter speed are manually determined. A flash device attachable to a camera capable of controlling exposure and outputting an identification signal for identifying which of the exposure control modes is used. The flash device includes a light emitting device and a control for controlling a light emission amount of the light emitting device. A light means, a setting means for selecting an automatic mode in which the light control is performed by the light control means, and a manual mode in which the control by the light control means is not performed, and the first to third modes in the camera are selected by the identification signal. Flash device including a light emission mode control means for operating the dimming means even when the manual mode is selected by the setting means when it is identified that the flash mode is set. . 5. The light control means comprises light emission stopping means for stopping light emission of the light emitting device in response to a light emission stop signal from the camera,
5. The flash device according to claim 4, wherein the light emission mode control means includes signal transmission control means for permitting or blocking transmission of the light emission stop signal to the light emission stop means according to the mode of the camera and the flash device.