JPH07169191A - Waveform equalizer - Google Patents

Abstract

(57) [Abstract] [Purpose] To respond to DC fluctuations, prevent erroneous updates when updating coefficients by automatic equalization, and set the data discrimination threshold optimally to perform highly reliable information reproduction. To provide a waveform equalizing device. [Structure] Two equalizers having comparators 104 and 105 for equalization error detection for reproduction data "0""1" and controlled to an average amplitude value of reproduction data "0""1" by automatic equalization processing. The intermediate value of the error detection threshold value is updated value calculation circuit 602
And the data discrimination threshold value. Further, the convergence determination circuit 601 detects the convergence of the coefficient and the threshold and the DC fluctuation and the reproduction characteristic fluctuation based on the equalization error evaluation value, and when the DC fluctuation occurs, the coefficient updating operation in the update value calculation circuit 602 is stopped.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention increases the aperture ratio of an eye pattern by always performing optimum waveform equalization on a reproduction signal whose reliability in data discrimination is low due to intersymbol interference. The present invention relates to a waveform equalization device that enables highly reliable information reproduction by always setting a data discrimination threshold at the center of the eye pattern opening.

[0002]

2. Description of the Related Art When transmitting information by wire or wirelessly,
If the transmitted signal cannot be obtained correctly at the receiving side, distortion and data errors will occur. Actually, there are some characteristics in the transmission line, not limited to wired / wireless. Waveform equalization is to return a signal changed by these transmission lines to a signal suitable for a receiver.

Broadly speaking, the waveform equalization technique is a technique for compensating frequency characteristics, and is a main technique in an information recording / reproducing apparatus, and is an essential technique for achieving high-density recording and improving reliability.

Most of the waveform equalizers are so-called fixed equalization systems in which the tap coefficient is set in advance in accordance with the recording / reproducing characteristics in both analog and digital, as long as it is limited to the recording device. On the other hand, if the automatic equalization method is introduced, (1) initial adjustment becomes simple.

(2) The reliability during compatible reproduction can be improved.

(3) Since it is not necessary to consider a margin for variations in reproduction characteristics, high density can be achieved.

The advantage of

Although there are many kinds of algorithms for performing automatic equalization, the zero forcing (ZF) algorithm is actually used for processing a high-speed data sequence such as a video signal. . As an automatic equalizer using the ZF algorithm, as shown in FIG. 44, No 6, pp. 728-
An automatic equalizer described in 735 (1990) is known.

In the automatic equalizer shown in FIG. 12, a waveform equalized reproduction is performed by an equalizer of a three-tap transversal filter which includes delay lines 1201 and 1202, gain adjusters 1203 and 1204, and an adder 1205. Signal y
_The reproduced data a _k ′ is _obtained by comparing _k with the data discrimination threshold SL in the comparator 1. In the comparator 2, the reproduction signal y _k and the equalization error detection threshold e
The equalization error e _k is detected by comparing s. The calculator 1210 obtains an equalization error evaluation value from the reproduced data a _k 'and the equalization error e _k, and equalizes the gain (equalization coefficient) of the gain adjuster of the equalizer with the obtained equalization error evaluation value. The error detection threshold value es is updated to optimize the waveform equalization characteristic of the equalizer.

[0010]

However, in the above-described automatic equalizer, since the data discrimination threshold value SL for discriminating reproduced data is fixed, when a DC fluctuation occurs in the reproduced signal, the eye pattern Since the center fluctuates, the data discrimination threshold SL deviates from the optimum value for data discrimination. If the data discrimination threshold SL is not optimally set, the probability that a code error will occur becomes high, and reliable information reproduction cannot be performed.

The condition for the coefficient of the equalizer based on the ZF algorithm to converge to the coefficient that maximizes the eye pattern aperture ratio is that there is no deterioration of the frequency characteristic such as closing of the eye pattern. The occurrence of a code error is equivalent to the eye pattern being locally closed. Therefore, the equalization error detection threshold / equalization coefficient updated using the equalization error evaluation value obtained at the time when the code error occurs is not the coefficient / threshold that maximizes the eye pattern aperture ratio. It causes an erroneous update. The false update due to this false evaluation value further increases the probability that a code error will occur, so that the false update is repeated, the equalization coefficient diverges without converging, intersymbol interference increases, and highly reliable information is obtained. Playback may not be possible. Even when the equalization coefficient converges, the number of updates until the equalization coefficient converges increases due to erroneous update. Since the data reproduced before the convergence of the equalization coefficient is not the optimum equalization, the number of updates until the coefficient convergence increases, so that reliable information reproduction cannot be performed.

The object of the present invention is to solve the above problems,
Corresponding to the DC fluctuation of the reproduced signal, by always setting the data discrimination threshold to the optimum value, it is possible to prevent erroneous updating at the time of coefficient updating by automatic equalization, and to perform optimal waveform equalization by automatic equalization to ensure reliability An object of the present invention is to provide a waveform equalization device for reproducing information with high property.

[0013]

In order to achieve the above object, the present invention provides a waveform equalizing means capable of changing the equalization coefficient for equalizing the waveform of an input signal, and a waveform by the waveform equalizing means. The data discriminating means for discriminating the equalized reproduced signal into the binarized data by the data discriminating threshold value SL and the binarized data discriminated by the data discriminating means are "
In the case of 1 "and" 0 ", two equalization error detecting means for detecting the equalization error, the binarized data discriminated by the data discriminating means and the equalization error detecting means are detected. The equalization error evaluation value calculation means for calculating the equalization error evaluation value by the equalization error, and the equalization coefficient of the waveform equalization means by the equalization error evaluation value calculated by the equalization error evaluation value calculation means. The data discriminating threshold value SL of the data discriminating means and the equalization error of the equalization error detecting means are detected by the coefficient updating means for updating and the equalization error evaluation value calculated by the equalization error evaluation value calculating means. Threshold value updating means for updating the threshold value es ± and the equalization error evaluation value calculated by the equalization error evaluation value calculation means are used to determine the convergence of the equalization coefficient and the equalization error detection threshold value. Convergence determination means for And a coefficient update control means for controlling the coefficient update operation in the unit.

[0014]

According to the present invention, the equalization coefficient of the waveform equalization means capable of changing the equalization coefficient is determined by the discrimination data output from the data discrimination means and the equalization error values output from the two equalization error detection means. The equalization error evaluation value is calculated by the equalization error evaluation value calculation means, and the equalization coefficient, the data discrimination threshold of the data discrimination means, and the two equalization error detection thresholds are updated by this equalization error evaluation value. To do.

Further, in the present invention, the discrimination data is "1", "
For the case of 0 ", the equalization error detection thresholds are individually provided, and the respective equalization error detection thresholds are set to the amplitudes of the reproduced signal amplitude after equalization when the discrimination data are" 1 "and" 0 ". Therefore, when the DC fluctuation occurs in the reproduced signal, the DC fluctuation is detected by the change of the equalization error evaluation value,
The equalization error detection threshold value can be controlled to the average value of the equalized reproduction signal amplitude after the DC fluctuation. Further, since the intermediate value of the respective equalization error detection thresholds is used as the data discrimination threshold, the data discrimination threshold is always equal to the eye pattern of the reproduction signal after equalization even with respect to the DC fluctuation during the data reproduction. It is set at the center of the opening.

On the other hand, the coefficient updating means updates the coefficient only after the equalization error detection threshold has converged. Therefore, even if a DC fluctuation occurs during coefficient updating, it is possible to prevent erroneous coefficient updating due to code detection error.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which a waveform equalizing device according to the present invention is applied to an information reproducing device will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of a waveform equalizer according to the present invention. In FIG. 1, 10
1 is an A / D converter, 102 is a digital equalizer, and 103
Is a data discriminating comparator, 104 and 105 are equalization error detecting comparators, 106 is an equalization error evaluation value calculation circuit, 107 is an update value calculation circuit, 109 is an input terminal, and 110 is an output terminal.

A reproduction signal reproduced from a recording medium (not shown) is input to the automatic equalizer from the input terminal 109.
The inputted reproduction signal is converted into n-bit (n is a positive integer of 1 or more) digital data by the A / D converter 101. At the start of information reproduction (at the start of automatic equalization), the reproduction signal converted into digital data is the digital equalizer 10
2, waveform equalization is performed using preset equalization coefficients of initial values.

FIG. 2 is a circuit block diagram showing a specific example of the digital equalizer 102. In FIG. 2, the latch circuits 201 and 202, the multipliers 203 and 204, and the adder 205 constitute a 3-tap digital transversal filter. Further, the tap coefficient (equalization coefficient) of each of the multipliers 203 and 204 can be changed by inputting the coefficient from the outside, so that the equalization characteristic can be changed.

In this embodiment, ZF algorithm is used for automatic equalization. Assuming that the impulse response at the output terminal of the digital equalizer 102 is h (t), the sum D of absolute values of intersymbol interference of the reproduced signal after equalization is given by the following equation (Equation 1).

[0022]

[Equation 1]

The ZF algorithm is an algorithm for controlling the tap coefficient C _j (j is a tap number) of the transversal filter of the digital equalizer 102 so that the value of D becomes minimum, and this is reproduced after equalization. It is equivalent to maximizing the aperture ratio of the signal eye pattern.

The digital reproduction signal y _k subjected to the equalization processing by the digital equalizer 102 is the data discrimination comparator 1
03, the equalization error detecting comparators 104 and 105. The data discriminating comparator 103 compares the input equalized digital reproduction signal y _k with the data discriminating threshold value SL, and “1” when y _k ≧ SL and “1” when y _k <SL ”.
The binary digital data a _k ′ of 0 ″ is output to the output terminal 110 and the equalization error evaluation value calculation circuit 106. Further, the equalized digital reproduction signal y _k is equalized error detection comparator 10.
4, 105 are input. Equalization error detection comparator 104
The equalized digital reproduction signal y _k input to is compared with the equalization error detection threshold value es + and the equalization error e _k + is output to the equalization error evaluation value calculation circuit 106. Equalized digital reproduction signal y input to the equalization error detection comparator 105
_k is compared with the equalization error detection threshold es− and the equalization error e _k− is output to the equalization error evaluation value calculation circuit 106.

Data a recorded on a recording medium (not shown)
_k is a binary signal and takes "1" or "0". Here, for convenience of the following, "1" is associated with +1 and "0" is associated with -1, and a _k ε {+1, -1}. At that time, the equalization error evaluation value H _j is given by the following equation (Equation 2).

[0026]

[Equation 2]

Here, e _k is an equalization error, and m is an evaluation value of 1
This is the number of additions required to obtain the number of times. In Equation (2), the first half gives an equalization error evaluation value when a _k is +1 and the second half is when a _k is −1.

Using the a _k ′ and e _k ± output from the data discrimination comparator 103 and the equalization error detection comparators 104 and 105, the equalization error evaluation value calculation circuit 106 determines the equalization error evaluation value. Calculate and output H0 ± and H ± 1. The equalization error evaluation value calculation circuit 106 uses the equalized digital reproduction signal y _k , the data discrimination threshold SL and the equalization error detection threshold es ± to output the equalization output from the comparators 103, 104 and 105. The error e _k ± and the binary digital data a _k '(here,
For convenience, "1" corresponds to +1 and "0" corresponds to -1,
Let a _k ', e _k ± ε {+1, -1}. ), The equalization error evaluation value is calculated by the equation (Equation 2) for obtaining the equalization error evaluation value H _j . However, since it is not possible to know _ak which is the recorded data information in advance, _ak 'which is an estimated value of the data a _k is used to calculate each equalization error evaluation value (Equation 3).
Calculate using.

[0029]

[Equation 3]

The equalization error evaluation value calculation circuit 106 calculates the equalization error evaluation value as shown in FIG. In FIG. 3, the number of additions m required to obtain the evaluation value once is 7, but the actual value of m may be the error of the equalization error evaluation value due to the code detection error due to the C / N of the reproduced signal. , A value that does not affect automatic equalization is set. The equalization error evaluation value calculation circuit 106 outputs the equalization error evaluation values H0 ±, H ± 1 for each m bits of reproduced data.

The calculated equalization error evaluation value H _j (where j
If ≠ 0) is positive, it means that equalization is insufficient and the tap coefficient C _j (where j ≠ 0) is set to a small amount (step width).
To increase the equalization amount. When the equalization error evaluation value H _j (where j ≠ 0) is 0, the tap coefficient C _j (where j ≠ 0) is not increased or decreased because there is no excess or deficiency of equalization. Further, if the equalization error evaluation value H _j (where j ≠ 0) is negative, it means that overequalization is performed and the tap coefficient C _j (where j ≠ 0).
Repeat the operation of decreasing ≠ 0) by a very small amount. on the other hand,
For the equalization error evaluation value H0 ±, the equalization error evaluation value H0
The equalization error detection threshold es ± is sequentially increased or decreased by a minute amount according to the plus or minus of ±, and the equalization error detection threshold es ± is updated,
The absolute value of the equalization error evaluation value H0 is minimized.
By repeating such processing, the intersymbol interference amount D shown in the equation (Equation 1) becomes the minimum. That is, optimum waveform equalization is performed that maximizes the aperture ratio of the eye pattern.

Using the equalization error evaluation values H0 ± and H ± 1 calculated by the equalization error evaluation value calculation circuit 106, the update value calculation circuit 107 uses a threshold value and an equalization coefficient used for automatic equalization. To update. FIG. 4 is a circuit block diagram showing a specific example of the update value calculation circuit 107. In FIG. 4, 401, 4
07, 412, 418 are input terminals, 402, 408, 4
13, 419 are comparators for comparing the positive and negative of the input equalization error evaluation values, 403, 409, 414, 420 are registers for holding the coefficient / threshold values before updating, and 405 is A register for holding the update step width Δs when updating the threshold value, 416 is a register for holding the update step width Δc when updating the equalization coefficient, and 404, 410, 415, 421 are comparators. 40
2, 408, 413, 419 results in register 4
03, 409, 414, 420 adder / subtractor 423 for adding / subtracting the step width from the coefficient / threshold value before update held by 403 is a data discriminating threshold value for calculating the data discriminating threshold value SL. Calculation circuit, 406, 411, 4
Reference numerals 17, 422 and 424 are output terminals.

In the figure, the value of the equalization error evaluation value H + 1 input from the input terminal 412 is compared by the comparator 413. If the value is positive, before the equalization coefficient C ₁ held in the register 414 is updated. Value (initial value at the start of reproduction) to the step width Δc held in the register 416.
Add with. When the value of the equalization error evaluation value H + 1 is 0, the value before updating the equalization coefficient C ₁ (initial value at the start of reproduction)
Is held in the register 414, and the addition / subtraction processing in the adder / subtractor 415 is not performed. When the equalization error evaluation value H + 1 is negative, the equalization coefficient C ₁ held in the register 414 is
Of the register 41 to the value before update (initial value at the start of reproduction).
The step width Δc held in 6 is subtracted by the adder / subtractor 415. Similarly, the equalization coefficient C _-1 is also updated with the equalization error evaluation value H-1. In this way, the equalization coefficients C ₁ , C
By continuing to update _-1 , the equalization coefficients C ₁ and C _-1 are
The intersymbol interference amount D of (Equation 1) converges to a value that minimizes (maximum eye pattern aperture ratio), and optimal equalization that suppresses intersymbol interference can be performed.

In FIG. 4, the value of the equalization error evaluation value H0 + input from the input terminal 401 is compared with the comparator 402.
If it is positive, the step width Δs held in the register 405 is added to or subtracted from the value before the update of the equalization error detection threshold es + held in the register 403 (initial value at the start of reproduction). It is added by the device 404. Equalization error evaluation value H0
When the value of + is 0, the value before update of the equalization error detection threshold value es + (initial value at the start of reproduction) is held in the register 403, and the addition / subtraction processing in the adder / subtractor 404 is not performed. When the value of the equalization error evaluation value H0 + is negative, the equalization error detection threshold value es + held in the register 403 is held in the register 405 at the value before update (the initial value at the start of reproduction). The step width Δs is subtracted by the adder / subtractor 404. In this way, by continuing to update the equalization error detection threshold value es + with the equalization error evaluation value H0 +, the equalization error detection threshold value es + is set so that the value of the equalization error evaluation value H0 + approaches 0. Controlled by. Similarly, by continuing to update the equalization error detection threshold value es− with the equalization error evaluation value H0−, the equalization error detection threshold value es− becomes 0. Controlled to approach. Further, the data discrimination threshold value calculation circuit 423 is similar to that shown in FIG.
With the configuration as shown in, the input equalization error detection thresholds es + and es− are added by the adder 501, and the sum is halved in the divider 502 to reduce the equalized reproduction signal amplitude. Calculates the intermediate value and sets the data discrimination threshold SL
Output as.

The equalization error evaluation value H0 ± is +1 when the reproduction signal amplitude when the reproduction data is "1" and "0" is larger than the equalization error detection threshold es ±, and -1 when the reproduction signal amplitude is small. It is the total sum of m bits. That is, the equalization error evaluation value H0 ± represents whether the average of the reproduction signal amplitudes when the reproduction data is “1” or “0” is larger or smaller than the equalization error detection threshold es ±. Become. for that reason,
Controlling the equalization error evaluation value H0 ± to 0 means that the equalization error detection threshold value es ± is set to the average value of the reproduction signal amplitude when the reproduction data is “1” or “0”. To control. The data discrimination threshold SL is an intermediate value of the equalization error detection thresholds es ± and is set at the center of the reproduction signal amplitude, that is, the center of the eye pattern opening.

As described above, according to the first embodiment of the present invention, the equalization error detection threshold value is equal to the DC value even when a DC fluctuation occurs during data reproduction. The data discrimination threshold SL is always set at the center of the eye pattern opening because it is updated in response to fluctuations. In addition, since the equalization coefficient is controlled to the optimum equalization coefficient that maximizes the aperture ratio of the eye pattern by the automatic equalization processing, it is possible to always perform highly reliable information reproduction.

Next, a second embodiment of the waveform equalizer according to the present invention will be described with reference to the drawings. FIG. 6 is a block diagram showing a second embodiment of the present invention. In FIG. 6, 101 is an A / D converter, 102 is a digital equalizer, 103 is a data discrimination comparator, 104 and 105 are equalization error detection comparators, 106 is an equalization error evaluation value calculation circuit, and 601. Is a convergence determination circuit, 602 is an update value calculation circuit,
109 is an input terminal and 110 is an output terminal. The same parts as those in FIG. 1 are designated by the same reference numerals.

Next, the operation of the second embodiment will be described with reference to FIG. Digital equalizer 1 as in the first embodiment
The reproduced data a _k 'and the equalization error e _k ± are detected from the equalized digital reproduction signal y _k equalized by 02, and the equalization error evaluation value calculated by the equalization error evaluation value calculation circuit 106 is used. Performs automatic equalization processing. The equalization error evaluation value calculated by the equalization error evaluation value calculation circuit 106 is output to the convergence determination circuit 601 and the update value calculation circuit 602.

FIG. 7 is a circuit block diagram showing a specific example of the convergence determination circuit 601. In FIG. 7, 701 is a coefficient convergence determination circuit, 702 is an error detection threshold value convergence determination circuit, and 703 is a logic circuit. In the figure, the coefficient convergence judgment circuit 701 has an equalization error evaluation value H ± 1 and the error detection threshold value convergence judgment circuit 702 has an equalization error evaluation value H0 ±.
Are input respectively. FIG. 8 shows the coefficient convergence determination circuit 70.
1 is a circuit block diagram showing a specific example of No. 1. In FIG. 8, reference numerals 801 and 802 denote absolute value calculation circuits for obtaining the absolute value of the equalization error evaluation value, 803 and 804 denote comparators for comparing the absolute value of the equalization error evaluation value with a convergence determination reference value,
Reference numerals 805 and 806 are counters, 807 and 808 are decoders, and 809 is an AND circuit.

The determination of convergence at the equalization coefficient C _-1 will be described with reference to FIG. Equalization error evaluation value H-1 of equalization coefficient C _-1
Is the equalization error evaluation value H in the absolute value calculation circuit 801.
The absolute value of -1 is obtained. When the equalization coefficient converges, the equalization error evaluation value should be 0.
As shown in (1), the equalization difference evaluation value has a range around 0 even in the convergence value of the equalization coefficient depending on the fluctuation of the input signal and the data pattern when detecting the equalization error. Therefore, it is determined that the coefficient C ₋₁ has converged when the equalization error evaluation value is within a range of ± dv at which the coefficient is a convergence value continuously for a certain number of times cv (cv is a positive integer of 1 or more). The range ± dv of the equalization error evaluation value when the equalization coefficient is the convergence value is used as the reference value for the convergence determination.

A comparator 803 compares the absolute value of the equalization error evaluation value H-1 with the convergence judgment reference value dv. If the absolute value of the equalization error evaluation value is equal to or smaller than the convergence judgment reference value dv, the comparator 803.
Outputs High when Low is greater than or equal to the reference value. The counter 805, which is counted by the clock that rises every time the equalization error evaluation value is calculated, performs the counting operation without clearing the counter coefficient value when the comparator 803 is Low. The decoder 807 which decodes the count value of the counter 805 and outputs a signal outputs a Low signal until the counter count value reaches the number of times cv when it is determined that the count value has converged,
The equalization coefficient C _-1 signals that it has not converged. When the counter count value of the counter 805 reaches the number of times cv when it is determined that the value has converged, the decoder 807 outputs a High signal and detects the coefficient convergence. When the output of the decoder 807 is High, the counter 805 is in the HOLT state, and the counting operation is not performed even when the clock rises. On the other hand, the comparison result of the comparator 803 is Hig.
In the case of h, since the equalization error evaluation value is equal to or larger than the convergence determination reference value dv, it is determined that the equalization coefficient C ₋₁ has entered the reconvergence operation during the convergence or due to the variation of the reproduction characteristic, and the counter 805 is cleared. Therefore, the output of the decoder 807 becomes Low, indicating that the equalization coefficient C _-1 has not converged.
The convergence judgment of the equalization coefficient C _-1 is performed by the above operation, and the result of the convergence judgment can be known from the output of the decoder 807.

[0042] Similarly coefficient convergence determination circuit 701, the equalization coefficients equalization coefficients to the decoder 808 performs the convergence determination of C ₁ C ₁
The convergence judgment result of is output. AND the convergence determination results of the equalization coefficients C ₋₁ and C ₁ output from the decoders 807 and 808.
The logical product is obtained by the circuit 809, and the control signal CSc that becomes High is output only when the equalization coefficients C ₋₁ and C ₁ both converge.

Further, the error detection threshold value convergence judgment circuit 70.
2 has the same configuration and determines the convergence from the absolute value of the equalization error evaluation value H0 ±. When it is determined that the error detection threshold value has converged, the control signal CSe of High is output.
When it is determined that the error detection threshold value is deviating from the average value of the reproduction signal amplitude after the equalization of the reproduction data "1""0" during convergence or due to DC fluctuation,
The low control signal CSe is output.

The control signals CSc and CSe output from the convergence determination circuits 701 and 702 are input to the logic circuit 703. The logic circuit 703 receives the input control signals CSc and CS.
The control signal CS based on the truth table (Table 1) is output by e.

[0045]

[Table 1]

According to the truth table (Table 1), the control signal CSe
Is Low, that is, when the equalization error detection threshold value has not converged, the control signal CS becomes Low. When the control signal CSe is High, that is, when the equalization error detection threshold value is converged, when the control signal CSc is High and the equalization coefficient is converged, the control signal CS is Low.
On the other hand, when the control signal CSc is Low and CSe is High,
That is, the control signal CS becomes High only when the equalization error detection threshold value has converged and the equalization coefficient has not yet converged.

In FIG. 6, the equalization error evaluation value calculation circuit 1
Using the equalization error evaluation values H0 ±, H ± 1 calculated in 06, the update value calculation circuit 602 updates the threshold value and the equalization coefficient used for automatic equalization. FIG. 10 shows the update value calculation circuit 60.
2 is a circuit block diagram showing a specific example of No. 2; FIG. In FIG. 10, 1001 and 1002 are switches controlled by the control signal CS.

In the figure, when the control signal CS is High, the equalization error evaluation value H + input from the input terminal 412
The value of 1 is compared by the comparator 413, and when the value is positive, the value before the update of the equalization coefficient C ₁ held in the register 414,
The step width Δc held in the register 416 is added by the adder / subtractor 415. When the value of the equalization error evaluation value H + 1 is 0, the value of the equalization coefficient C ₁ before being updated is held in the register 414, and the adder / subtractor 415 does not perform addition / subtraction processing. When the value of the equalization error evaluation value H + 1 is negative, the step width Δc held in the register 416 is added to the value before the update of the equalization coefficient C ₁ held in the register 414 and the subtracter 4
Subtract at 15. Similarly, the equalization coefficient C _-1 is also updated with the equalization error evaluation value H-1. In this way, the equalization coefficients C _1, C _- by continuing to update the _1, equalization coefficients C _1,
C ₋₁ converges to a value that minimizes the intersymbol interference amount D of (Equation 1) (maximum eye pattern aperture ratio), and can perform optimal equalization while suppressing intersymbol interference.

However, when the control signal CS is Low,
The switches 1001 and 1002 are turned off, and the step width Δc held in the register 416 is added to the adder / subtractor 415.
The values of the equalization coefficients C ₁ and C _-1 are not updated because they are not supplied to the 421.

At the start of data reproduction, the equalization coefficient,
The equalization error detection threshold value is an initial value. Therefore, at the start of automatic equalization, the equalization coefficient and the equalization error detection threshold value are not converged values, so the control signal CS output from the convergence determination circuit 601 is Low, and the coefficient update operation is not performed. The update operation is performed only on the equalization error detection threshold value. After the equalization error detection threshold value converges at the initial value of the equalization coefficient, the control signal CS becomes High, and the coefficient updating operation starts. When DC fluctuation occurs in the reproduced signal in the convergence process due to coefficient update, the DC signal fluctuation causes the equalization error detection threshold value to deviate from the convergence value.
Becomes Low, and the coefficient updating operation is stopped. Therefore, even if a code error occurs due to DC fluctuation, the coefficient updating operation is not performed and the equalization coefficient is not erroneously updated.

After the equalization coefficient and the equalization error detection threshold have converged, the control signal CS becomes Low and the coefficient updating operation is stopped. However, even after the equalization coefficient and the equalization error detection threshold have converged, the equalization error detection threshold is constantly updated so that even if a DC fluctuation occurs, the equalization can be performed in response to the fluctuation. The error detection threshold is updated.

Further, in FIG. 10, as in the first embodiment, the data discrimination threshold SL calculated by the data discrimination threshold calculation circuit 423 is the center of the reproduced signal amplitude even when a DC fluctuation occurs. That is, it is set at the center of the opening of the eye pattern.

As described above, according to the second embodiment of the present invention, optimum waveform equalization can be performed by automatic equalization, and the equalization error detection threshold value is updated during data reproduction even after convergence. Therefore, even if a DC fluctuation occurs during data reproduction, the data discrimination threshold SL is always set at the center of the eye pattern opening, and highly reliable data reproduction can be performed. In addition, since the coefficient update operation is stopped after the coefficient has converged or when the equalization error detection threshold value has not converged, the coefficient update is performed even when DC fluctuation occurs during coefficient update. Can be prevented, and erroneous updating of the equalization coefficient due to an increase in the probability of occurrence of an error in the equalization error evaluation value can be prevented.

In the above description of the first and second embodiments, the coefficient is updated by automatic equalization from the time of data reproduction, but the recording format of the recording medium is as shown in FIG. If a recording format having a training signal area for converging the equalization coefficient prior to the data is used, optimum equalization can be performed from the beginning of the data to be reproduced, and highly reliable data reproduction can be performed. Also, in the embodiment, the number of taps of the equalizer is three, but
It goes without saying that the present invention can be applied even when the number of taps is further increased.

[0055]

As described above, according to the present invention, the automatic equalization processing controls the equalization coefficient to the optimum equalization coefficient that maximizes the aperture ratio of the eye pattern, thereby detecting the error used for automatic equalization. Threshold value es ± allows easy data discrimination threshold SL
Can be set to the center of the opening of the eye pattern. Moreover, since the error detection threshold value es ± is constantly updated,
Since the data discrimination threshold SL can always be set at the center of the opening of the eye pattern in response to the DC fluctuation during the data reproduction, highly reliable information reproduction can be performed. Even when the data discrimination threshold SL deviates from the center of the aperture of the eye pattern due to DC fluctuation during coefficient updating and the probability of occurrence of a code error increases, the coefficient updating operation is stopped to stop the coefficient due to a code detection error. It is possible to prevent erroneous update of.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a first embodiment of a waveform equalizer according to the present invention.

FIG. 2 is a circuit block diagram showing a specific example of a digital equalizer.

FIG. 3 is a diagram illustrating a process of calculating an equalization error evaluation value from a reproduction signal.

FIG. 4 is a circuit block diagram showing a specific example of an update value calculation circuit in FIG.

5 is a circuit block diagram showing a specific example of a data discrimination threshold value calculation circuit in FIG.

FIG. 6 is a circuit block diagram showing a second embodiment of the waveform equalizer according to the present invention.

7 is a circuit block diagram showing a specific example of a convergence determination circuit in FIG.

8 is a circuit block diagram showing a specific example of the coefficient convergence determination circuit in FIG.

FIG. 9 is a diagram showing a relationship between an equalization error evaluation value and an equalization coefficient.

10 is a circuit block diagram showing a specific example of an update value calculation circuit in FIG.

FIG. 11 is a diagram showing an example of a recording format having a training signal for converging a coefficient and a threshold value by automatic equalization prior to data.

FIG. 12 is a circuit block diagram showing a configuration of a conventional automatic equalizer using a ZF algorithm.

[Explanation of symbols]

 101 ... A / D converter, 102 ... Digital equalizer, 103 ... Data discrimination comparator, 104, 105 ... Equalization error detection comparator, 106 ... Equalization error evaluation value calculation circuit, 107, 602 ... Update Value calculation circuit, 601 ... Convergence determination circuit.

Claims (7)

[Claims] 1. A waveform equalizer for performing a waveform equalization process on a reproduced signal reproduced from a recording medium, and a data discriminating means for discriminating reproduced data from a reproduced signal waveform-equalized by the waveform equalizer. An equalization error detection means for detecting an equalization error from the reproduction signal waveform-equalized by the waveform equalization means, the reproduction data discriminated by the data discrimination means and the equalization error detection means. The equalization error evaluation value calculation means for calculating the equalization error evaluation value by the equalized error evaluation value, and the equalization error evaluation value calculated by the equalization error evaluation value calculation means, The automatic equalization processing has a coefficient updating means for updating the equalization coefficient, and a threshold updating means for updating the equalization error detection threshold used when the equalization error detecting means detects the equalization error. Automatic equalizer The first equalization error detecting means for detecting an equalization error when the reproduction data is "1" from the reproduction signal waveform-equalized by the waveform equalization means, and the reproduction data of "0". A second equalization error detection means for detecting the equalization error in the case, and using the equalization error evaluation value calculated by the equalization error evaluation value calculation means, the first and second A waveform equalizer, wherein two equalization error detection thresholds used when the equalization error detecting means detects an equalization error are updated by the threshold updating means. 2. The waveform equalizer according to claim 1, wherein the first and second equalization error detecting means equalize a data discrimination threshold value used when the data discriminating means discriminates data. An intermediate value between two equalization error detection thresholds used when detecting an error, and each time the two equalization error detection thresholds are updated by the threshold value updating means, a data discrimination threshold value is also set. A waveform equalizer characterized by updating. 3. The waveform equalizer according to claim 1, wherein the equalization error evaluation value calculated by the equalization error evaluation value calculation means is used to perform convergence judgment of the equalization coefficient and the threshold value. When the convergence determining unit determines that the equalization coefficient has converged, it has a convergence determining unit and a coefficient updating control unit that controls the coefficient updating operation of the coefficient updating unit based on the determination result of the convergence determining unit. A waveform equalizer, wherein the coefficient updating control means stops the coefficient updating operation of the coefficient updating means. 4. The waveform equalizing apparatus according to claim 3, wherein when the convergence determining means determines that the equalization error detection threshold has not converged, the coefficient updating control means updates the coefficient. A waveform equalizer characterized in that the coefficient updating operation of the means is stopped. 5. The waveform equalization circuit according to claim 3 or 4, wherein the convergence determination means determines that the equalization coefficient / threshold value has converged, and the coefficient update control means updates the coefficient of the coefficient update means. A waveform equalizing device characterized in that, even when the operation is stopped, the threshold updating operation by the threshold updating means continues the updating operation during data reproduction. 6. An information reproducing apparatus which obtains reproduction data by performing waveform equalization processing on a reproduction signal reproduced in time series from a recording medium by a waveform equalizing apparatus, and as the waveform equalizing apparatus, claim An information reproducing device characterized by using the waveform equalizing device of items 1, 2, 3 or 4. 7. The information reproducing apparatus according to claim 6, further comprising a training signal for converging an equalization coefficient and a threshold value of the waveform equalizing apparatus before reproducing data reproduced in time series from a recording medium. An information reproducing apparatus characterized by using a recording format.