JPH07169902A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH07169902A JPH07169902A JP5343494A JP34349493A JPH07169902A JP H07169902 A JPH07169902 A JP H07169902A JP 5343494 A JP5343494 A JP 5343494A JP 34349493 A JP34349493 A JP 34349493A JP H07169902 A JPH07169902 A JP H07169902A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- frame
- lead frame
- selection
- coordinates
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
(57)【要約】
【目的】 バイトワイド品、及び同一チップ異種パッケ
ージ品において、測定治工具の共用化をはかる。
【構成】 バイトワイド品及び同一チップ異種パッケー
ジ品において、アウトリード（３）を延長させて、電気
選別時に測定端子となるアウトリードの先端の座標を等
くした枠付き選別用リードフレームをとする。これによ
り、テストボード、ＢＴ板等の測定治工具の共用が可能
となり、費用及び工数削減につながる。
(57) [Summary] [Purpose] Use a common measuring tool for bite-wide products and products with different chips of the same chip. [Structure] For the bite-wide product and the same chip different package product, the outlead (3) is extended to form a framed selection leadframe in which the coordinates of the tips of the outleads that become measurement terminals during electrical selection are equal. . This makes it possible to share measurement jigs and tools such as test boards and BT boards, leading to cost and man-hour reduction.
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体集積回路チップ
を搭載して、パッケージ封入した半導体集積回路装置に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device in which a semiconductor integrated circuit chip is mounted and packaged.
【０００２】[0002]
【従来の技術】従来の製品は、バイトワイド品のよう
に、ビット数は同じでもそのＩ／Ｏ（入出力）構成等が
異なり、ピン数が違う品種において、選別治工具（テス
トボード、ＢＴ版等）は品種毎に必要であった。また、
ＤＩＰ，ＳＯＪ，ＳＯＰ（ＴＳＯＰ）で、リード形成後
の形状が大きく異なっていたり、選別体系（枠付き、枠
なし）が異なっている為、同一チップを搭載した製品で
も各パッケージ毎、又は選別体系に合わせた選別治工具
が必要であった。2. Description of the Related Art Conventional products, such as byte-wide products, have different I / O (input / output) configurations even if they have the same number of bits, but have different pin numbers. Versions, etc.) were required for each variety. Also,
DIP, SOJ, and SOP (TSOP) differ greatly in the shape after lead formation, and the sorting system (with or without frame) is different, so even for products with the same chip, each package or sorting system It was necessary to have a selection tool according to the above.
【０００３】[0003]
【発明が解決しようとする課題】従来の技術では、バイ
トワイド品及び同一チップ異種パッケージ品は、製品の
ピン数や大きさ及び、選別方法（枠付き・なし）が異な
るため、テストボードやＢＴ板等の選別治工具を共用す
ることができない。そのため、各品種・パッケージ毎に
設計・作成し、かつ、作業時にこれら治工具の交換を行
なう必要があり、費用・時間の面で効率が非常に悪いと
いう問題があった。In the prior art, the bit-wide product and the same-chip dissimilar package product differ in the number of pins and size of the product and the selection method (with / without frame), so that the test board and the BT are different. It is not possible to share selection tools such as plates. Therefore, it is necessary to design and create each product type and package and replace these jigs and tools at the time of work, which is very inefficient in terms of cost and time.
【０００４】[0004]
【課題を解決するための手段】本発明は、従来技術の課
題解決するために、半導体集積回路チップを搭載してパ
ッケージ封入した半導体集積回路装置において、各種リ
ードフレームのアウトリードを延長させて、電気選別時
に測定端子となるリード端子の先端の座標を等しくした
枠付き選別用リードフレームであり、また各種リードフ
レームが、ピン数の異なるバイトワイド品においてピン
数の多いリードフレームの品種に合わせて、同種の信号
を測定するリード端子の先端座標が等しくなるようにア
ウトリードを延長させた枠付き選別用リードフレームで
ある。SUMMARY OF THE INVENTION In order to solve the problems of the prior art, the present invention extends the out leads of various lead frames in a semiconductor integrated circuit device in which a semiconductor integrated circuit chip is mounted and packaged. A lead frame for sorting with a frame in which the coordinates of the tips of the lead terminals, which are measurement terminals during electrical sorting, are the same. Also, various lead frames have different pin counts. , A lead frame for selection with a frame in which the out leads are extended so that the tip coordinates of the lead terminals for measuring the same type of signals are equal.
【０００５】[0005]
【作用】本発明においては、ピン数の同じ同一チップ異
種パッケージ品種において、アウトリードを延長させ
て、同一の信号を測定するリード端子の先端座標を等し
くした枠付き選別用リードフレームを用いるものであ
り、また、ピン数の異なるバイトワイド品において、最
もピン数の多い品種に合わせて、同種の信号を測定する
リード端子の先端座標が等しくなる様にアウトリードを
延長させた枠付き選別用リードフレームを用いるもので
あるから、これにより、テストボード、ＢＴ板等の測定
治工具の共用ができるものである。In the present invention, in the same chip different package type having the same number of pins, the outlead is extended to use the framed selection leadframe in which the tip coordinates of the lead terminals for measuring the same signal are made equal. Yes, in the case of bite-wide products with different pin counts, the framed selection lead has an extended out lead so that the tip coordinates of the lead terminals that measure the same type of signal are the same, according to the product with the largest number of pins. Since the frame is used, the measurement jigs such as the test board and the BT board can be commonly used.
【０００６】[0006]
【実施例】次に本説明の実施例について、図面を参照し
て説明する。 ［実施例１］図１（Ａ）（Ｂ）は、本発明の第一の実施
例のリードフレームの図である。図１（Ａ）は、半導体
集積回路チップを搭載してパッケージ封入したもので、
そのパッケージがＤＩＰで、チップが樹脂（１）でパッ
ケージされており、そこには、タイバー（２）、アウト
リード（３）、吊りリード（４）が付けられている。ま
た図１（Ｂ）は、パッケージがＳＯＪで、図１（Ａ）と
同様に樹脂（１）でパッケージされており、タイバー
（２）、アウトリード（３）、吊りリード（４）が付け
られているものである。これらは、それぞれパッケージ
がＤＩＰ、ＳＯＪであるが、アウトリード（３）を従来
よりもフレキシブルに延長させて、同一信号ピンのリー
ド先端部の座標が等しくなっている。このような構造を
持ったリードフレームを用いて、選別方法を枠付きで統
一することにより、同一チップ、異種パッケージ品にお
いて、測定治工具の共用が可能となる。Embodiments of the present description will be described below with reference to the drawings. [Embodiment 1] FIGS. 1A and 1B are views of a lead frame of a first embodiment of the present invention. FIG. 1A shows a semiconductor integrated circuit chip mounted and packaged.
The package is a DIP and the chip is packaged with a resin (1), and a tie bar (2), an out lead (3), and a suspension lead (4) are attached thereto. Further, in FIG. 1 (B), the package is SOJ and is packaged with resin (1) as in FIG. 1 (A), and tie bars (2), out leads (3), and suspension leads (4) are attached. It is what The packages of these are DIP and SOJ, respectively, but the outlead (3) is extended more flexibly than in the conventional case, and the coordinates of the lead tip of the same signal pin are made equal. By using the lead frame having such a structure and standardizing the selection method with a frame, it becomes possible to share the measurement jigs and tools in the same chip and different package products.
【０００７】［実施例２］図２、図３及び図４は本発明
の第二の実施例のリードフレームの図である。このリー
ドフレームは、それぞれ、図２は３２pin 、図３は２８
pin 、そして図４は２４pin のバイトワイド品である。
これらは、ピン数の異なるバイトワイド品であるが、測
定端子の座標を最もピン数の多い品種、ここでは図２の
３２pinに合わせて測定端子の座標を決定する。ピン数
の少ない品種、例えば、図３の２８pin では、そのアウ
トリードは同種の信号を測定する（ＧＮＤ，ＶＣＣ，Ｉ
／Ｏ、アドレス）端子の位置まで延長させ、同種の信号
を測定するリード端子の先端座標が等しくなるようにす
る。また使用しない端子は、図３のように（ＶＣＣ）の
となりの（ＮＣ）を空き端子とする。図４の２４pin で
も、図３と同様に、アウトリードは同種の信号を測定す
る（ＧＮＤ，ＶＣＣ，Ｉ／Ｏ、アドレス）端子の位置ま
で延長させ、同種の信号を測定するリード端子の先端座
標が等しくなるようにする。また使用しない端子は空き
端子とする。その結果、ピン数の異なるバイトワイド品
において、選別方法を枠付きで統一し、選別プログラム
にて対応することにより測定治工具の共用が可能とな
る。[Second Embodiment] FIGS. 2, 3 and 4 are views of a lead frame according to a second embodiment of the present invention. This lead frame has 32 pins in FIG. 2 and 28 pins in FIG. 3, respectively.
pin, and Fig. 4 is a 24-pin byte wide product.
These are bite-wide products with different numbers of pins, but the coordinates of the measurement terminals are determined by matching the coordinates of the measurement terminals with the product having the largest number of pins, here 32 pins in FIG. For a product with a small number of pins, for example 28pin in Fig. 3, its outread measures the same type of signal (GND, VCC, I).
/ O, address) terminal so that the tip coordinates of the lead terminals for measuring signals of the same type are equal. Further, as for the unused terminal, as shown in FIG. 3, (NC) next to (VCC) is an empty terminal. Even in the case of 24pin of Fig. 4, as in Fig. 3, the outlead extends to the position of the terminal (GND, VCC, I / O, address) for measuring the same type of signal, and the tip coordinates of the lead terminal for measuring the same type of signal. Are equal. Unused terminals are unused terminals. As a result, for bite-wide products with different numbers of pins, the sorting method can be unified with a frame, and the sorting program can be used to share measurement jigs and tools.
【０００８】［実施例３］図５（Ａ）（Ｂ）は本発明の
第３の実施例のリードフレームの図である。実施例１お
よび実施例２で説明したように、チップが樹脂でパッケ
ージされており、そこに付けられているアウトリードは
リード端子の先端の座標を等しくなるように延長させて
いるので、従来のリードフレームよりも長い。そこで枠
付き選別を行う際のタイバー切断後のリードのふらつき
を抑えるため、アウトリード先端部を絶縁テープ（５）
で固定し、測定時の接触不良を低減させることができる
ものである。[Third Embodiment] FIGS. 5A and 5B are views of a lead frame according to a third embodiment of the present invention. As described in the first and second embodiments, the chip is packaged with resin, and the out leads attached to the chip extend the coordinates of the tips of the lead terminals so that they are the same as the conventional one. Longer than the lead frame. Therefore, in order to prevent the lead from fluctuating after cutting the tie bar when sorting with a frame, the tip of the out-lead is insulated tape (5).
It is possible to reduce contact failure during measurement by fixing with.
【０００９】[0009]
【発明の効果】以上説明したように、本発明によれば、
バイトワイド品及び同一チップ異種パッケージ品におい
て、アウトリードを延長させて、電気選別時に測定端子
となるアウトリードの先端の座標を等しくした枠付き選
別用リードフレームを用いることにより、テストボー
ド、ＢＴ板等の測定治工具の共用が可能となり、費用及
び工数削減という効果を奏するものである。As described above, according to the present invention,
For bite-wide products and same-chip different-package products, by using the lead frame for sorting with a frame, in which the out leads are extended and the coordinates of the tips of the out leads that are measurement terminals at the time of electrical sorting are the same, It is possible to share the measuring jigs and tools such as the above, and it is possible to reduce the cost and man-hours.
【図１】本発明の第１の実施例の半導体装置の平面図。FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention.
【図２】本発明の第２の実施例の半導体装置の平面図。FIG. 2 is a plan view of a semiconductor device according to a second embodiment of the present invention.
【図３】本発明の第２の実施例の半導体装置の平面図。FIG. 3 is a plan view of a semiconductor device according to a second embodiment of the present invention.
【図４】本発明の第２の実施例の半導体装置の平面図。FIG. 4 is a plan view of a semiconductor device according to a second embodiment of the present invention.
【図５】本発明の第３の実施例の半導体装置の平面図。FIG. 5 is a plan view of a semiconductor device according to a third embodiment of the present invention.
１ 樹脂 ２ タイバー ３ アウトリード ４ 吊りリード ５ 絶縁テープ 1 Resin 2 Tie bar 3 Out lead 4 Hanging lead 5 Insulating tape
Claims (3)
ージ封入した半導体集積回路装置において、各種リード
フレームのアウトリードを延長させて、電気選別時に測
定端子となるリード端子の先端の座標を等しくした枠付
き選別用リードフレーム。1. In a semiconductor integrated circuit device in which a semiconductor integrated circuit chip is mounted and packaged, a frame in which the out-leads of various lead frames are extended and the coordinates of the tips of the lead terminals serving as measurement terminals at the time of electrical selection are equalized. With lead frame for sorting.
バイトワイド品においてピン数の多いリードフレームの
品種に合わせて、同種の信号を測定するリード端子の先
端座標が等しくなるようにアウトリードを延長させたこ
とを特徴とする請求項１に記載の枠付き選別用リードフ
レーム。2. The lead frame of various types is extended in accordance with the type of a lead frame having a large number of pins in a bite-wide product having a different number of pins so that the tip coordinates of the lead terminals for measuring the same type of signal are equal. The lead frame for selection with a frame according to claim 1, wherein the lead frame for selection is provided.
ープで固定したことを特徴とする請求項１または２に記
載の枠付き選別用リードフレーム。3. The framed lead frame for sorting according to claim 1, wherein the extended out-lead tip portion is fixed with an insulating tape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5343494A JP2928075B2 (en) | 1993-12-16 | 1993-12-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5343494A JP2928075B2 (en) | 1993-12-16 | 1993-12-16 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07169902A true JPH07169902A (en) | 1995-07-04 |
| JP2928075B2 JP2928075B2 (en) | 1999-07-28 |
Family
ID=18361955
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5343494A Expired - Fee Related JP2928075B2 (en) | 1993-12-16 | 1993-12-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2928075B2 (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60165748A (en) * | 1984-02-08 | 1985-08-28 | Toshiba Corp | Lead frame |
| JPH04127450A (en) * | 1990-09-18 | 1992-04-28 | Fujitsu Miyagi Electron:Kk | Manufacture of lead frame and semiconductor device |
| JPH0669410A (en) * | 1992-08-17 | 1994-03-11 | Nec Yamagata Ltd | Manufacture of semiconductor device |
-
1993
- 1993-12-16 JP JP5343494A patent/JP2928075B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60165748A (en) * | 1984-02-08 | 1985-08-28 | Toshiba Corp | Lead frame |
| JPH04127450A (en) * | 1990-09-18 | 1992-04-28 | Fujitsu Miyagi Electron:Kk | Manufacture of lead frame and semiconductor device |
| JPH0669410A (en) * | 1992-08-17 | 1994-03-11 | Nec Yamagata Ltd | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2928075B2 (en) | 1999-07-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6831353B2 (en) | Interdigitated leads-over-chip lead frame and device for supporting an integrated circuit die | |
| EP1081757A1 (en) | Multichip module packaging process for known good die burn-in | |
| JP2928075B2 (en) | Semiconductor device | |
| JP2003318353A (en) | Semiconductor chip package | |
| WO1989010593A1 (en) | Memory testing system | |
| JPS60200537A (en) | Semiconductor device with exclusive testing terminal | |
| JP2972473B2 (en) | Semiconductor device | |
| JP2765467B2 (en) | Semiconductor integrated circuit device | |
| KR970010677B1 (en) | Leadframe structure | |
| JPS62195136A (en) | Manufacture of semiconductor device | |
| KR200166710Y1 (en) | Burn-in board of COB type semiconductor chip | |
| JPH04144266A (en) | Manufacture of hybrid integrated circuit | |
| KR100234025B1 (en) | Stacked Module Test Unit | |
| KR19980037796U (en) | Performance boards for semiconductor chip test equipment | |
| JPH0159741B2 (en) | ||
| JPS6379364A (en) | Eiectronic part | |
| JPH0474450A (en) | Method and jig for testing semiconductor integrated circuit | |
| JPS62102536A (en) | Integrated circuit package | |
| JPH05226567A (en) | Semiconductor package | |
| JPH06132464A (en) | Method for assembling semiconductor integrated circuit | |
| JPH10313088A (en) | Semiconductor element, semiconductor device and method of manufacturing the same | |
| JPH0317576A (en) | semiconductor equipment | |
| JPS60167452A (en) | socket | |
| JPS59138353A (en) | Integrated circuit device | |
| JPH06181287A (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19970401 |
|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313117 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090514 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090514 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100514 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100514 Year of fee payment: 11 |
|
| S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100514 Year of fee payment: 11 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100514 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110514 Year of fee payment: 12 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120514 Year of fee payment: 13 |
|
| LAPS | Cancellation because of no payment of annual fees |