JPH07182014A - Chip adsorption control circuit for arm - Google Patents

Abstract

PURPOSE:To perform valve control during the move of an arm so as not to generate any time loss caused by the acceleration/deceleration time of the arm or the like for stopping the arm. CONSTITUTION:A CPU 101 performs selection so that a selector 106 can output a timing signal as a valve latch signal, outputs a valve control signal and valve control data and outputs the valve control data from a first latch 107 to a latch 108 for valve control. A memory 104 stores the prescribed value of timing to control a valve 109 and next, a counter 103 starts counting. When the arm is moved, an encoder pulse is outputted from an encoder 102 and the counter 103 counts the number of those pulses. When the count value is matched with the value in the memory 104, the timing signal is outputted from a comparator 105, the selector 106 outputs it to the latch 108 as a valve latch signal, and the valve 109 is controlled by the data from the latch 108.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounter for mounting a chip on a substrate such as an IC, and more particularly to chip suction control of an arm for carrying the chip.

[0002]

2. Description of the Related Art A conventional chip adsorption control is disclosed in Japanese Patent Laid-Open No.
As described in JP-A-191428, after the arm moves to the bonding surface, a control circuit turns on a valve that supplies air to a suction mechanism for sucking a chip.
/ OFF control is performed.

Next, this conventional arm chip suction control circuit will be described in detail with reference to the drawings.

FIG. 3 is a block diagram showing an example of a conventional chip adsorption control circuit for an arm.

The chip suction control circuit of the arm of this conventional example reads the valve control signal output from the CPU by the valve latch signal and supplies air to the suction mechanism by the valve 304.
And a CPU 301 for controlling a valve 302
And a valve latch signal generation circuit 303 which reads a data signal output from the CPU 301 by the OUT signal from the CPU, generates a valve latch signal, and outputs the valve latch signal to the valve control latch 302.

Next, the operation will be described.

First, the CPU 301 outputs the OUT signal and the data signal to the valve latch signal generation circuit 303, and then outputs the valve control signal to the valve control latch 302. The valve latch signal generation circuit 303 generates a valve latch signal from the OUT signal and the data signal, and outputs the generated valve latch signal to the valve control latch 302. The valve control latch 302 turns on the valve 304 based on the valve control signal according to the input valve latch signal.
N / OFF control.

Then, in order to prevent the suction mechanism (not shown) from sucking the solder for mounting the chip on the substrate such as an IC, the moving arm is temporarily moved to the valve 304.
Stop at a position that controls
F is set to stop the supply of air to the suction mechanism (not shown).

[0009]

The above-described conventional arm chip adsorption control circuit controls the valve in order to prevent the adsorption mechanism from inhaling the solder for mounting the chip on the substrate of an IC or the like. It is necessary to stop the arm once at the position, which causes a time loss due to the acceleration / deceleration time of the arm and the like, which causes a problem of lowering work efficiency.

[0010]

A chip adsorption control circuit for an arm according to the present invention comprises an encoder mounted on an arm motor that operates an arm that carries a chip and operates according to a count start signal from a host device, and a pulse from the encoder. A counter that counts the number, a memory that stores a predetermined value output from a host device that controls a valve that supplies air to a suction mechanism that suctions chips, and a counter value and a memory value are compared. A comparator that outputs a timing signal when they match, a selector that selects the valve control signal from the host device and the timing signal from the comparator with the select signal from the host device, and outputs either one as the valve latch signal, and the host device When the valve control signal from the A first latch for latching the valve control data that is characterized in that the valve control data from the first latch in accordance with the valve latch signal from the selector and a latch valve control outputs to the valve.

[0011]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an arm chip adsorption control circuit according to the present invention.

The chip adsorption control circuit of the arm of this embodiment operates in response to a count start signal from the CPU 101 and is mounted on an arm motor that moves an arm that carries chips, and a pulse from the arm motor encoder 102. A counter 103 that counts the number and a suction mechanism (not shown) that suctions chips
CP for controlling the valve 109 that supplies air to the
A memory 104 for storing a predetermined encoder pulse count value output from U101, a comparator 105 for comparing the value of the counter 103 with the value of the memory 104 and outputting a timing signal when they match, and a valve control signal from the CPU 101. A selector 106 that selects a timing signal from the comparator 105 with a select signal from the CPU 101 and outputs one of them as a valve latch signal, and a valve control output from the CPU 101 when the valve control signal from the CPU 101 is input. First latch 107 for latching data
And valve control data from the first latch 107 according to the valve latch signal from the selector 106.
And a valve control latch 108 for outputting to.

Next, the operation will be described.

When performing normal valve control, first the CPU
A selector 106 selects a valve control signal to be output as a valve latch signal by a select signal from 101, and then CPU 101 outputs valve control data and a valve control signal. First latch 107
Receives the valve control data and the valve control signal, latches and outputs the valve control data. The selector 106 outputs the input valve control signal as a valve latch signal. Latch for valve control 1
When the valve latch signal is input from the selector 106, 08 outputs the valve control data output from the first latch 107 to the valve 109, and the valve 109 controls ON / OFF of the valve 109 according to the valve control data. Air is supplied to (not shown).

Next, the case of controlling the valve while the arm is moving will be described with reference to the flow charts of FIGS. 1 and 2.

FIG. 2 is a flow chart in the case of controlling the valve during the movement of the arm by the chip adsorption control circuit of the present embodiment.

First, when a predetermined select signal is output from the CPU 101, the selector 106 is activated by the select signal.
Selects to output the timing signal as a valve latch signal (S201). Next, the CPU 101 outputs the valve control signal and the valve control data, and causes the first latch 107 to output the valve control data to the valve control latch 108 (S202). The CPU 101 outputs a predetermined encoder pulse count value, which is the timing for controlling the valve 109, and stores the value in the memory 104 (S203). The CPU 101 outputs a count start signal to cause the counter 103 to start counting (S204). When the arm moves, an encoder pulse is output from the arm motor encoder 102, and the counter 103 counts the pulse number. Counter 1
When the count value of 03 matches the value of the memory 104, a timing signal is output from the comparator 105, the selector 106 outputs the timing signal as a valve latch signal to the valve control latch 108, and the valve control latch 108 outputs the valve latch signal. The valve control data output from the first latch 107,
The valve 109 is ON / OFF controlled by the valve control data, and the supply of air to the suction mechanism (not shown) is stopped (S205).

[0019]

As described above, the arm chip adsorption control circuit of the present invention enables the valve to be controlled even when the arm carrying the chip is moving, thereby adding the arm for stopping the arm. There is an effect that time loss due to deceleration time and the like can be eliminated and work efficiency can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an arm chip suction control circuit according to the present invention.

FIG. 2 is a flow chart when a valve is controlled during movement of the arm by the chip adsorption control circuit of the arm of the present embodiment.

FIG. 3 is a block diagram showing an example of a conventional chip adsorption control circuit for an arm.

[Explanation of symbols]

 101 CPU 102 Encoder 103 Counter 104 Memory 105 Comparator 106 Selector 107 First Latch 108 Valve Control Latch 109 Valve 301 CPU 302 Valve Control Latch 303 Valve Latch Signal Generation Circuit 304 Valve

Claims (1)

[Claims] 1. An encoder mounted on an arm motor that operates an arm that carries a chip and operates according to a count start signal from a host device, a counter that counts the number of pulses from the encoder, and an adsorption mechanism that adsorbs the chip. A memory for storing a predetermined value output from the host device for controlling a valve for supplying air to the comparator, and a comparator for outputting a timing signal when the value of the counter and the value of the memory are compared and coincident with each other. , A selector for selecting a valve control signal from the host device and a timing signal from the comparator by a select signal from the host device and outputting one of them as a valve latch signal, and a valve control signal from the host device. Valve control output from the host device when input Suction control of the arm, including a first latch for latching the control data and a valve control latch for outputting the valve control data from the first latch to the valve according to a valve latch signal from the selector. circuit.