JPH07193191A - MOS capacitor and method of manufacturing the same - Google Patents

Abstract

(57) [Summary] [Structure] A MOS capacitor of the present invention comprises a first electrode layer in which a slit having a specific shape is formed on the surface of a dielectric oxide film and which is in contact with the dielectric oxide film at an arbitrary area. A second electrode layer joined to the first electrode layer is provided, and the capacitor capacitance can be controlled with high accuracy. [Effect] According to the present invention, by forming the electrode layer on the dielectric insulating film in a specific shape, the error in the capacitance of the capacitor is reduced, the correction capacitor is not required, and the integrated circuit is downsized. it can. In addition, since a capacitor having any structure can be manufactured, the manufacturing yield is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS capacitor formed in a semiconductor integrated circuit and its manufacturing method.

[0002]

2. Description of the Related Art When manufacturing a highly accurate capacitor in an integrated circuit, since the capacitance of the capacitor is determined by the film thickness of the dielectric, it is important to suppress this film thickness variation. FIG. 3 shows a plan view and a sectional view showing an example of a conventional MOS capacitor. According to this, in the current manufacturing equipment, the film thickness varies from wafer to wafer by about ± 10%.
Even within the same wafer surface, the film thickness varies by about ± 3%. In the future, there is a strong tendency to increase the diameter of wafers, and the variation in film thickness within the same wafer surface tends to increase. In the case of a filter circuit or the like that requires precision of capacitance, it is necessary to carry out the adjustment work by taking out the terminal from the integrated circuit and mounting it externally. Therefore, there is a problem that the number of terminals increases. Further, when the external circuit for adjustment is built in the integrated circuit by the conventional technique, there is a problem that the accuracy of the adjustment capacitor capacity and the resistance is required to be improved, and the yield is reduced.

[0003]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and when forming an electrode of a capacitor, an electrode contacting the dielectric depending on the data of the film thickness of the dielectric. The purpose of this method is to adjust the area when forming the device, make the total capacitance to a required value, reduce the circuit for correction, and reduce the size of the integrated circuit and increase the yield.

[0004]

In order to achieve the above object, according to the present invention, when a capacitor is manufactured in an integrated circuit, the thickness of the dielectric oxide film formed on a semiconductor substrate is changed according to the thickness of the dielectric oxide film. The total area of the first electrode layer that is in contact with is adjusted. When forming the first electrode layer, a groove having a specific width is formed in the first electrode layer by adjusting the exposure time or the etching time of the exposure device or by using several kinds of mask patterns. Adjust the contact area with the oxide film. The first electrode layer thus formed is coupled by the second electrode layer, and the total capacitance of the capacitor is made to be a required value.

[0005]

According to the present invention, the first electrode layer is formed on the basis of the film thickness map data even when the film thickness varies between wafers or when the film thickness varies within the same wafer. In doing so, the contact area between the electrode layer and the dielectric oxide film can be adjusted by adjusting the exposure time and the etching time and selecting the type of mask pattern. By coupling the first electrode layer when forming the second electrode layer, the total capacitance of the capacitor can be made to a required value.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIG. FIG. 1A is a plan view and FIG. 1B is a sectional view.
FIG. 1 shows a case where the first electrode layer contacting the dielectric oxide film formed on the semiconductor substrate (1) is formed by slits in a grid pattern. As a method for forming this grid-shaped electrode layer, there is a method in which Al is vapor-deposited on the dielectric oxide film (4), a resist is applied, and exposure is performed with a mask manufactured in a grid shape. After exposure, etching is performed to remove the resist
An electrode layer (5) is formed. Here, the slit width of the electrode layer is adjusted by determining the electrode area based on the film thickness map data created from the values measured by the film thickness measuring device after forming the dielectric oxide film. The exposure time and etching time of the PEP when forming the slits are adjusted so that the required electrode area is obtained. The resist may be of either positive type or negative type. Next, in order to insulate and separate the dielectric oxide film exposed under the slit, a first electrode layer interlayer insulating film (6) is formed. This is performed at low temperature by plasma SIO which is a kind of oxide film. The reason for carrying out at a low temperature is to prevent the Al forming the first electrode layer, which was previously formed, from melting. After that, an insulating polymer (7) is formed on the interlayer insulating film to flatten the surface of the interlayer insulating film and the surface of each electrode of the first electrode layer. Second electrode layer
By (8), the first electrode layer is electrically coupled to complete the element portion of the MOS capacitor. Where slit width 2.0 μm
Then, FIG. 2 shows a relational table of the slit width, the electrode area, and the correction value for the electrode whose one side of the first electrode layer is a square having one side of 20 μm as a reference. As shown in Fig. 2, the slit width,
By adjusting the side length of the electrode, the contact area with the dielectric oxide film can be finely adjusted. Further, even if the slit width is adjusted further than this, the electrode area changes in accordance therewith, so that a larger scale correction can be performed. Therefore, the capacitance of the capacitor can be corrected by adjusting the electrode area according to the variation in the film thickness of the dielectric oxide film.

In addition, in the method of forming the first electrode layer, it is considered that the wiring width of other element portions may be affected. Therefore, after the PEP mask of the first electrode layer is aligned, the slit pattern is formed. A method of double exposure with only one,
Separately from the above method, several kinds of reticles having different slit widths are prepared based on the film thickness map data, and the reticles having the slit width so that the total capacity is a desired value are selected, and exposure and etching are performed. There is a way.

As described above, the pattern of the first electrode layer is not limited to the lattice shape in view of the technical idea of the present invention, and the above-mentioned method such as the stripe shape, the circular shape or the triangular shape is used. The pattern can be manufactured by any method and the contact area with the dielectric oxide film can be arbitrarily controlled, and various modifications can be carried out without departing from the spirit of the pattern.

[0009]

As described above, when the first electrode layer is formed on the dielectric insulating film of the capacitor, the exposure time and the etching time are adjusted, and the type of mask pattern is selected so that the electrode layer And adjust the contact area of the dielectric oxide film. By combining the first electrode layer when forming the second electrode layer, the total capacitance of the capacitor can be built into the required value.

As a result, the error in the capacitance of the capacitor is reduced, and it becomes possible to fabricate a highly accurate MOS capacitor in the integrated circuit. The adjustment circuit, which has been conventionally required for external attachment, becomes unnecessary, the number of terminals of the integrated circuit for external attachment can be reduced, and miniaturization of the integrated circuit can be realized. Further, even if a circuit is conventionally provided for capacitance correction inside the integrated circuit, it is not necessary, so that the integrated circuit can be downsized and the manufacturing yield is improved.

[Brief description of drawings]

FIG. 1A is a plan view and FIG. 1B is a sectional view showing an embodiment of a MOS capacitor of the present invention.

FIG. 2 is a relational chart of slit width, electrode area, and correction value.

3A is a plan view and FIG. 3B is a sectional view showing an example of a conventional MOS capacitor.

[Explanation of symbols]

1 Semiconductor Substrate 2 N ⁺ Diffusion Layer 3 Field Oxide Film 4 Dielectric Oxide Film 5 First Electrode Layer 6 First Electrode Layer Interlayer Insulation Film 7 Insulating Polymer 8 Second Electrode Layer

Claims (4)

[Claims] 1. A semiconductor substrate, a dielectric oxide film formed on the semiconductor substrate, a slit having a specific shape which is present on the surface of the dielectric oxide film, and has an arbitrary area with the dielectric oxide film. A first electrode layer which is in contact with the first electrode layer, an interlayer insulating film which is formed with a predetermined opening to cover the first electrode layer, and a first electrode layer which is bonded to the first electrode layer through the opening. A MOS capacitor comprising two electrode layers. 2. The MOS capacitor according to claim 1, wherein the slit shape of the first electrode layer is a lattice shape. 3. A step of preparing a semiconductor substrate, a step of forming a dielectric oxide film on the semiconductor substrate, and a first electrode layer having a slit of a specific shape formed on the surface of the dielectric oxide film. And a step of forming an interlayer insulating film which covers the slit of the first electrode layer and has a predetermined opening, and a step of joining the first electrode layer on the interlayer insulating film through the opening. And a step of forming a second electrode layer. 4. The method for manufacturing a MOS capacitor according to claim 3, wherein the slit width of the first electrode layer is adjusted based on film thickness map data produced from the film thickness of the dielectric oxide film. And a method for manufacturing a MOS capacitor.