JPH07193473A - Waveform change detection circuit - Google Patents

Abstract

(57) [Summary] [Object] The present invention relates to a waveform change detection circuit for detecting a waveform change of an input periodic analog signal, and an object thereof is to enable detection of a waveform change with a small circuit scale. To do. [Structure] Binarizing an analog signal by using a threshold value derived from the analog signal itself in synchronization with a clock 2
An analog signal is obtained by comparing the output value and the input value of the shift register means 12 with the shift register means 12 that latches the output value of the binarization means 11 while shifting the output value of the binarization means 11 by the period of the analog signal. And a comparing means 13 for detecting the occurrence of the waveform change of.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform change detecting circuit for detecting a waveform change of an input periodic analog signal, and more particularly to a waveform change detecting circuit for detecting a waveform change with a small circuit scale. Regarding

In various monitoring systems, there is a demand for detecting waveform changes of analog signals having periodicity. A waveform change detection circuit that fulfills such a demand needs to be able to detect a waveform change with a small circuit scale in order to enhance the practicality of the system.

[0003]

2. Description of the Related Art FIG. 11 shows a circuit configuration of a conventional waveform change detection circuit. As shown in this figure, in the conventional waveform change detection circuit, in order to detect the waveform change of the periodic analog signal that is input, a sampling hold circuit 1 that samples and holds the input analog signal is used. , A / which converts the analog signal held by the sampling and holding circuit 1 into a digital signal
The D converter 2, the first memory 3 / second memory 4 for storing one cycle of digital signal output from the A / D converter 2, and the two first memory 3 / second Memory 4
And a comparison circuit 5 for comparing the digital signals stored in

In the conventional waveform conversion detection circuit having such a configuration, when an analog signal to be processed is input, the sampling and holding circuit 1 samples and holds this analog signal and A / D converts it. Vessel 2 is
The analog signal held by the sampling and holding circuit 1 is converted into a digital signal and alternately stored in the first memory 3 / second memory 4 in units of one cycle.

In response to this storage processing, the comparison circuit 5 compares the digital signal for one cycle stored in the first memory 3 with the digital signal for one cycle stored in the second memory 4. By doing so, it is detected whether or not a change has occurred in the waveform of the input analog signal and the result is output.

In this way, the conventional waveform change detection circuit adopts a configuration in which the waveform data of the analog signal to be processed is sequentially detected, and the detected current period waveform data and the waveform data of one period before are detected. It is configured to detect whether or not a waveform change has occurred in the analog signal by comparing.

[0007]

However, according to such a conventional technique, an A / D having a large circuit scale is obtained.
The converter 2 is required, and the first memory 3 / second memory 4 having a large memory capacity defined by the number of samplings and the number of output bits of the A / D converter 2 is required. was there.

That is, if the conventional waveform change detection circuit is followed, there is a problem that the circuit scale becomes large. The present invention has been made in view of the above circumstances, and an object thereof is to provide a new waveform change detection circuit that detects a waveform change of an input periodic analog signal with a small circuit scale.

[0009]

[Means for Solving the Problems] FIG. 1 (a) (b) (c)
The principle structure of the waveform change detection circuit 10 of the present invention for executing the detection processing of the waveform change of the input periodic analog signal is shown.

A waveform change detection circuit 10 whose principle configuration is shown in FIG. 1A includes a binarizing means 11 for binarizing an input analog signal using a threshold value derived from the analog signal itself. By comparing the output value and the input value of the shift register means 12 with the shift register means 12 that shifts and latches the output value of the binarizing means 11 by the period of the analog signal, occurrence of a waveform change of the analog signal is detected. And the output unit 14 that outputs the waveform change occurrence of the analog signal to the outside when the occurrence frequency of the waveform change detected by the comparison unit 13 is equal to or higher than the specified frequency.

On the other hand, the waveform change detection circuit 10 whose principle configuration is shown in FIG. 1B, binarizes the input analog signal by using a threshold value derived from the analog signal itself. A shift register means 12 for latching the output value of the binarizing means 11 while shifting it by the cycle of the analog signal; and a first counter means 1 for counting the output value of the shift register means 12 in accordance with a prescribed counting cycle.
5 and the shift register means 12 according to this counting cycle.
Second counter means 16 for counting the input value of, the count value of the first counter means 15, and the second counter means 16
Of the analog signal by detecting the occurrence of the waveform change of the analog signal, and when the frequency of occurrence of the waveform change detected by the comparing means 17 is equal to or more than the specified value And an output means 18 for outputting to.

On the other hand, the waveform change detection circuit 10 whose principle configuration is shown in FIG. 1 (c) is a binarizing means 11 for binarizing an input analog signal using a threshold value derived from the analog signal itself. And according to the specified counting cycle, 2
Counter means 19 for counting the output value of the digitizing means 11;
A plurality of shift register means 20 provided corresponding to the binary output of the counter means 19 and latching corresponding binary output values while shifting them by the cycle of the analog signal according to this counting cycle, and the output values and inputs of the shift register means 20. By comparing with the value, the comparison unit 21 for detecting the occurrence of the waveform change of the analog signal, and when the occurrence frequency of the waveform change detected by the comparison unit 21 is equal to or more than the specified value, the occurrence of the waveform change of the analog signal is output to the outside Output means 22 for

The binarizing means 11 shown in these principle configuration diagrams is, for example, as shown in FIG. 2, a comparator means 23 for binarizing an input analog signal by comparing it with a threshold value, and a comparator means. Latch means 24 for latching the output value of 23 in synchronization with the clock, charging / discharging means 25 for generating a threshold value by executing charging / discharging according to the output value of the latch means 24, and for each cycle of the analog signal. The charging / discharging means 25 may be configured with a resetting means 26 for resetting the charging / discharging voltage.

[0014]

In the waveform change detection circuit 10 whose principle configuration is shown in FIG. 1A, the binarizing means 11 is derived from the input analog signal itself by adopting the configuration shown in FIG. 2, for example. The threshold value is used to binarize the input analog signal in synchronization with the clock.

In response to this binarization processing, the shift register means 12 latches the output value of the binarization means 11 while shifting it by the period of the analog signal. If there is no change in the periodicity of the input analog signal according to this latch processing, as shown in FIG.
The output value output by the above-mentioned means shows the same binarized value as the input value input to the shift register means 12.

Then, the comparing means 13 compares the output value and the input value of the shift register means 12 to detect whether or not a change has occurred in the waveform data of the analog signal which is input, and this detection is performed. Upon receiving the result, the output means 1
Reference numeral 4 outputs the waveform change occurrence of the analog signal to the outside when the occurrence frequency of the waveform change detected by the comparison means 13 is equal to or higher than a prescribed value.

In this way, by using the waveform change detection circuit 10 whose principle configuration is shown in FIG. 1A, the waveform of the periodic analog signal that is input is input according to a simple circuit configuration with a small circuit scale. Change can be detected.

On the other hand, in the waveform change detection circuit 10 whose principle configuration is shown in FIG. 1B, the binarization means 11 derives from the input analog signal itself by adopting the configuration shown in FIG. 2, for example. The inputted analog signal is binarized in synchronization with the clock by using the threshold value.

In response to this binarization processing, the shift register means 12 latches the output value of the binarization means 11 while shifting it by the period of the analog signal, and in response to this latching processing, the first counter means. 15 counts the output value of the shift register means 12 according to a prescribed counting period, while
The second counter means 16 counts the input value of the shift register means 12 in accordance with this counting cycle.

As described above, when there is no change in the periodicity of the input analog signal, the output value output from the shift register means 12 is the same as the input value input to the shift register means 12. Indicates a binarized value. Therefore, when there is no change in the periodicity of the input analog signal, the count value of the first counter means 15 and the count value of the second counter means 16 show the same value.

Then, the comparing means 17 compares the count value of the first counter means 15 with the count value of the second counter means 16 to generate a change in the waveform data of the input analog signal. In response to the detection result, the output unit 18 outputs the waveform change occurrence of the analog signal to the outside when the occurrence frequency of the waveform change detected by the comparison unit 17 is equal to or more than the specified value.

In this way, by using the waveform change detection circuit 10 whose principle configuration is shown in FIG. 1B, the waveform of the periodic analog signal input according to the simple circuit configuration having a small circuit scale is obtained. Change can be detected.

On the other hand, in the waveform change detection circuit 10 whose principle configuration is shown in FIG. 1C, the binarizing means 11 derives from the input analog signal itself by adopting the configuration shown in FIG. 2, for example. The inputted analog signal is binarized in synchronization with the clock by using the threshold value.

Upon receiving this binarization processing, the counter means 1
9 counts the output value of the binarizing means 11 in accordance with a prescribed counting cycle, and in response to this counting processing, each shift register means 20 changes the corresponding binary output value of the counter means 19 by the cycle of the analog signal. Latch while shifting. According to this latch processing, when there is no change in the periodicity of the input analog signal, each shift register means 2
The output value output from 0 indicates the same binarized value as the input value input to each shift register means 20.

From this, the comparison means 21 compares the output value of each shift register means 20 with the input value to detect whether or not a change has occurred in the waveform data of the analog signal that is input, and this In response to the detection result, the output unit 22 outputs the waveform change occurrence of the analog signal to the outside when the occurrence frequency of the waveform change detected by the comparison unit 21 is equal to or higher than the regulation.

In this way, by using the waveform change detection circuit 10 whose principle configuration is shown in FIG. 1C, the waveform of the periodic analog signal input according to a simple circuit configuration with a small circuit scale is obtained. Change can be detected.

[0027]

EXAMPLES The present invention will be described in detail below with reference to examples. FIG. 4 shows an embodiment of the waveform change detection circuit 10 of the present invention whose principle configuration is shown in FIG. here,
It is assumed that an analog signal having a period T is input to the waveform change detection circuit 10.

In the figure, 30 is a clock source having a period T
A clock generator for generating a clock having _c , 31 is an N divider, which divides the clock generated by the clock source 30 to generate a clock having the same period as the period T of the input analog signal. 32 is a binarization circuit for binarizing an input analog signal,
33 is a shift register composed of N bits,
In synchronization with the clock generated by the clock source 30, the binarized value output from the binarized circuit 32 is latched while being shifted by the period of the analog signal. Reference numeral 34 is an EOR circuit, which is the output of the shift register 33. The exclusive OR value of the output value to be input and the input value input to the shift register 33 is calculated and output.

Since the shift register 33 latches the binarized value output from the binarization circuit 32 while shifting it by the period of the analog signal, the N-bit configuration of the shift register 33 and the clock. The relational expression “T = T _c × N” holds between the period T _{c of} the clock generated by the source 30 and the period T of the input analog signal.

The binarization circuit 32 includes a resistor R₂
And capacitor C₂It consists of and
High-pass filter 35 for removing the DC component of the analog signal
And the output voltage value V of the high pass filter 35_aAnd anaro
Voltage value V derived from the waveform characteristics of the_bLarge with
Outputs high level value / low level value by comparing small
The clock generated by the comparator 36 and the clock source 30
The output of the comparator 36 is latched in synchronization with
Output to the register 33 / EOR circuit 34
Flip-flop 37 and a D-type flip-flop 37 latch
+ V depending on the value_c/ -V_cGenerates and outputs the voltage value of
Buffer 38, inverting amplifier and resistor R ₁And capacitor
C₁And the output voltage value of the buffer 38
The comparison voltage value V used by the comparator 36_bGenerate
And the clock output from the N divider 31
By turning it on and off as a control signal, the integration circuit 39
And a switch 40 for discharging the charging voltage of the
It

Next, the operation processing of the waveform change detection circuit 10 of the embodiment shown in FIG.
When an analog signal having a cycle T is input, the comparator 36 compares the output voltage value V _a output by the high-pass filter 35 with the comparison voltage value V _b generated by the integrating circuit 39, outputs a low level value when detecting V _a ≧ V _b ", when detecting" V _a <V _b "is going to output a high-level value.

In response to the output processing of the comparator 36, the D-type flip-flop 37 latches the output of the comparator 36 and outputs it to the buffer 38 in synchronization with the clock generated by the clock source 30. It receives the output processing flop 37, the buffer 38 outputs a voltage value of "-V _c" when the D-type flip-flop 37 latches the low level value, when latches the high level value of "+ V _c" The voltage value is output.

[0033] Thus, the integration circuit 39, and the period T _c of the generated clock of the clock source 30 to the unit, "- V _c" or "+ V _c" voltage that is sequentially input Become.

The integrating circuit 39 receives this input and

[0035]

[Equation 1]

According to the integral expression
Generates a comparison voltage value V _b used by Therefore, when the buffer 38 outputs the voltage value of “−V _c ”, the integrating circuit 39 uses the previously output comparison voltage value V _b as

[0037]

[Equation 2]

When the buffer 38 outputs the voltage value of "+ V _c ", the comparison voltage value V _b output last time is

[0039]

[Equation 3]

According to the above, the processing is performed so as to be updated. That is, in the integrating circuit 39, the switch 40 is turned on in accordance with the N frequency divider 31, so that the comparison voltage value V _b is “0”.
Then, the comparator 36 is reset to "V
When “ _a ≧ V _b ” is detected, the comparison voltage value V _b is increased according to the formula [2] and “V _a <
When detecting “V _b ”, the comparison voltage value V _b is decreased according to the formula [3].

In this way, the binarization circuit 32 is configured as shown in FIG.
As shown in FIG. 5, a comparison voltage value V _b is generated from the input analog signal, and the input analog signal is binarized by using the generated comparison voltage value V _b to shift register 33 / EOR. It is processed so as to be output to the circuit 34.

The shift register 33 receives the output processing of the binarization circuit 32 and latches the binarized value of the output analog signal while shifting it by the period of the analog signal. According to this latching process, when the periodicity of the input analog signal does not change, the binarized value output from the shift register 33 is the same as the binarized value input to the shift register 33. Will be shown.

When the binarized value output from the shift register 33 and the binarized value input to the shift register 33 are received, the EOR circuit 34 determines that the binarized values of the two coincide with each other. , A low level value is output to indicate that no change occurs in the input analog signal waveform data, and when there is no binary value for both, a change occurs in the input analog signal waveform data. A high level value is output to display the fact.

In this way, the waveform change detection circuit 10 shown in FIG. 4 does not use an A / D converter or a large-capacity memory, and according to a simple structure, the waveform of the input periodic analog signal is obtained. Change can be detected.

In the embodiment shown in FIG. 4, the integrating circuit 39
Although a device using an inverting amplifier is disclosed as FIG.
It is also possible to use an integral structure composed of a resistor R ₁ and a capacitor C ₁ as shown in (a). When this configuration is adopted, the buffer 38 outputs a voltage value of “+ V _c ” when “V _a ≧ V _b ”, so that the comparison voltage value V _b is increased so that the D-type voltage is increased. The output value of the inverted Q terminal of the flip-flop 37 is input to the buffer 38. As shown in FIG. 6B, the integrating circuit 39 includes a capacitor C ₁ , two current sources, and a switch that selects one of the current sources according to the output value of the D-type flip-flop 37. It is also possible to use

Next, an embodiment of the waveform change detection circuit 10 whose principle configuration is shown in FIG. 1B will be described. Figure 7
FIG. 1B shows an embodiment of the waveform change detection circuit 10 whose principle configuration is shown in FIG. Here, it is assumed that an analog signal having a cycle T is input to the waveform change detection circuit 10, and the same components as those shown in FIG. 4 are indicated by the same symbols.

In the figure, reference numeral 41 is a frequency divider, which generates a clock having a cycle Tx by dividing the clock generated by the clock source 30, 42 is an AND circuit, and the shift register 33 Which calculates and outputs a logical product value of the binary value output by the clock source 30 and the clock generated by the clock source 30, 43 is an AND circuit, and the binary value input to the shift register 33, One that calculates and outputs a logical product value with the clock generated by the clock source 30, 4
A counter 4 counts the high level value output from the AND circuit 42 and resets the count value according to the clock generated by the frequency divider 41. Reference numeral 45 represents a counter, which outputs the AND circuit 43. Which counts the high level value that is generated and resets the count value according to the clock generated by the frequency divider 41. Reference numeral 46 denotes a comparison circuit, which is provided with two counters 44 when the frequency divider 41 generates the clock. , 45 are detected.

In order to execute this detection processing, the comparison circuit 46 is provided corresponding to the binary output of the counter 44 / counter 45, and the binary output value of the counter 44 and the binary output value of the counter 45 are exclusive. A plurality of EOR circuits 47 for calculating and outputting a logical sum value, an OR circuit 48 for calculating and outputting a logical sum value of the output values of these EOR circuits 47, an output value of the OR circuit 48 and a frequency divider Four
AND circuit 49 for calculating and outputting a logical product value with the clock generated by 1.

Next, the operation processing of the waveform change detection circuit 10 of the embodiment shown in FIG. 7 having such a configuration will be described.
In accordance with the operation described in the embodiment of FIG. 4, the binarization circuit 32
Generates a comparison voltage V _b from coming inputted analog signal, using the reference voltage value V _b, by binarizing the analog signal inputted continue to output the shift register 33.

In response to this output processing, the AND circuit 42
Passes the high-level value output from the shift register 33, and the counter 44 resets the count value according to the clock generated by the frequency divider 41 until the next clock is generated. Will be counted. On the other hand, the AND circuit 43 allows the high level value input to the shift register 33 to pass, and the counter 45 causes the frequency divider 4 to operate.
After resetting the count value in accordance with the clock generated by 1, the high level value is counted until the next clock is generated.

As described above, the shift register 33 is
Since the binarized value of the analog signal output from the binarization circuit 32 is shifted and latched by the period of the analog signal, the counter 44 counts when the periodicity of the input analog signal does not change. The count value and the count value counted by the counter 45 have the same value.

The comparator circuit 46 receives the count value output by the counter 44 and the count value output by the counter 45, and the comparator circuit 46 receives the count value and outputs the count value of both. When they match, a low level value is output to indicate that no change occurs in the input analog signal waveform data. When the count values do not match, the input analog signal waveform data changes. A high level value is output to indicate that the occurrence of.

As described above, the waveform change detection circuit 10 shown in FIG. 7 does not use an A / D converter or a large-capacity memory, and according to a simple configuration, the waveform of the input periodic analog signal is obtained. Change can be detected.

FIG. 8 shows a time chart of the embodiment shown in FIG. As shown in this time chart, according to the embodiment of FIG. 7, fluctuations occur in the waveform data of the input analog signal, which causes fluctuations in the output value of the binarization circuit 32. Alternatively, even if the binarized value output from the binarization circuit 32 does not show accurate repeatability due to a sudden change in the waveform data of the input analog signal, the cycle If the count value of the counter 44 and the count value of the counter 45 match during T _x, the fact that no change occurs in the waveform data of the input analog signal is output. Compared to this, it has a characteristic of being resistant to noise.

Next, an embodiment of the waveform change detection circuit 10 whose principle configuration is shown in FIG. 1C will be described. Figure 9
FIG. 1C shows an embodiment of the waveform change detection circuit 10 whose principle configuration is shown in FIG. Here, it is assumed that an analog signal having a period T is input to the waveform change detection circuit 10, and the same components as those shown in FIGS. 4 and 7 are represented by the same symbols. is there.

In the figure, reference numeral 50 denotes an AND circuit which calculates and outputs a logical product value of the binarized value output from the binarization circuit 32 and the clock generated by the clock source 30.
Reference numeral 1 is a counter, which counts the high-level value output from the AND circuit 50 and resets the counted value in accordance with the clock generated by the frequency divider 41, and 52 is a plurality of counters corresponding to the binary output of the counter 51. Shift register for latching while shifting the output value output from the counter 51 by the period of the analog signal in synchronization with the clock generated by the frequency divider 41. Reference numeral 53 denotes a comparison circuit, When the device 41 generates a clock, it detects whether the output value output from the shift register 52 and the input value input to the shift register 52 match.

The comparison circuit 53 calculates the exclusive OR value of the output value and the input value of the shift register 52 and outputs the shift register 52 in order to execute the detection processing.
A plurality of EOR circuits 54 provided for the correspondence and these EOR circuits 54
O for calculating and outputting the logical sum of the output values of the OR circuit 54
R circuit 55, output value of OR circuit 55 and frequency divider 41
A that calculates and outputs the logical product value with the clock generated by
And an ND circuit 56.

Next, the operation processing of the waveform change detection circuit 10 of the embodiment shown in FIG. 9 having such a configuration will be described.
In accordance with the operation described in the embodiment of FIG. 4, the binarization circuit 32
Generates a comparison voltage V _b from coming inputted analog signal, using the reference voltage value V _b, binarizes the analog signal inputted to continue to output the AND circuit 50.

In response to this output processing, the AND circuit 50
Passes the high-level value output from the binarization circuit 32, and the counter 51 resets the count value according to the clock generated by the frequency divider 41 until the next clock is generated. The level value is counted.

In response to this counting process, each shift register 52 shifts the binary output value output from the counter 51 by the period of the analog signal and latches it when the frequency divider 41 generates a clock. According to this latching process, when the periodicity of the input analog signal does not change, the binarized value output from each shift register 52 is the same as the binarized value input to each shift register 52. Will indicate the value of.

From this, the comparator circuit 53 receives the binarized value output from each shift register 52 and the binarized value input to each shift register 52 when the frequency divider 41 generates a clock. When the two binarized values match, a low level value is output to indicate that no change occurs in the input analog signal waveform data, and the two binarized values do not match. At times, a high level value is output to indicate that the waveform data of the input analog signal has changed.

In this way, the waveform change detection circuit 10 shown in FIG. 9 does not use an A / D converter or a large-capacity memory, and according to a simple configuration, the waveform of the input periodic analog signal. Change can be detected.

FIG. 10 shows a time chart of the embodiment shown in FIG. In the figure, the counter output A is the counter 5
1 binary output A (least significant bit), counter output B
Is a binary output B (medium-order bit) of the counter 51, a counter output C is a binary output C (most significant bit) of the counter 51, and 52-A is a shift register 52, 52-B connected to the binary output A. Represents the shift register 52 connected to the binary output B, and 52-C represents the shift register 52 connected to the binary output C. Further, “2 × T _x = T”, and therefore, the shift register 52 having a 2-bit configuration is assumed.

Also in this embodiment, since the waveform data of the input analog signal fluctuates, the binarization circuit 3
The binarized value output from the binarization circuit 32 does not show accurate repeatability because the output value of 2 fluctuates or the waveform data of the input analog signal shows a sudden change. Even if such a situation occurs, if the count value of the counter 51 is repetitive during the period T _x , the fact that no change occurs in the waveform data of the input analog signal is output. Compared with the embodiment of FIG.

In the embodiment disclosed in FIGS. 4/7/9,
Although the configuration in which the waveform data of the input analog signal is changed even once is immediately output is disclosed, the EOR circuit 34 / comparison circuits 46 and 53 are configured to have a structure resistant to noise. By installing a counter in the latter stage,
It is also possible to adopt a configuration in which the count value of this counter, which is reset at a specified cycle, is output on condition that the count value is greater than or equal to the specified value.

While the invention has been disclosed according to the illustrated embodiment,
The present invention is not limited to this. For example, the method of binarizing the input analog signal is not limited to the one disclosed in the embodiment, and for example, when the current sampling voltage is higher than the previous sampling voltage, a high level value, It is also possible to use a binarization method in which a low level value is output when it is small.

[0067]

As described above, according to the present invention,
Since it becomes possible to detect the waveform change of the input periodic analog signal without requiring the A / D converter and the large-capacity memory required in the conventional technology, the input can be performed with a small circuit scale. It becomes possible to detect the waveform change of the incoming periodic analog signal.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a principle configuration diagram of the present invention.

FIG. 3 is an operation explanatory diagram of the present invention.

FIG. 4 is an example of the present invention.

FIG. 5 is an operation explanatory diagram of a binarization circuit.

FIG. 6 is another configuration example of the integrating circuit.

FIG. 7 is another embodiment of the present invention.

FIG. 8 is a time chart of the embodiment of FIG.

FIG. 9 is another embodiment of the present invention.

FIG. 10 is a time chart of the embodiment of FIG.

FIG. 11 is an explanatory diagram of a conventional technique.

[Explanation of symbols]

 10 Waveform Change Detection Circuit 11 Binarization Means 12 Shift Register Means 13 Comparison Means 14 Output Means 15 First Counter Means 16 Second Counter Means 17 Comparison Means 18 Output Means 19 Counter Means 20 Shift Register Means 22 Outputs means

Claims (6)

[Claims] 1. A waveform change detection circuit for detecting a waveform change of an input periodic analog signal, and binarizes the analog signal using a threshold value derived from the analog signal itself in synchronization with a clock. Binarization means
(11), shift register means (12) for latching the output value of the binarizing means (11) while shifting it by the period of the analog signal, and the output value and input value of the shift register means (12) A waveform change detection circuit characterized by comprising a comparison means (13) for detecting occurrence of a waveform change of an analog signal by comparison. 2. A waveform change detection circuit for detecting a waveform change of an input periodic analog signal, and binarizes the analog signal using a threshold value derived from the analog signal itself in synchronization with a clock. Binarization means
(11), shift register means (12) for latching the output value of the binarizing means (11) while shifting it by the period of the analog signal, and the shift register means (12) according to a prescribed counting period.
A first counter means (15) for counting the output value of the shift register means, a second counter means (16) for counting the input value of the shift register means (12) according to the counting cycle, and a first counter means. A comparison means (17) for detecting the occurrence of a waveform change of an analog signal by comparing the count value of (15) with the count value of the second counter means (16). Waveform change detection circuit. 3. A waveform change detection circuit for detecting a waveform change of an input periodic analog signal, and binarizes the analog signal using a threshold value derived from the analog signal itself in synchronization with a clock. Binarization means
(11), counter means (19) for counting the output value of the binarizing means (11) in accordance with a prescribed counting cycle, and binary counting output of the counter means (19). According to the above, by comparing the output value and the input value of the shift register means (20) with a plurality of shift register means (20) for latching while shifting the binary output value by the period of the analog signal, A waveform change detection circuit characterized by comprising a comparison means (21) for detecting the occurrence of a waveform change. 4. The waveform change detection circuit according to claim 1, 2 or 3, wherein the binarizing means (11) comprises a comparator means (23) for binarizing an analog signal by comparing the analog signal with a threshold value. Latch means (24) for latching the output value of the comparator means (23) in synchronization with a clock, and charge / discharge means for generating a threshold value by executing charge / discharge according to the output value of the latch means (24) ( 25) A waveform change detection circuit characterized by being configured by 5. The waveform change detection circuit according to claim 4, further comprising reset means (26) for resetting the charging / discharging voltage of the charging / discharging means (25) for each cycle of the analog signal. Change detection circuit. 6. The waveform change detection circuit according to claim 1, 2, 3, 4 or 5, further comprising: a comparator provided after the comparing means (13, 17, 21).
(3,17,21) Output means that outputs the waveform change occurrence of the analog signal when the occurrence frequency of the waveform change detected is more than the specified value.
A waveform change detection circuit characterized by including (14, 18, 22).