JPH07200094A - Phase synchronization clock distribution circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] To enable circuit design and component placement to be determined without being aware of the clock phase difference between components even when the clock in the circuit board or semiconductor device is high speed. [Structure] A circuit 1 is divided into a plurality of blocks 2, a clock 13 is generated and is distributed to each block 2 as an outbound clock 10, and a clock generator circuit 7 is provided corresponding to each block 2 and corresponds to the clock 13. A clock generation unit 3 including a phase coincidence detection circuit 8 that detects a phase difference from the return clock 11 from the block 2 and outputs phase difference information 12, and a clock generation unit 3 that is provided in each block 2 and receives a forward clock 10 to correspond thereto. The return clock 11 is returned to the phase coincidence detection circuit 8 and the forward clock 10 is used as the phase difference information 1
The variable delay circuit 9 that corrects the phase based on 2 and the clock generator 3 and each block 2 have the same transmission delay in both the forward and backward paths, and the forward clock 10 and the backward clock 1
1, and information transfer means 5 for transferring the phase difference information 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase synchronous clock for distributing a clock of the same phase to a semiconductor device such as a circuit board or a large scale integrated circuit (LSI) on which a plurality of active elements and a plurality of passive elements are mounted. Regarding distribution circuit.

[0002]

2. Description of the Related Art As the frequency of a clock required in a digital circuit increases, a delay due to wiring in a circuit board and a delay inside a semiconductor element such as an LSI increase in comparison with a clock cycle. Therefore, conventionally, a high frequency clock is supported by a detailed design method based on circuit analysis by analog simulation and adjustment of component placement and phase in an actual circuit.

[0003]

However, the detailed design based on circuit analysis by analog simulation accompanying the higher frequency of the clock and the adjustment of component placement and phase in the actual circuit require enormous man-hours as the circuit scale increases. It had the drawback of needing it. The present invention has been made in view of such a background, and allows circuit design and component placement without being aware of the clock phase difference between components even when the clock inside a semiconductor element such as a circuit board or LSI is high speed. An object is to provide a phase-locked clock distribution circuit that can be determined.

[0004]

The invention according to claim 1 is
A clock generation circuit that divides a circuit board on which a plurality of active elements and a plurality of passive elements are mounted or a semiconductor element on which an integrated circuit is formed into a plurality of blocks, generates a reference clock, and distributes the reference clock to each of the blocks as a forward clock. And a plurality of phase detection circuits which are provided corresponding to the respective blocks and which detect the phase difference between the reference clock and the return clock returned from the corresponding block and output phase difference information, respectively. , Provided in each block,
A plurality of phase difference correction circuits that input the forward path clock and return it to the corresponding phase detection circuit as the return path clock, and correct the phase of the forward path clock based on the phase difference information and output it as a block clock; Between the unit and each of the blocks, an information transfer unit for transferring the forward clock, the backward clock, and the phase difference information with the same transmission delay on the forward path and the backward path is provided.

According to a second aspect of the present invention, in the first aspect of the present invention, each block is further divided into a plurality of cells, and each block has a block clock whose phase is corrected by the phase difference correction circuit. A cell clock generation circuit that generates a reference cell clock based on the forward cell clock and distributes it to each of the cells as a forward cell clock, and a return cell clock that is provided corresponding to each of the cells and is returned from the cell corresponding to the reference cell clock. Block common part consisting of a plurality of block phase detection circuits for respectively detecting the phase difference of each cell and outputting cell phase difference information, and provided to each cell, and the forward cell clock is input to the corresponding block phase detection circuit. The return cell clock is folded back and the forward cell clock is phase-corrected based on the cell phase difference information. A plurality of cell phase difference correction circuit that outputs a cell clock Te, between the blocks common unit and each cell, a transmission delay same both forward and backward,
Cell information transfer means for transferring the forward cell clock, the backward cell clock and the cell phase difference information are provided.

According to a third aspect of the invention, in the second aspect of the invention, when the distribution delay of the clock generated between the common unit and each block is T _db , the frequency of the clock is (1 / 2 × T _db ), each of the phase difference correction circuits performs phase correction of the forward path clock based on the phase difference information and outputs it, and each of the cell clock generation circuits outputs a phase by a corresponding phase difference correction circuit. When a reference cell clock having a higher frequency is generated based on the corrected block clock and a distribution delay of the cell clock generated between the block common unit and each cell is T _dc ,
The frequency of the cell clock is set to (1/2 × T _dc ) or less, and each cell phase difference correction circuit performs phase correction of the forward cell clock based on the cell phase difference information and outputs the corrected cell phase difference. .

According to a fourth aspect of the present invention, in the second aspect of the present invention, the reference clock has a reference delay circuit that delays the reference clock by a time that does not exceed a time corresponding to one cycle of the clock. The circuit is characterized in that it detects the phase difference between the clock output from the reference delay circuit and the return clock returned from the corresponding block and outputs phase difference information.

According to a fifth aspect of the present invention, in the second aspect of the invention, each of the phase difference correction circuits has a first configuration having the same configuration.
And a second variable delay circuit, wherein the first variable delay circuit delays the forward clock and outputs the block clock, and inputs the second variable delay circuit to the second variable delay circuit. The variable delay circuit delays the output clock of the first variable delay circuit, returns the output clock to the corresponding phase detection circuit as the return clock, and delays each of the first and second variable delay circuits. Are controlled to be the same on the basis of the phase difference information, and each cell phase difference correction circuit has third and fourth variable delay circuits having the same configuration, and the third variable delay circuit is , The forward cell clock is delayed to output the cell clock, and the cell clock is input to the fourth variable delay circuit, and the fourth variable delay circuit outputs the output clock of the third variable delay circuit. The output clock is then returned to the corresponding cell phase detection circuit as the return cell clock, and the respective delays of the third and fourth variable delay circuits are made equal based on the cell phase difference information. It is characterized by being controlled by.

According to a sixth aspect of the present invention, in the second aspect of the present invention, each of the phase detection circuits outputs the phase difference information between the return clock and the reference clock by advancing the reference clock with respect to the return clock. It is represented by detecting the delay or the advance / lag of the return clock with respect to the reference clock, and transfers the phase difference information to the corresponding phase difference correction circuit through the information transfer means to control the phase difference information and detect the phase of each cell. The circuit, the cell phase difference information between the return cell clock and the reference cell clock,
The advance / delay of the reference cell clock with respect to the return cell clock or the advance / delay of the return cell clock with respect to the reference cell clock is represented by detecting the cell phase difference information through the cell information transfer means. It is characterized in that it is transferred to a phase difference correction circuit for control.

According to a seventh aspect of the present invention, in the second aspect of the invention, the phase difference correction circuit and the cell phase difference correction circuit according to the fifth aspect, and the phase detection circuit and the cell phase detection circuit according to the sixth aspect are provided. First, the delay of the first and second variable delay circuits is set to the minimum or maximum,
Next, the delay amount is increased or decreased in accordance with the variable step of the first and second variable delay circuits, and the phase difference information transferred from the phase detection circuit at that time is such that the backward clock advances from the reference clock. The delay amount is increased or decreased according to the variable step of the first and second variable delay circuits, and the phase difference information indicates that the return clock is the reference clock. If it indicates that the delay is ahead or the lead is ahead, the delay amounts of the first and second variable delay circuits are fixed, and the delays of the third and fourth variable delay circuits are first set. The minimum or maximum is set, and then the delay amount is increased or decreased according to the variable step of the third and fourth variable delay circuits, and the cell phase detection at that time is performed. If the cell phase difference information transferred from the path indicates that the return cell clock is ahead of or behind the reference cell clock, the variable step of the third and fourth variable delay circuits In the case where the cell phase difference information indicates that the return cell clock is behind or ahead of the reference cell clock, the delay amount is increased or decreased according to the third and fourth delays. The feature is that the delay amount of the variable delay circuit is fixed.

[0011]

According to the first aspect of the present invention, the clock output from the clock generation circuit is transferred to each phase difference correction circuit as a forward clock through the information transfer means, and then the backward clock is passed through the information transfer means. Is returned to the corresponding phase detection circuit. Each phase detection circuit detects the phase difference between the reference clock and the return clock and transfers the phase difference information to the corresponding phase difference correction circuit via the information transfer means. As a result, the phase of the block clock output from the phase difference correction circuit of each block matches the phase of the reference clock.

According to the second aspect of the invention, in each block of the first aspect of the invention, the reference cell clock output from the cell clock generating circuit is used as a forward cell clock via the cell information transfer means. After being transferred to each cell phase difference correction circuit, it is returned to the corresponding block phase detection circuit as a return cell clock through the cell information transfer means. Each block phase detection circuit detects the phase difference between the reference cell clock and the return cell clock and transfers the cell phase difference information to the corresponding cell phase difference correction circuit via the cell information transfer means. As a result, the phase of the cell clock output from the cell phase difference correction circuit of each cell matches the phase of the reference cell clock. Further, according to the invention described in claims 3 to 7, in the invention described in claim 2,
High phase synchronization accuracy can be obtained.

[0013]

1 is a conceptual diagram showing the outline of the present invention. In the present invention, a semiconductor element (hereinafter simply referred to as a circuit) 1 such as a circuit board or an LSI is divided into a plurality of blocks 2,
A clock generator 3 that receives a reference clock 6 supplied from the outside and generates a clock having a predetermined cycle; and a clock receiver 4 that is provided in each block 2 and that receives the clock output from the clock generator 3. An information transfer means 5 for transferring information between the clock generator 3 and the clock receiver 4 is provided. Then, the transmission delay generated in the information transfer means 5 is made equal to all the blocks 2, so that the clocks of the same phase are distributed to the respective blocks 2.

The distribution of the clock between the clock generator 3 and the clock receiver 4 is realized by the basic circuit configuration shown in FIG. In FIG. 2, the clock generator 3
Is composed of a clock generation circuit 7 and a phase coincidence detection circuit 8, and the clock reception unit 4 has a variable delay circuit 9. Further, the information transfer means 5 outputs the forward clock 10, the backward clock 11 and the phase difference information 12 to the clock generator 3.
And the clock receiving unit 4.

In such a configuration, the clock 13 output from the clock generation circuit 7 is transferred to the variable delay circuit 9 as the outward clock 10 via the information transfer means 5, and then to the return path via the information transfer means 5. The clock 11 is returned to the phase coincidence detection circuit 8. The phase coincidence detection circuit 8 uses the clock 1 output from the clock generation circuit 7.
3 and return clock 1 returned from the variable delay circuit 9
After detecting the phase coincidence with 1, the phase difference information 12 is transferred to the variable delay circuit 9 via the information transfer means 5.

In this case, the transmission delay of the forward clock 10 and the transmission delay of the backward clock 11 are set to be equal, the transmission delay of the folded backward clock 11 is measured in the phase coincidence detection circuit 8, and this transmission is performed. The phase deviation of the delay from the preset delay is calculated as the phase difference information 12
, The phase of the clock output from the variable delay circuit 9 of each block 2 can be controlled to ½ of the preset delay, and the clock receiving unit 4 sets the preset phase. It is possible to receive a clock that is delayed by 1/2 the delay that has been set. Accordingly, by providing the clock receiving unit 4 in each block 2, it is possible to guarantee that the phases of the clocks in the circuit 1 divided into the plurality of blocks 2 are in agreement.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 3 is a diagram showing a configuration of a circuit 1 to which a phase-locked clock distribution circuit according to an embodiment of the present invention is applied. In this embodiment, the circuit 1 is divided into a plurality of blocks as shown in FIG.
As shown in (b), each block is divided into a plurality of cells.

The circuit 1 comprises a low speed clock distribution section 14, a low speed clock receiving section 15, and a low speed clock information transfer line 1.
8, a high-speed clock distribution unit 16, a high-speed clock reception unit 17, and a high-speed clock information transfer line 19 have a phase synchronization clock distribution circuit. The low-speed clock distribution unit 14 receives the reference clock 6 and distributes the low-speed clock to each block. The low speed clock receiving unit 15 is provided in each block and receives the low speed clock. The low-speed clock information transfer line 18 includes the low-speed clock distribution unit 14
And information is transferred between the low-speed clock receiving unit 15 and the low-speed clock receiving unit 15. The high-speed clock distributor 16 is provided in each block and receives the low-speed clock output from the low-speed clock receiver 15 to generate a high-speed clock. High-speed clock receiver 17
Is provided in each cell and receives the high-speed clock.
The high-speed clock information transfer line 19 transfers information between the high-speed clock distributor 16 and the high-speed clock receiver 17.

Next, FIG. 4 shows the low-speed clock distribution unit 14,
The structure of the low-speed clock receiving unit 15 provided in each block is shown. The low-speed clock distribution unit 14 includes a clock generation circuit 20, a reference delay circuit 21 that generates a delay that does not exceed a time corresponding to one cycle of the low-speed clock 26, and a phase matching detection circuit 22 provided corresponding to each block. It consists of and. Further, the low-speed clock receiving unit 15 has a variable delay circuit 23. Further, a low-speed clock information transfer line 18 including a delay control wiring 24 and a clock distribution wiring 25 is provided between the low-speed clock distribution unit 14 and the low-speed clock reception unit 15 of each block.

In such a configuration, first, the reference clock 6 is input to the clock generation circuit 20, where
A low-speed clock 26 is generated based on the reference clock 6 and distributed to each block and the reference delay circuit 21. The low-speed clock 26 distributed to each block is distributed from the low-speed clock distribution unit 14 to the low-speed clock reception unit 15 of each block via the forward wiring 27 that constitutes the clock distribution wiring 25, and transferred to the variable delay circuit 23. To be done.

Next, the low-speed clock 26 transferred to each variable delay circuit 23 is output as a low-speed clock 28 from each variable delay circuit 23, and the high-speed clock distributor 1 of each cell is output.
6 and each low-speed clock receiving unit 15
From the return wiring 29 that constitutes the clock distribution wiring 25
The low-speed clock 31 is returned to the corresponding phase coincidence detection circuit 22 of the low-speed clock distribution unit 14 via.

In each phase coincidence detection circuit 22, the phase relationship between the low speed clock 30 passing through the reference delay circuit 21 and the folded low speed clock 31 is detected, and the phase difference information 32 is passed through the delay control wiring 24. And is transferred to the variable delay circuit 23 of the corresponding block. In each variable delay circuit 23, the delay amount is varied based on the phase difference information 32 until the phases match. By performing the operation described above for each block, all the phases of the low-speed clock 28 obtained in each block match the phase of the low-speed clock 26 that is the output of the clock generation circuit 20.

Next, FIG. 5 shows a high-speed clock distribution unit 16,
The structure of the high-speed clock receiving unit 17 provided in each cell is shown. The high-speed clock distribution unit 16 includes the low-speed clock reception unit 15 described above, the phase synchronization circuit 33, and the phase matching detection circuit 34 provided corresponding to each cell. In addition, the high-speed clock receiving unit 17 includes the variable delay circuit 3
5 and an in-cell clock distribution unit 36. Further, a high-speed clock information transfer line 19 including a delay control wiring 37 and a clock distribution wiring 38 is provided between the high-speed clock distribution unit 16 and the high-speed clock reception unit 17 of each cell.

In such a configuration, first, the low-speed clock 28 output from the variable delay circuit 23 of the low-speed clock receiving section 15 is converted into the high-speed clock 41 in the phase synchronization circuit 33, and then each cell and each phase. It is distributed to the coincidence detection circuit 34. The high-speed clock 41 distributed to each cell is distributed from the high-speed clock distribution unit 16 to the high-speed clock reception unit 17 of each cell through the forward wiring 42 that constitutes the clock distribution wiring 38, and transferred to the variable delay circuit 35. To be done.

Next, the high-speed clock 41 transferred to each variable delay circuit 35 is output as a high-speed clock 43 from each variable delay circuit 35, distributed to the in-cell clock distribution unit 36 of each cell, and High-speed clock receiver 1
7 to the return wiring 4 constituting the clock distribution wiring 38
The high-speed clock 45 is returned to the corresponding phase coincidence detection circuit 34 of the high-speed clock distribution unit 16 via the circuit 4.

In each phase coincidence detecting circuit 34, the phase relationship between the high speed clock 41 and the folded high speed clock 45 is detected, and the variable delay of the corresponding cell is output as the phase difference information 46 via the delay control wiring 37. It is transferred to the circuit 35. In each variable delay circuit 35, the phase difference information 4
The delay amount is changed based on 6 until the phases match.
By performing the above-described operation for each cell, the phases of the high-speed clock 43 obtained in each cell all match the phase of the high-speed clock 41 that is the output of the phase synchronization circuit 33.

Next, FIG. 6 shows an example of the configuration of the clock generation circuit 20 shown in FIG. The reference clock 6 is a distribution circuit 10 for increasing isolation and fanout.
After passing 0, the signal is branched and transferred to the reference delay circuit 21 and the plurality of low speed clock receiving units 15 shown in FIG. 4 as the low speed clock 26 via the plurality of inverters 101. 7 is an example of the configuration of the reference delay circuit 21 shown in FIG. The low-speed clock 26 transferred from the clock generation circuit 20 is delayed by the inverter array 102, and then, as the low-speed clock 30 via the plurality of inverters 103, the plurality of phase-match detection circuits 22 shown in FIG.
Transferred to.

Further, FIG. 8 shows an example of the configuration of the phase matching detection circuits 22 and 34 shown in FIGS. 4 and 5, respectively. Both are D-type positive edge triggered flip-flops (hereinafter simply referred to as FF) 104.
It is composed by. When the FF 104 shown in FIG. 8 is the phase matching detection circuit 22, the reference delay circuit 21 shown in FIG.
The low-speed clock 30 transferred from is input to the D terminal of the FF 104, and the low-speed clock 31 folded by the variable delay circuit 23 illustrated in FIG. 4 is input to the CK terminal of the FF 104. When the low-speed clock 31 becomes "H" level,
When the low-speed clock 30 is "H" level, the phase difference information 32 output from the Q terminal of the FF 104 is "H" level, and when the low-speed clock 31 is "H" level, the low-speed clock 30 is "L" level. If so, the phase difference information 32 output from the Q terminal of the FF 104 becomes the “L” level. Therefore, the phase difference information 32 changes from "L" level to "
When it goes to the H ”level, the phase of the low-speed clock 30 and the phase of the low-speed clock 31 match each other.
The low speed clock 31 may be input to the D terminal of the FF 104 and the low speed clock 30 may be input to the CK terminal of the FF 104.

On the other hand, when the FF 104 shown in FIG. 8 is the phase coincidence detection circuit 34, the high speed clock 41 transferred from the phase synchronization circuit 33 shown in FIG. 5 is input to the D terminal of the FF 104, and the variable delay circuit shown in FIG. The high-speed clock 45 folded by 35 is input to the CK terminal of the FF 104. If the high-speed clock 41 goes to the “H” level when the high-speed clock 45 goes to the “H” level, Q of the FF 104
The phase difference information 46 output from the terminal becomes “H” level, and when the high speed clock 45 becomes “H” level, if the high speed clock 41 is “L” level, the phase difference information output from the Q terminal of the FF 104. 46 becomes "L" level.
Therefore, the phase difference information 46 changes from "L" level to "H".
When the level becomes high, the phase of the high speed clock 41 and the phase of the high speed clock 45 match. The high speed clock 45 may be input to the D terminal of the FF 104 and the high speed clock 41 may be input to the CK terminal of the FF 104.

Next, FIG. 9 shows an example of the configuration of the variable delay circuits 23 and 35 shown in FIGS. 4 and 5, respectively.
Each of the variable delay circuits 23 and 35 has a switch control circuit 105 and two variable delay circuits 106 and 10.
7 and 7. Each of the variable delay circuits 106 and 107 is composed of a switch 108, a delay generating inverter 109, and an OR gate.

When the circuit shown in FIG. 9 is the variable delay circuit 23, the low-speed clock 26 transferred from the clock generation circuit 20 of the low-speed clock distribution unit 14 shown in FIG. Is entered. The output clock 110 of the variable delay circuit 106 is branched into two, one is the low-speed clock 28 output from the variable delay circuit 23, and the other is input to the variable delay circuit 107. The output clock 111 of the variable delay circuit 107 is returned to the corresponding phase coincidence detection circuit 22 of the low speed clock distribution unit 14 as the low speed clock 31 via the return path wiring 29.

The delay control of the low-speed clock is performed by the variable delay circuit 23 receiving the phase difference information 32 transferred from the phase coincidence detection circuit 22 via the delay control wiring 24. First, by the switch control circuit 105, while making a1 and b1 conductive in the switch 108, the other switches a2-an and b2-b
Open n. This is the state with the least delay.

At this time, assuming that the phase difference information 32 is generated from the Q terminal of the FF 104 constituting the phase coincidence detection circuit 22, if the phase difference information 32 is "L" level, the switch control circuit 105 causes the switch a2 to operate. And b2 are made conductive, and other switches a1, a3 to a
n and b1 and b3 to bn are opened. This operation is repeated until the phase difference information 32 becomes "H" level, and when the phase difference information 32 becomes "H" level, the switch 108
Fix the combination of continuity and open. As a result, the phase of the low-speed clock 28 output from the variable delay circuit 23 matches the phase of the low-speed clock 30 output from the reference delay circuit 21 with the accuracy of the delay amount of the inverter 109.

In the above delay control of the low speed clock, first, the delay amount of the variable delay circuit 23 is set to the minimum state, and the delay amount of the variable delay circuit 23 is gradually increased based on the phase difference information 32. However, conversely, first, the delay amount of the variable delay circuit 23 may be set to the maximum state, and the delay amount of the variable delay circuit 23 may be gradually reduced based on the phase difference information 32. .

On the other hand, when the circuit shown in FIG. 9 is the variable delay circuit 35, the high speed clock 41 transferred from the phase synchronization circuit 33 of the high speed clock distribution unit 16 shown in FIG. It is input to 106. The output clock 110 of the variable delay circuit 106 is branched into two, one is the high-speed clock 43 output from the variable delay circuit 35, and the other is input to the variable delay circuit 107. The output clock 111 of the variable delay circuit 107 is
The high-speed clock 45 is returned to the corresponding phase coincidence detection circuit 34 of the high-speed clock distribution unit 16 via the return line 44.

The delay control of the high-speed clock is performed by the variable delay circuit 35 receiving the phase difference information 46 transferred from the phase coincidence detection circuit 34 via the delay control wiring 37. First, by the switch control circuit 105, while making a1 and b1 conductive in the switch 108, the other switches a2-an and b2-b
Open n. This is the state with the least delay.

At this time, assuming that the phase difference information 46 is generated from the Q terminal of the FF 104 constituting the phase coincidence detection circuit 34, if the phase difference information 46 is "L" level, the switch control circuit 105 causes the switch a2 to operate. And b2 are made conductive, and other switches a1, a3 to a
n and b1 and b3 to bn are opened. This operation is repeated until the phase difference information 46 becomes "H" level, and when the phase difference information 46 becomes "H" level, the switch 108
Fix the combination of continuity and open. As a result, the phase of the high-speed clock 43 output from the variable delay circuit 35 matches the phase of the high-speed clock 41 output from the phase synchronization circuit 33 with the accuracy of the delay amount of the inverter 109. However, to be precise, the phase of the high-speed clock 43 output from the variable delay circuit 35 is the same as that of the high-speed clock 4
It matches the phase after one cycle of 3.

In the above delay control of the high-speed clock, first, the delay amount of the variable delay circuit 35 is set to the minimum state, and the delay amount of the variable delay circuit 35 is gradually increased based on the phase difference information 46. However, conversely, first, the delay amount of the variable delay circuit 35 may be set to the maximum state, and the delay amount of the variable delay circuit 35 may be gradually reduced based on the phase difference information 46. .

Next, FIG. 10 shows an example of the phase correction procedure and the phase relationship of the low-speed clock 28 of each block. 10A shows the phase of the low-speed clock 26 transferred from the clock generation circuit 20 of the low-speed block distribution unit 14 shown in FIG. 4 to each block. The low-speed clock 26 is transferred from the low-speed clock distribution unit 14 to the variable delay circuit 23 of the low-speed clock reception unit 15 of each block via the forward wiring 27. FIG. 10B shows the variable delay circuit 2
3 shows the phase of the low-speed clock 28 output from No. 3. As can be seen from FIGS. 10 (1) and 10 (2), the phase of the low-speed clock 28 is longer than that of the low-speed clock 26 by the delay T _dbl1 (FIG. 10 (a)) in the forward wiring 27.
See only).

Each low-speed clock 26 is returned from each low-speed clock reception section 15 to the corresponding phase coincidence detection circuit 22 as a low-speed clock 31 via the return line 29. FIG. 10C shows the phase of the low-speed clock 31 returned from each low-speed clock receiving unit 15. Figure 10
As can be seen from (2) and (3), the low speed clock 3
The phase of 1 is delayed from the phase of the low-speed clock 28 by a delay T _{db l2} (see FIG. 10A) in the return wiring 29. If the delay amount of the variable delay circuit 23 is set to the minimum state, the phase relationship in this state becomes as shown in FIGS. 10 (3) and (4), and the folded low-speed clock 31 (FIG. 10 (3)). (See FIG. 10) is ahead of the low-speed clock 30 (see FIG. 10 (4)) that has passed through the reference delay circuit 21.

Therefore, the phase difference information 32 output from the phase coincidence detection circuit 22 becomes "L" level, and in the variable delay circuit 23, the switch control circuit 105 (see FIG. 9) operates to increase the delay. . By repeating this operation, the phase of the folded low-speed clock 31 and the phase of the low-speed clock 28 output from the variable delay circuit 23 are delayed, and finally the state shown in FIG. At this time, the phase difference information 32 output from the phase coincidence detection circuit 22 becomes “H” level, and in the variable delay circuit 23, the switch control circuit 105 fixes the state of the switch 108.

The delay amount inserted in the variable delay circuit 23 is 2 × T _dbc , as shown in FIG.
Here, T _dbc is the delay amount of one of the variable delay circuits 106 and 107 that constitute the variable delay circuit 23 shown in FIG. The phase difference between the folded low-speed clock 31 that is first observed in the phase matching detection circuit 22 and the low-speed clock 30 that has passed through the reference delay circuit 21 is expressed by equation (1) (see FIG. 10A). ). T _dbl = T _dbl1 + T _dbl2 (1)

Therefore, the delay T _dbl1 in the outward wiring 27
And the delay T _dbl2 in the return wiring 29 can be designed to be equal, the equation (1) becomes the equation (2) (FIG. 10).
(See (b)). T _dbl = 2 × T _dbl1 (2) Therefore, after delay control, the delay amount from the clock generation circuit 20 of the low-speed clock distribution unit 14 to the output end of the variable delay circuit 23 of the low-speed clock reception unit 15 is ( It is represented by the equation 3) (see FIG. 10E). T _db = (2 × T _dbl + 2 × T _dbc ) / 2 = T _dbc + T _dbl (3) The phase correction procedure of the high speed clock 43 of each cell is also the phase correction of the low speed clock 28 of each block described above. Since the procedure is the same as the procedure, its description is omitted.

Next, FIG. 11 shows an example of the configuration of the phase locked loop 33 shown in FIG. The phase lock circuit 33 includes a phase comparator 112, a filter 113, a variable frequency oscillator 115, and a frequency divider 116. The phase comparator 112 detects a phase difference between the low speed clock 28 transferred from the low speed clock receiving unit 15 and the low speed clock 117 output from the frequency divider 116. The detected phase difference is converted into a voltage by the phase comparator 112, and then input to the filter 113 as the output signal 118 of the phase comparator 112.

The filter 113 suppresses the high frequency component of the signal 118, and the control signal 119 of the frequency variable oscillator 115 is suppressed.
To occur. The variable frequency oscillator 115 uses the control signal 11
The output frequency is controlled by 9. The output signal 120 of the frequency variable oscillator 115 becomes the high-speed clock 41 and the input signal of the frequency divider 116. Frequency divider 1
16 divides the high-speed clock 120 into the low-speed clock 117 with the division ratio 1 / N. The control signal 119 changes the frequency of the output signal 120 of the variable frequency oscillator 115, and consequently changes the phase of the output signal 117 of the frequency divider 116, so that the low frequency clock signal transferred from the low frequency clock receiving unit 15 is changed. It is generated so as to match the phase of the clock 28.
Therefore, finally, the frequency of the output signal 120 of the variable frequency oscillator 115 is controlled to N times the low speed clock 40.

In the phase-locked clock distribution circuit described above, the frequency of the low-speed clock distributed to each block is such that the maximum wiring delay from the low-speed clock distribution unit 14 to the low-speed clock reception unit 15 in each block is 10 ns. , 50 MHz or less can be selected as the low speed clock.
Here, the frequency of the low-speed clock is 40 MHz.
At this time, the variable delay circuit 23 in the low-speed clock receiving unit 15
Is required to be able to vary the delay amount by about 0 to 30 ns.

The frequency of the high-speed clock distributed to each cell in each block is 500 MHz or less as a high-speed clock if the maximum wiring delay from the high-speed clock distributor 16 to the high-speed clock receiver 17 in each cell is 1 ns. Can be selected. Here, set the frequency of the high-speed clock to 4
00 MHz. At this time, the variable delay circuit 35 in the high-speed clock receiver 17 is required to be able to vary the delay amount by about 0 to 3 ns.

Regarding the final phase synchronization accuracy, ignoring the influence of noise superimposed on each signal, the variable delay circuit 23 in the low-speed clock receiving section 15 and the high-speed clock receiving section 17 are ignored.
It depends on the delay variable step width of the variable delay circuit 35 inside. If the delay of the inverter 109 (see FIG. 9) used in the variable delay circuits 23 and 35 can be set to 0.1 ns, an error of 0.1 ns or less in the distribution of the low speed clock and an error of 0.1 ns or less in the distribution of the high speed clock will occur. Occur. Therefore, in the configuration as described above, the maximum is 0.2.
Phase synchronization is possible with accuracy within ns.

More generally, the above-described method for determining the frequency of the low speed clock and the high speed clock is the distribution delay of the low speed clock generated between the low speed clock distribution unit 14 and each block 2 being T _db (s). At this time, the frequency f _{b of the} low speed clock is set within (½ × T _db ) (Hz), and the distribution delay of the high speed clock generated between the high speed clock distribution unit 16 and each cell is T _dc (s). At this time, the frequency f of the high-speed clock is set within (1/2 × T _dc ) (Hz). Although the embodiment of the present invention has been described in detail above with reference to the drawings, the specific configuration is not limited to this embodiment, and there are design changes and the like within a range not departing from the gist of the present invention. Also included in the present invention.

[0050]

As described above, according to the present invention,
High-speed clocks can be supplied in the same phase to a circuit board and a semiconductor element such as an LSI, and circuit design and component placement can be determined without being aware of clock phase differences between components.

[Brief description of drawings]

FIG. 1 is a conceptual diagram showing an outline of the present invention.

FIG. 2 is a block diagram showing a more detailed configuration of a clock generator 3 and a clock receiver 4.

FIG. 3 is a diagram showing a configuration of a circuit 1 to which a phase-locked clock distribution circuit according to an embodiment of the present invention is applied.

FIG. 4 is a block diagram showing a configuration of a low speed clock distribution unit 14 and a low speed clock reception unit 15.

FIG. 5 is a block diagram showing the configurations of a high-speed clock distribution unit 16 and a high-speed clock reception unit 17.

FIG. 6 is a block diagram showing a configuration of a clock generation circuit 20.

7 is a block diagram showing the configuration of a reference delay circuit 21. FIG.

FIG. 8 is a block diagram showing a configuration of phase matching detection circuits 22 and 34.

FIG. 9 is a block diagram showing a configuration of variable delay circuits 23 and 35.

FIG. 10 is a diagram showing an example of a phase correction procedure and a phase relationship of a low speed clock.

FIG. 11 is a block diagram showing a configuration of a phase synchronization circuit 33.

[Explanation of symbols]

 2 blocks 3 clock generation unit 4 clock reception unit 5 information transmission means 7, 20 clock generation circuit 8, 22, 34 phase matching detection circuit 9, 23, 35, 106, 107 variable delay circuit 14 low-speed clock distribution unit 15 low-speed clock reception Part 16 High-speed clock distributor 17 High-speed clock receiver 18 Low-speed clock information transfer line 19 High-speed clock information transfer line 21 Reference delay circuit 24, 37 Delay control wiring 25, 38 Clock distribution wiring 27, 42 Forward wiring 29, 44 Return wiring 33 Phase synchronization circuit 36 In-cell clock distribution unit 100 Distribution circuit 101, 103, 109 Inverter 102 Inverter array 104 FF 105 Switch control circuit 108 Switch 112 Phase comparator 113 Filter 115 Frequency variable oscillator 116 Divider

Claims (7)

[Claims] 1. A circuit board on which a plurality of active elements and a plurality of passive elements are mounted and a semiconductor element on which an integrated circuit is formed are divided into a plurality of blocks, and a reference clock is generated to each block as a forward clock. A clock generation circuit for distributing, and a plurality of phase detection circuits provided corresponding to each of the blocks, for detecting a phase difference between the reference clock and a return clock returned from the corresponding block, and outputting phase difference information respectively. And a common section provided in each block, which inputs the forward clock and returns it to the corresponding phase detection circuit as the backward clock, and also corrects the forward clock as a block clock based on the phase difference information. A plurality of phase difference correction circuits for outputting, and the same for both the forward path and the return path between the common unit and each block. An information transfer means for transferring the forward clock, the backward clock and the phase difference information with one transmission delay. 2. Each of the blocks is further divided into a plurality of cells, and in each of the blocks, a reference cell clock is generated based on a block clock whose phase is corrected by the phase difference correction circuit, and the reference cell clock is used as a forward cell clock. A cell clock generation circuit to be distributed to each cell and a phase difference between the reference cell clock provided for each cell and a return cell clock returned from the corresponding cell are detected to output cell phase difference information. And a block common part made up of a plurality of block phase detection circuits, which is provided in each cell, receives the forward cell clock and returns to the corresponding block phase detection circuit as the backward cell clock, and the forward cell clock is Compensation for multiple cell phase differences that corrects the phase based on the cell phase difference information and outputs it as a cell clock. A circuit, and a cell information transfer unit that transfers the forward cell clock, the backward cell clock, and the cell phase difference information with the same transmission delay in the forward path and the backward path between the block common unit and each cell. The phase synchronization clock distribution circuit according to claim 1, wherein the phase synchronization clock distribution circuit is provided. 3. When the distribution delay of the clock generated between the common section and each of the blocks is T _db , the frequency of the clock is within (1/2 × T _db ) and each phase difference correction circuit Outputs the forward clock with phase correction based on the phase difference information, and each cell clock generation circuit has a higher frequency reference cell based on the block clock phase-corrected by the corresponding phase difference correction circuit. When the clock is generated and the distribution delay of the cell clock generated between the block common part and each cell is T _dc , the frequency of the cell clock is set within ( _½ × T _dc ) and 3. The phase-locked clock distribution circuit according to claim 2, wherein the cell phase difference correction circuit corrects the phase of the forward path cell clock based on the cell phase difference information and outputs it. 4. The reference clock is one of the clocks.
The phase detection circuit has a reference delay circuit that delays by a time that does not exceed the time corresponding to the cycle, and each of the phase detection circuits detects a phase difference between the clock output from the reference delay circuit and the return clock returned from the corresponding block. 3. The phase-locked clock distribution circuit according to claim 2, wherein the phase-difference information is output by each of them. 5. Each of the phase difference correction circuits has first and second variable delay circuits having the same configuration, and the first variable delay circuit delays the forward clock and outputs the block clock. At the same time, the signal is input to the second variable delay circuit, the second variable delay circuit delays the output clock of the first variable delay circuit, and the output clock is used as the return path clock. The respective delays of the first and second variable delay circuits are controlled to be the same on the basis of the phase difference information, and the cell phase difference correction circuits have the same and third delays. 4 variable delay circuit, the third variable delay circuit,
The forward path cell clock is delayed to output the cell clock, and the cell clock is input to the fourth variable delay circuit. The fourth variable delay circuit delays the output clock of the third variable delay circuit. , Its output clock is returned to the corresponding cell phase detection circuit as the return cell clock, and the respective delays of the third and fourth variable delay circuits are controlled to be the same based on the cell phase difference information. 3. The phase-locked clock distribution circuit according to claim 2, wherein: 6. Each phase detection circuit uses the phase difference information between the return clock and the reference clock as a lead / lag of the reference clock with respect to the return clock or a lead / lag of the return clock with respect to the reference clock. It is represented by detecting and transfers the phase difference information to the corresponding phase difference correction circuit via the information transfer means to control the phase difference information, and each cell phase detection circuit controls the return path cell clock and the reference cell clock. The cell phase difference information is represented by detecting a lead / lag of the reference cell clock with respect to the return cell clock or a lead / lag of the return cell clock with respect to the reference cell clock, and the cell is transferred via the cell information transfer means. The phase difference information is transferred to a corresponding cell phase difference correction circuit and controlled. Phase synchronous clock distribution circuit 2 described. 7. A phase difference correction circuit and a cell phase difference correction circuit according to claim 5, and a phase detection circuit and a cell phase detection circuit according to claim 6, wherein the first and second variable The delay of the delay circuit is set to the minimum or maximum, and then the delay amount is increased or decreased according to the variable step of the first and second variable delay circuits, and the phase difference transferred from the phase detection circuit at that time is increased. If the information indicates that the return clock is ahead of or behind the reference clock, the delay amount is increased or decreased according to a variable step of the first and second variable delay circuits, If the phase difference information indicates that the backward clock is behind or ahead of the reference clock, the first and second variable delay circuits Fixing the extension amount, first, leave the delay of the third and fourth variable delay circuit to the minimum or maximum, then the third and fourth
The amount of delay is increased or decreased according to the variable step of the variable delay circuit, and the cell phase difference information transferred from the cell phase detection circuit at that time is that the backward cell clock is ahead of or behind the reference cell clock. If it indicates that the delay amount is increased or decreased according to the variable step of the third and fourth variable delay circuits, the cell phase difference information indicates that the return cell clock is delayed from the reference cell clock. 3. The phase-locked clock distribution circuit according to claim 2, wherein the delay amounts of the third and fourth variable delay circuits are fixed when it indicates that the delay time is in progress or in progress.