JPH07200709A - An arithmetic unit that obtains an integral value or an average value - Google Patents

Abstract

(57) [Abstract] [Purpose] Compared with conventional analog and digital arithmetic units, the integrated value or average value of the input signal can be obtained with high accuracy and without error, and the pure analog type (EN) Provided is an arithmetic unit capable of insulating and holding a signal by using a circuit element which is inexpensive as compared with ones. [Configuration] An input inverting circuit 2a for inverting an input signal with a common voltage as a center, a switch 3 for selectively supplying the output of the input inverting circuit 2a and the input signal to an integrating circuit 4, and an output of the integrating circuit 4 from a common voltage. Two comparators 5a and 5b, which are respectively compared with two high and low reference voltages biased by the same potential to the + and − sides, and their respective comparators 5
Switch 3 is switched every time either the output of a or 5b is inverted.
A switch drive circuit 6 for switching between and, and a counter 12 for performing a counting operation in synchronization with the inversion of the outputs of the comparators 5a and 5b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic unit for obtaining a time integral value or a time average value of detection signals of various detectors such as an analyzer and a flow meter.

[0002]

2. Description of the Related Art As a method for obtaining the time integration value or time average value of detection signals from various detectors, conventionally, a pure analog method using an analog integrating circuit and a detection signal
A digital method of digitizing by a -D converter and integrating is widely adopted.

In a purely analog system, generally,
A current proportional to the input signal is supplied to a charge storage element such as a capacitor for a predetermined time (for example, 1 hour when obtaining an average value for 1 hour) to obtain an integrated voltage. On the other hand, in the digital method, the detection signal is digitized every moment by the A / D converter, and the digital data is taken into the computer and similarly integrated for a predetermined time.

[0004]

Among the above-mentioned conventional methods, in the pure analog method, the charge storage element such as a capacitor forming the integrator requires a large electrostatic capacity corresponding to the integration amount. . Here, there is a tendency that the larger the capacitance of a capacitor, the larger the leakage current, and moreover, the temperature coefficient of the capacitance increases, which causes an integration error in the pure analog system, which is a bottleneck for improving accuracy. It was. Further, in the case of a pure analog type arithmetic unit, generally, when signal isolation and hold are required, it is necessary to incorporate an analog amplifier having each function, which is an obstacle to cost reduction. There is.

On the other hand, in the digital system, the time required for A / D conversion is a blank time with no data in a predetermined time for integration or averaging, and the existence of this blank time causes an error in the calculation result. It is the cause. In addition, the data acquisition period (sampling period) is also a blank time without data, which causes a similar error.

The present invention has been made in view of the above circumstances, and it is possible to obtain a time integrated value or a time average value of an input signal without error as compared with each of the conventional methods under a high resolution. It is another object of the present invention to provide an arithmetic unit that can insulate and hold a signal by using a circuit element that is less expensive than a conventional pure analog method and that obtains an integral value or an average value.

[0007]

A configuration for achieving the above object will be described with reference to FIG. 1 which is an embodiment drawing, and an arithmetic unit for obtaining an integrated value or an average value according to the present invention is an input signal. The input inverting circuit 2a for inverting Vin around the common line voltage Vc, the switch 3 for selectively supplying the output signal of the input inverting circuit 2a and the input signal Vin to the integrating circuit 4, and the integrating circuit 4 Outputs are input respectively, and a reference voltage (for example, V
When c is 0V, the high and low comparators 5a and 5b for which + Vref, −Vref) are set and the outputs of the respective comparators 5a and 5b are input, and the respective comparators 5a and 5b are input.
A switch drive circuit 6 that switches the switch 3 each time any of the outputs of 5b is inverted, and each comparator 5a,
The counter 12 that performs a counting operation in synchronization with the inversion of the output of 5b is provided, and the input signal V
Characterized by being configured to obtain the time integral or time average of in.

Here, as the counting operation of the counter 12 in the present invention, in addition to simple up-counting, the polarity of the output of the integrating circuit 4 with respect to the common voltage is determined from the outputs of the comparators 5a and 5b and the switching state of the switch 3. , Counting up or down according to the result, and counting only an arbitrary polarity according to the result.

[0009]

The input signal or an inverted signal (hereinafter simply referred to as an inverted signal) with respect to the common voltage thereof is integrated by the integrating circuit 4 until it reaches two kinds of high and low reference voltages set in the comparator 5a or 5b. On arrival, switch 3 switches to the opposite signal. That is, the comparators 5a and 5b are inverted each time the integrated value of the input signal or its inverted signal reaches the reference voltage deviated from the common voltage by the same potential, that is, every time the unit integrated amount is reached. Therefore, the counter 12 that performs the counting operation in synchronization with this inversion operation, therefore, one count thereof represents the unit integration amount, and by repeating this operation for a predetermined time (for example, 1 hour), the unit integration amount is changed. It is possible to obtain the integral value of the input signal for the predetermined time or the signal amount (average value) per predetermined time as the resolution.

When performing the above polarity determination, the counter 12 performs addition / subtraction for each unit integration amount according to the polarity determination result. Here, since the integrating circuit 4 only needs to integrate the unit integration amount, it is sufficient that the capacitance required for the charge storage element used therein has a capacitance corresponding to the resolution of the computing unit. The integration circuit 4 switches to the integration on the opposite side every time the integration operation of the unit integration amount is performed by the switch 3, but there is no non-operation time and no blank time in a predetermined time to be integrated or averaged. Furthermore, since the output of the integrated value or the average value is performed by a digital method by supplying a pulse to the counter 12 without using the output of the integrating circuit 4, a special circuit element is used for insulating the input from the output and retaining the data. Achieve the intended purpose without need.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In this example, the voltage of the common line is set to 0V which is the ground level.

The signal input terminal 1 has two operational amplifiers M1.
Input to the input circuit 2 using M2 and M2, one of the operational amplifiers M1 having its positive phase input connected to the signal input terminal 1 and its output being fed back to the negative phase input, and the other operational amplifier M1. The reverse phase input of M2 is connected to the signal input terminal 1, its output is fed back to the input using the same feedback resistance r as the input resistance r, and the positive phase input is grounded. Therefore, the operational amplifier M1 outputs a signal equal to the input signal Vin supplied to the signal input terminal 1, while the operational amplifier M2 outputs the input signal V supplied to the signal input terminal 1.
It functions as an input inverting circuit 2a that outputs a signal -Vin with the polarity of in inverted.

Either the input signal Vin from the input circuit 2 or its inverted signal -Vin is selectively supplied to the input of the integrating circuit 4 via the switch 3. The integrating circuit 4 comprises an operational amplifier M3, an input resistor R and a capacitor C, the signal from the switch 3 is supplied to the negative phase input of the operational amplifier M3, and the positive phase input thereof is grounded.

The output of the integrating circuit 4 is input to both the first and second comparators 5a and 5b. Reference voltages + Vref and -Vref having the same absolute value and different polarities are set to the first and second comparators 5a and 5b, respectively, and the output of the integrating circuit 4 is these two high and low voltages + Vref and -Vref. Always compared to Vref.

The outputs of the comparators 5a and 5b are provided with a switch drive logic circuit 6 for supplying the switching control signal of the switch 3, a pulse generation logic circuit 7 described later, and a unit integration amount polarity determination logic circuit 8 respectively. Are input respectively.

The switch driving logic circuit 6 outputs an L signal from one of the first and second comparators 5a and 5b.
When the level is inverted to the H level, the switch 3 is inverted from the previous state. That is, in the switch 3, each time the output (integrated value) of the integrating circuit 4 reaches + Vref or -Vref, the input to the integrating circuit 4 is either the input signal Vin or its inverted signal -Vin. Operates to switch to the other signal.

The operation of the switch 3 by the control signal from the switch driving logic circuit 6 and each comparator 5a
And 5b and the operation of the integrating circuit 4 will be specifically described,
Now, assuming that the switch 3 is on the a side and the input signal Vin has a positive polarity, the output of the integrating circuit 4 changes in the negative direction in proportion to the integration amount. When the output of the integrating circuit 4 reaches -Vref, the output of the second comparator 5b is inverted from L level to H level. In response to this, the switch driving logic circuit 6 inverts the switch 3 to switch it to the b side.
At this point, the inversion signal −Vin is switched to the integration circuit 4, and the integration output changes to the positive direction this time, and the value is + V.
When it reaches ref, the output of the first comparator 5a is inverted from L level to H level. In response to this, the switch drive logic circuit 6 inverts the switch 3 to the a side again.
In this way, the integrating circuit 4 sequentially repeats the integrating operation in the negative direction and the positive direction. When the input signal Vin has a negative polarity, the output of the integrating circuit 4 changes in the positive direction when the switch 3 is on the a side, and changes in the negative direction when the switch 3 is on the b side, and the integration is sequentially performed in the same manner as above. repeat.

The pulse generation logic circuit 7 includes first and second pulse generation logic circuits.
One pulse is generated each time the output of either of the comparators 5a and 5b is inverted to the H level, and this pulse signal is supplied to the counter 12 via the photo coupler 9.
Therefore, one pulse signal is output from the pulse generation logic circuit 7 every time the absolute value of the integration result of the input signal Vin or its inverted signal -Vin by the integration circuit 4 reaches Vref, that is, the unit integration amount. become.

The unit integration amount polarity determination logic circuit 8 outputs a state signal (a side or b side) of the switch 3 every time one of the outputs of the first and second comparators 5a and 5b is inverted to H level. The polarity of the unit integration amount is determined by. This polarity discrimination output is self-held until the output of either the comparator 5a or 5b is inverted to the H level next time.

As the status signal of the switch 3, the switching control signal from the switch driving logic circuit 6 is added to the delay circuit 1.
It is obtained by taking in via 1 and is in the state before the inversion of the switch 3 at the time of determining the polarity of the unit integration amount. Therefore, the state of the switch 3 until the output of either the comparator 5a or 5b is inverted to the H level is incorporated in the unit integration amount polarity determination logic circuit 8.
The polarity of the unit integration amount is determined based on the state.
Table 1 shows a truth table of the unit integration amount polarity determination logic circuit 8.

[0021]

[Table 1] As is clear from Table 1 and the integration operation of the integration circuit 4 described above, the output of the unit integration amount polarity determination logic circuit 8 matches the polarity of the input signal Vin supplied to the signal input terminal 1.

The discrimination output of the unit integration amount polarity discrimination logic circuit 8 is supplied to the counter 12 via the photocoupler 10. The count mode of the counter 12 is determined by an instruction from the count mode instruction logic circuit 13. Count mode is 1) mode that adds / subtracts according to the positive or negative polarity of the input signal, 2) mode that adds only when the input signal is positive, 3) mode that adds only when the input signal is negative, and 4) input signal It is possible to select four modes, that is, a mode of adding positive or negative polarities, by a count mode command external input. For example, when the mode of 1) is selected, the counter 12 is a unit integration amount polarity determination logic circuit. Based on the output from 8, the pulse generated for each unit integration amount is added or subtracted according to the polarity of the input signal. In this case, the count value of the counter 12 for a predetermined time (for example, 1 hour in the case of 1-hour averaging) represents the total integrated value over both positive and negative polarities of the input signal, with the unit integrated amount as the resolution. . When the mode of 2) or 3) is selected, the count value for the predetermined time of the counter 12 represents the integrated value of only the positive polarity component of the input signal or the integrated value of only the negative polarity component. . Further, when the mode of 4) is selected, the count value for the same time of the counter 12 represents the integral value of the absolute value thereof regardless of the polarity of the input signal.

The count value of the counter 12 is the latch circuit 1
4 and read out at every predetermined time in accordance with a latch command supplied from the outside. In synchronization with this latch command, the counter 12 is preset by a preset command from the outside, and thereafter, the counting operation for the next predetermined time is started. Here, if the output of the latch circuit 14 is converted into an analog signal by the DA converter 15, any of the above integrated values can be output to the outside as an analog output signal.

What is particularly noticeable in the above-described embodiment of the present invention is that the integrator circuit 4 is required to have the ability to integrate only the unit integration amount. Therefore, the capacitor C as a charge storage element used in the integrator circuit 4 is required. The capacity is sufficient if the unit integration amount corresponding to the resolution of the arithmetic unit is satisfied. Therefore, when the resolution is 1/1000 of the full scale, the capacity of the capacitor C is 1/1000 as compared with a conventional arithmetic unit using an analog integrator circuit. It becomes easy to select a product with a small coefficient, and it is possible to easily greatly improve accuracy.

Further, a point to be further noted in the above-mentioned embodiments is that the polarity of the unit integral amount is judged not by the polarity of the input signal itself but by the polarity of the unit integral amount itself. As a result, when the polarity of the input signal itself is discriminated, the polarity of the unit integral amount may be discriminated by the instantaneous polarity of the input signal at the time of the discrimination. The polarity determination method of the embodiment has a high effect of absorbing noise included in the input signal, and the reliability of the polarity determination of the unit integration amount is very high. Further, it is possible to obtain an integrated value of both positive and negative polarities without using a rectifier circuit for an input signal of positive and negative polarities, and to output a calculated value corresponding to the integrated value in both positive and negative polarities. Therefore, unlike the conventional analog computing unit described as "input signal 0 to 1V, output signal 0 to 1V" and the like found in general examples, "input signal 0 to
It is possible to provide a bipolar computing unit such as ± 1 V, output signal 0 to ± 1 V ”.

Furthermore, since the integration or the time average output is performed via the counter 12, the input and the output can be insulated by the photocouplers 9 or 10, and the data retention is also a digital signal. This can be performed using the inexpensive latch circuit 14.

Here, in the above embodiment, an example in which the count mode of the counter 12 can be freely selected from the modes 1) to 4) by the count mode instruction logic circuit 13 has been described. May be fixed in any of these modes, in which case the count mode instruction logic circuit 13 is not needed and the counter may be fixed to operate in the required mode.

The mode required for this arithmetic unit is
In the case of the mode of 4) described above, that is, the mode in which the integrated value or the time average value of the absolute value thereof is obtained regardless of the polarity of the input signal, in addition to the count mode instruction logic circuit 13, the unit integration amount polarity determination logic The circuit 8 is also unnecessary. The present invention includes all of these.

Further, in the above embodiments, the case where the common line is set to the ground level, that is, the voltage of 0 V has been described, but the present invention is not limited to this, and any voltage can be used as the common line. That is, when the operational amplifier used in the circuit has one power supply (for example, 0 V and 10 V), the common line is set to an intermediate value of the one power supply (for example, 5 V). In this case, the polarity reversal of the input signal by the input inversion circuit 2a is inverted around the voltage value of this common line, and the reference voltage of the first and second comparators 5a and 5b is also the voltage value of that common line. The voltage is biased to the plus and minus sides by the same potential centered at.

Furthermore, in the above embodiment, the timing of pulse generation by the pulse generation logic circuit 7 is set such that one of the outputs of the two high and low comparators 5a and 5b is inverted to the H level. The outputs of the comparators 5a and 5b may be inverted to the H level once each. In this case, the unit integration amount is twice that of the above-mentioned embodiment.

[0031]

As described above, according to the present invention,
An input inverting circuit that inverts the input signal centered on the voltage of the common line is provided, and the output signal of the input inverting circuit and the input signal are selectively supplied to the integrating circuit by a switch, and the output of the integrating circuit is set to the common. Two comparators, high and low, with reference voltages that are biased to the positive and negative sides by the same potential with respect to the line voltage, are compared with each other, and each comparator output is inverted. Switch the above switch to
And since the configuration is provided with a counter that performs a counting operation in synchronization with the inversion of the output of each comparator, the capacitance required for the charge storage element used in the integration circuit is
Since the unit integration amount, that is, the resolution equivalent of the arithmetic unit is sufficient, it is only about 1/1000 of that of the conventional pure analog type arithmetic unit, resulting in less leakage current.
It becomes possible to easily select and use one with a small temperature coefficient, and the calculation accuracy is dramatically improved.

Since the input signal is integrated by the integrating circuit in increments of unit increments in the opposite direction, a blank time does not occur during a predetermined time for integration or averaging as in the conventional digital system, which causes There is no error.

Furthermore, since the integration result of the input signal is counted as a discrete quantity for each unit integration quantity and becomes an output,
The input and the output can be insulated by using an inexpensive element such as a photocoupler, and the output data can be held in a digital amount, so that it can be performed by an inexpensive IC such as a latch circuit. Also, CPU and RAM
There is also an advantage that the circuit can be configured by a simple digital logic without requiring a computer function such as.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of an embodiment of the present invention.

[Explanation of symbols]

 1 Signal Input Terminal 2 Input Circuit 2a Input Inversion Circuit 3 Switch 4 Integration Circuit 5a First Comparator 5b Second Comparator 6 Switch Drive Logic Circuit 7 Pulse Generation Logic Circuit 8 Unit Integration Amount Discrimination Logic Circuit 9, 10 Photocoupler 11 Delay circuit 12 Counter 13 Count mode instruction logic circuit 14 Latch circuit 15 DA converter

Claims (1)

[Claims] 1. An input inverting circuit for inverting an input signal centered on a voltage of a common line, a switch for selectively supplying an output signal of the input inverting circuit and the input signal to an integrating circuit, and an integrating circuit of the integrating circuit. Two high and low comparators, to which the outputs are respectively input, and reference voltages which are biased to the plus side and the minus side by the same potential with respect to the voltage of the common line are set, and the outputs of the respective comparators are input, and A switch drive circuit that switches the switch every time one of the outputs of the comparator is inverted, and a counter that performs a counting operation in synchronization with the inversion of the output of each comparator, and the time integrated value of the input signal from the output of the counter An arithmetic unit for obtaining an integrated value or an average value, which is configured to obtain a time average value.