JPH0720101B2 - Cell exchange device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a cell switching device, and more particularly to a so-called ATM (Asy
nchronous Transfer Mode) This is related to cell contention control in a switching device.

[Prior Art] ATM is a network that can support communication services of any speed and any exchange mode, and also targets services that must be continuously transferred in real time, such as voice and video. Therefore, it is necessary to minimize the transfer speed in the switching device, and therefore, the hardware switch is used to execute the cell (packet) switching at high speed (Nikkei Electronics 19
88 1-11 (No.438) pp132-137).

FIG. 2 shows an example of the configuration of a conventional ATM switching apparatus. It should be noted that FIG. 2 shows an exchange configuration of 4 inputs × 4 outputs.

In FIG. 2, the ATM switching apparatus 1 includes a buffer memory 2a to 2d for accumulating cells provided by four forward highways 3a to 3d, and a cell transmission control for controlling cell transmission from the buffer memories 2a to 2d. It is composed of a circuit 4 and a 4-input.times.4-output switch 5 for exchanging cells output from the buffer memories 2a to 2d based on their destinations and outputting them to the backward highways 6a to 6d.

The buffer memories 2a to 2d are for inputting and accumulating cells from the corresponding forward highways 3a to 3d and transmitting the cells in the order of accumulation. However, a plurality of buffer memories may try to send cells to the same destination at the same time, and if they are given to the switch 5 as they are, the switch 5 may perform an erroneous exchange operation, so that cell contention control is performed. There is a need. The cell transmission control circuit 4 performs such competition control. Buffer memory 2a-2d
Sends the destination code of the cell to be sent to the cell sending control circuit 4 before sending the cell, and the cell sending control circuit 4 determines the buffer memory which may send the cell based on the destination code of each cell. Then, the cell transmission right is output to the buffer memory determined by the switch memory, and only the buffer memory to which the cell transmission right is given switches the cell at the transmission timing.
Output to.

The cell transmission control circuit 4 transmits cells only to the buffer memory having the smallest buffer memory number (2a, 2b, 2c, and 2d are the smallest) among a plurality of buffer memories that try to transmit cells of the same destination. The cell transmission control is performed so that the cell is left in the buffer memory without giving the cell transmission right to the remaining buffer memories that try to transmit the cell of the same destination.

For example, at the cell transmission timing at a certain point, as shown in FIG. 3, four cells of the destination “0” are continuously arranged in the buffer memory 2a from the output side, and next, the cells of the destination “1” are accumulated and stored in the buffer memory 2a. In the memory 2b, there is a cell with the destination "0" from the output side, then four cells with the destination "1" are continuously stored, and in the buffer memory 2c there are 5 cells with the destination "2" from the output side.
It is assumed that cells are continuously stored, and five cells of the destination "3" are continuously stored in the buffer memory 2d from the output side. In this case, since there is a cell having the same destination “0” in the buffer memories 2a and 2b in the first cell transmission from this point,
According to the above-mentioned transmission control method executed by the cell transmission control circuit 4, the cells of the buffer memory 2a are preferentially transmitted and the cells of the destination "0" of the buffer memory 2b are not transmitted but remain in the buffer memory 2b as they are. That is, in this first transmission, the cells of the buffer memories 2a, 2c and 2d are transmitted.

Even after this transmission, since the cells of the destination “0” are continuously stored in the buffer memory 2a from the output side, the same cell transmission control as the first time is performed in the second time, the third time, and the fourth time. When executed, only the cells of the buffer memories 2a, 2c and 2d are sent out, and the cells of the destination "0" accumulated at the most output side of the buffer memory 2b remain unsent. In the fifth cell transmission, all the buffer memories 2a to 2d have no cells with the same destination, all the buffer memories 2a to 2d perform the transmission operation, and the cell of the destination "0" of the buffer memory 2b is transmitted for the first time. It will be.

FIG. 4 shows the format of the cell CEL in this conventional example. The cell CEL is composed of a header HEA having a destination code as a connection destination and data DAT obtained by dividing transmission information into blocks. Figure 5 shows the destination and header H
2-bit SIU1 that defines the destination inserted in the EA and
It shows the relationship with the state of SIU0 (these two bits are called the destination code). Therefore, the cell transmission control circuit 4
Performs the control based on the states of these destination codes of the cells to be output by the respective buffer memories 2a to 2d.

FIG. 6 shows a detailed configuration of the switch 5. The switch 5 inputs the cells output from the buffer memories 2a to 2d, performs a switching operation in cell units according to the destination codes SIU1 and SIU0 inserted in the header HEA of the cells, and outputs the backward highways 6a to 6d. Is. In addition,
The switching principle executed by this switch 5 is disclosed in the above-mentioned document.

The switch 5 sorts a plurality of input cells in the ascending order of destination codes, and a backward highway 6a to 6d that connects the plurality of cells sorted by the sorter 5S to a destination according to the destination. Output router
Consisting of 5R. The sorter 5S includes unit switch elements 5a to 5f each having two inputs and two outputs. Router 5R has 2 inputs x
It consists of two output unit switch elements 5g to 5j.

One of the unit switch elements 5a provided in the first stage of the sorter 5S receives cells from the buffer memories 2a and 2b, outputs cells having a small destination code from the upper output terminal to the unit switch element 5c, and A cell with a large code is output from the lower output terminal to the unit switch element 5d. The other unit switch element 5b provided in the first stage receives cells from the buffer memories 2c and 2d, outputs cells having a large destination code from the upper output terminal to the unit switch element 5c, and outputs a small destination code. The cell is output from the lower output terminal to the unit switch element 5d.

Each of the unit switch elements 5c and 5d in the second stage outputs the cell having the smaller destination code among the input cells to the unit switch element 5e provided in the upper side in the third stage, and outputs the cell having the larger destination code. The data is output to the unit switch element 5f provided on the lower side of the third stage. The third-stage unit switch elements 5e and 5f respectively output cells having a smaller destination code among the input cells from the upper output terminal to the first-stage unit switch element 5g of the router 5R, and have a larger destination code. The cell is output from the lower output terminal to the first-stage unit switch element 5h of the router 5R.

In this way, cells having smaller destination codes are sequentially output from the output lines above the third-stage unit switch elements 5e and 5f of the sorter 5S.

As described above, some buffer memories may not send cells, but each unit switch element 5a-
5f operates as if it had the largest destination code for those without cell inputs.

First stage unit switch elements 5g and 5h of router 5R
Outputs to the upper unit switch element 5i of the second stage when the first bit SIU1 indicating the destination of the input cell is logic "0", while the first bit SIU1 has logic "1". In this case, the switching operation is performed so as to output to the lower unit switch element 5j of the second stage. In this way, the unit switch element 5i to which the cells of the destination code “00” and / or “01” are input is output to the upper backward highway 6a when the second bit SIU0 indicating the destination is logic “0”. On the other hand, when the second bit SIU0 has the logic "1", the switching operation is performed so as to output it to the backward backward highway 6b. The unit switch element 5j to which the cells of the destination code “10” and / or “11” are input outputs to the upper backward highway 6c when the second bit SIU0 indicating the destination is logic “0”, while When the second bit SIU0 is logic "1", the switching operation is performed so as to output to the lower backward highway 6d.

Thus, the router 5R outputs each cell to the backward highway according to the destination code.

In addition, each unit switch element 5g ~ 5j of the router 5R,
If there is no cell input on one side, the exchange operation is performed on the input cell and the exchange operation is performed so that there is no cell input on the remaining output line. If there is no one cell input, the exchange operation is performed. No action is taken.

[Problems to be Solved by the Invention] Therefore, in the above ATM switching apparatus, when a plurality of buffer memories try to send cells of the same destination at the same time, as in the description of the sending example using FIG. Only the buffer memory with the smallest number is given a cell transmission right so that cells of the same destination are not simultaneously transmitted. Therefore, when the cells of the same destination compete, the buffer memory that is given the cell transmission right continues to reach the destination, and the buffer memories that try to send other cells of the same destination wait for the cell transmission. It will be.

Therefore, the cells of the same destination are weak against the bursty pattern in which the cells are continuously output from the buffer memory. Also,
The larger the number of the buffer memory, the longer the cell waiting time in the buffer memory, the unevenness occurs in the cell transmission delay time among the buffer memories, and the channel quality deteriorates. Furthermore, the larger the number of the buffer memory, the larger the cell transmission delay time, and therefore the larger the memory capacity, which is not economical.

The present invention has been made in consideration of the above points, and it is an object of the present invention to provide a cell exchange apparatus in which cell transmission delay times are made uniform among buffer memories and the memory capacity of each buffer memory is small. It is a thing.

[Means for Solving the Problems] Basically, a cell exchange apparatus of the present invention follows a plurality of buffer memories for accumulating cells and cells output from the buffer memories according to a destination code inserted in the cells. It consists of a switch to be replaced. However, with this alone, multiple cells with the same destination code cannot be exchanged accurately, so when the cell send signal is given, the cell update signal is sent without deleting the oldest cell when the cell send signal is given. When given, the one that deletes the oldest cell was applied and the following means were provided.

That is, cell sending signal output means for giving a cell sending signal to these buffer memories at a predetermined timing, priority code setting means for setting a priority code indicating a priority order for the cells output from the buffer memory, and the buffer memory The destination codes of the output cells are compared, the highest priority is set for cells that do not have the same destination code, and the priority code setting means sets for multiple cells with the same destination code. Priority is set sequentially from the highest order according to the priority code for that cell, and for the same destination code and priority code, the highest priority is given to the same cell according to the number assigned to the buffer memory. And a priority setting means for setting the order. Further, the cell passing means for passing only the cell from the buffer memory having the highest priority set by the priority setting means and giving it to the switch, and the cell having the highest priority setting by the priority setting means are output. And a cell update signal output means for giving a cell update signal to the buffer memory and deleting the cell from the buffer memory.

The above-mentioned priority code setting means, more specifically,
As the priority code for the next cell transmission, the priority code with the lowest priority is set for the buffer memory that has output the cell with the highest priority set by the priority setting means, and the other priority is set by the priority setting means. For the buffer memory which has output the cells for which the rank is set, the priority code of the rank one class higher than the set rank is set.

[Operation] When the cell transmission signal is given from the cell transmission signal output means, each buffer memory transmits the cell without deleting the oldest cell. Also, the priority code setting means sets a priority code indicating the priority order for the cell.

The priority setting means sets the highest priority to a cell having no identical destination code based on the destination code inserted in the cell from the buffer memory and the priority code set by the priority code setting means. However, for multiple cells with the same destination code, priority is set sequentially from the highest priority according to the priority code, and the destination code and priority code are also assigned to the buffer memory for the same cell. The priority order is set in order from the highest order according to the number, and this priority order setting information is given to the cell passing means, the cell update signal output means and the priority code setting means.

The cell passing means passes only the cell from the buffer memory having the highest priority and gives it to the switch to perform the exchange operation. Further, the cell update signal output means deletes the cell thus given to the switch from the buffer memory.

When one cell sending operation is completed in this way, the priority code setting means sets the buffer memory which has output the cell having the highest priority by the priority setting means for the next cell sending operation. The priority code of the lowest priority is set, and the priority code of the class which is one class higher than the set priority is set for the buffer memory which has output the cell in which another priority is set by the priority setting means.

Embodiment An embodiment of the present invention will be described in detail below with reference to the drawings.

Here, FIG. 7 is a block diagram showing the overall configuration of the cell exchange apparatus according to this embodiment, FIG. 1 is a block diagram showing the detailed configuration of the buffer memory control unit thereof, and FIG. 8 is a selector circuit of this embodiment. FIG. 9 is a schematic diagram showing the format of the output cell, FIG. 9 is a schematic diagram showing a selection command signal for the selector circuit, FIG. 10 is a chart showing the relationship between priority code contents and priority, and FIG. 11 is a buffer. It is a schematic diagram which shows the change of the storage cell content of a memory.

In FIG. 7 in which parts corresponding to those in FIG. 2 are designated by the same reference numerals, the cell exchange apparatus 10 of this embodiment comprises a buffer memory control unit 11 and a switch 5. The buffer memory control unit 11 receives the cells given from the forward highways 3a to 3d and stores them in the internal buffer memories 12a to 12d. The accumulated cells are read out from the buffer memories 12a to 12d in the order in which they are accumulated in accordance with the cell transmission timing, and the cells are controlled by the cell transmission control circuit 13 so that the cells of the same destination are not simultaneously given to the switch 5. , To the switch 5.

The cell transmission control circuit 13 executes contention control as follows. Read cells from the buffer memories 12a-12d,
The priority code is added to the header of the cell, and when there are a plurality of cells with the same destination, the highest priority designated cell is sent to the switch 5 according to the priority code added to the cell, and the unselected cell is selected. Is not sent, but remains in the buffer memory and is read again when the next cell is sent.
At this time, the priority of the cell that has not been transmitted at the last transmission timing that has been read out is increased by 1 and added to the header. For the newly read cell, the priority of the priority code is added to the lowest order to prepare for the next transmission. After that, the transmission control according to the priority code is performed as described above.

The switch 5 provided with the cells subjected to the competition control in this way
In the same manner as in the conventional device, the cells are switched in cell units according to the cell destination and output to the backward highways 6a to 6d.

Next, the detailed configuration of the buffer memory control unit 11 will be described with reference to FIG.

In FIG. 1, the buffer memory control unit 11 includes buffer memories 12a to 12d provided for each input system, priority code addition control circuits 14a to 14d, holding circuits 15a to 15d, and selector circuits 16a to 16d. The gate circuits 171 to 174, a sorter 18 provided in common to each input system, and a priority code detection circuit 19 are provided.

Each of the buffer memories 12a to 12d receives and accumulates cells given from the corresponding forward highways 3a to 3d, and accumulates at the timing when the cell sending signals S2a to S2d are given from the corresponding priority code addition control circuits 14a to 14d. The oldest cells S1a to S1d among the selected cells are read and output to the corresponding selector circuits 16a to 16d. The buffer memory
Different from the conventional device, 12a to 12d perform only cell transmission at the time of cell transmission, and do not perform cell update operation.
That is, the buffer memories 12a to 12d still accumulate the transmitted cells.

The buffer memories 12a to 12d include a priority code addition control circuit 14
When the cell update signals S3a to S3d are given from a to 14d, the oldest stored cell is erased and the stored cell is updated.

Each of the selector circuits 16a to 16d includes a priority code addition control circuit 14
Cells S1a to S1d output from the buffer memories 12a to 12d and the holding circuit 15 based on the selection signals S4a to S4d from a to 14d.
Priority codes FB1a ~ FB1d, FB0a ~ held in a ~ 15d
FB0d is selected alternatively and a priority code is added to the predetermined bit position of the cell. In addition, the priority code addition control circuits 14a to 14d, the buffer memory 12a ~ 12d from the cells S1a ~ S.
Prior to sending 1d, the holding circuits 15a to 15d are given priority code FB.
1a to FB1d and FB0a to FB0d are given and held.

In the case of this embodiment, as shown in FIG. 8, the priority code consists of 2 bits FB1n (n = a to d) and FB0n, and the header HE
It is inserted in an empty area of An, for example, a 2-bit area immediately after the destination SIU1n and SIU0n. Therefore, the selection signals S4a to S4d
As shown in FIG. 9, the first two bits (destination code) of the cell S1n are selected, and at the subsequent bit timing, the first priority code bit FB1 held in the holding circuit 15n is selected.
The contents are determined so that n is selected, and at the subsequent bit timing, the next priority code bit FB0n held in the holding circuit 15n is selected, and thereafter the cell S1n is selected.

In this embodiment, as shown in FIG. 10, the priority code is set such that the smaller the numerical value determined by the priority bits FB1n and FB0n, the higher the priority.

The cells S5a to S5d to which the priority code is added in this way
Is given to Sorter 18. Sorter 18 is a selector circuit
The cells S5a to S5d from 16a to 16d are received by the cell input terminals iDa to iDd, and are sorted in the ascending order of 4 bits based on the contents of the total 4 bits of the cell destination code and the priority code, and the cell output terminal oD1 ~ OD4 to output to the priority code detection circuit 19 and the gate circuits 171-174. Even if there are a plurality of cells having the same 4 bits, all cells are rearranged without ignoring any cells. In this case, the cells from the buffer memory with the smallest number (12a, ..., 12d in ascending order) come to the cell output terminals with the smallest numbers (oD1, ... oD4 in the smallest order). It

Further, the sorter 18 secures a path route in the reverse direction of the path taken by the cells S5a to S5d and uses it for the return route of the priority order signals S71 to S74 given from the priority code detection circuit 19 described later. That is, the priority signals S71 to S of the sorter 18
If the input terminals for the 74 return route are iF1 to iF4 and the output terminals are oFa to oFd, the cell input terminals iDx (x = a to
When d) and the cell output terminal oDy (y = 1 to 4) are connected, the priority signal input terminal iFy and the priority signal output terminal oFx are connected.

As an example of the configuration of the sorter 18, the sorter 5S shown in FIG. 6 is provided with a reverse path route.

The priority code detection circuit 19 uses the cell output terminal oD1 of the sorter 18.
~ Cells S61 to S64 output from oD4 are connected to cell input terminals H1 to H
In step 4, the cell transmission priority control is performed based on the destination code and the priority code of the received cells S61 to S64 so that the cells of the same destination are not output to the switch 5 at the same time. Expressed in bits, the priority signals S71 to S74 are output from the priority signal output terminals F1 to F4 to the priority signal input terminals iF1 to iF4 of the sorter 18 and the gate circuit 17
Output to 1 to 174. The relationship between the 2-bit state of the priority order signal and the priority order is determined in the same manner as the 2-bit state of the priority code and the priority order (see FIG. 10).

The priority control method of cell transmission executed by the priority code detection circuit 19 is as follows.

The destination codes SIU1m and SIU0m of the cells input from the cell input terminals Hm (m = 1 to 4) are all the other cell input terminals H1 to
Destination code SI of cell input from H4 (excluding Hm terminal)
If they do not match U1 and SIU0, the priority signal S7m is output from the priority signal output terminal Fm as a binary signal "00" indicating the highest priority.

Destination code of the cell input from each cell input terminal H1 to H4
When SIU1 and SIU0 are the same for a plurality of cells, the priority codes FB1 and FB0 are further compared with each other, and priority signals are formed and output according to the highest priority indicated by the priority code. If the priority codes are also the same, the priority signal is formed by increasing the priority in ascending order of the cell input terminal numbers (H1, ..., H4) in which cells with the same destination code and priority code are input. And output from the corresponding priority signal output terminal.

That is, the priority code detection circuit 19 first determines the priority order by the destination code, and when the priority order cannot be determined by the destination code, it determines the priority order by the priority code and cannot set the priority order by the priority code. In this case, the priority order is determined by the cell input terminal number.

The gate circuits 171 to 174 receive the cells S61 to S64 output from the corresponding cell output terminals oD1 to oD4 of the sorter 18, and give the priority indicating the highest priority (“00”) from the priority code detection circuit 19. When the priority signal is given, the received cell is passed and given to the switch 5, and when the priority signal of a priority other than this priority is given, the passage of the cell is blocked. In this case, the cells S61 to S64 to which the priority code is added to the switch 5 are
However, since the priority code is inserted in the empty area of the cell, no malfunction occurs.

Priority signal output terminal oF via the return route of sorter 18
Priority signals S7a-S7d (S71-S74d) output from a-oFd
Is equal to any of the above), the priority code addition control circuit 14a
Given to ~ 14d. Priority code addition control circuit 14a-14d
Manages the priority state of the cells read from the buffer memories 12a-12d based on the given priority signals S7a-S7d, and assigns priority codes FB1a-FB1d, FB to the cells.
0a to FB0d are determined, and cells S1 from the buffer memories 12a to 12d are determined.
Before outputting a to S1d, the holding circuits 15a to 15d are provided with the determined priority code and held, and the buffer memories 12a to 12d are updated as necessary.

The priority code addition control circuits 14a to 14d use the priority signal S7a.
Based on S7d to S7d, the priority code to be added is determined as follows, and the update of the corresponding buffer memories 12a to 12d is controlled.

First, the control content executed by the priority code addition control circuit 14n when the priority signal S7n (n = a to d) is a binary number "00" indicating that the priority is highest will be described.

The cell output from the buffer memory 12n is the gate circuit 1
Since it is given to the switch 5 via 7n, the cell update signal S3n is output to the buffer memory 12n to erase the cell from the buffer memory 12n.

When the priority code “11” indicating the lowest priority is set in the holding circuit 15n and the cells compete at the next cell transmission timing, the cell S from the buffer memory 12n
Make sure 1n is not prioritized.

At the next cell transmission time, the cell transmission signal S2n is output to the buffer memory 12n.

By the above processing, the new cell S1n is taken out from the buffer memory 12n at the time of reading the next cell, and the lowest priority code “11” is added to the header.

Next, when the priority signal S7n is other than the binary number "00", that is, when the cell destination is conflicted and the cell is not prioritized, the control content executed by the priority code addition control circuit 14n will be described. explain.

A priority code indicating a rank one class higher than the priority indicated by the returned priority signal S7n is created. Therefore, -1 in decimal notation is added to the returned priority signal S7n (the operation itself is performed in binary number). That is, the degree of selection in the next cell transmission is increased.

The priority code thus obtained is set in the holding circuit 15n.

At the next cell transmission time, the cell transmission signal S2n is output to the buffer memory 12n.

By the above processing, when the next cell is read, the cell that was read once from the buffer memory 12n but was not sent to the switch 5 is read again, and the priority codes FB1n, FB
The priority of 0n is upgraded by 1 and the header of this cell
Added to HEA.

Next, the operation of the cell exchange apparatus 10 having the above configuration will be described.

In the p-th cell reading, as shown in FIG. 11 (A), cells are accumulated in each of the buffer memories 12a to 12d, and the cell of the destination "0" is output from the output side in the buffer memory 12a. 4 cells are continuously stored,
In the buffer memory 12b, there is a cell of the destination "0" from the output side, and then the cells of the destination "1" are continuously stored in three cells. In the buffer memory 12c, the cell of the destination "2" is output. Is continuously stored for four cells, and further, the cell of the destination "3" from the output side is continuously stored for four cells in the buffer memory 12d. Further, it is assumed that in the immediately preceding p−1-th cell reading, there is no cell having the same destination, and the cells output from all the buffer memories 12a to 12d are sent to the switch 5.

From such a state, the p-th cell reading will be described.

Since the priority code addition control circuits 14a to 14d output the cells from all the buffer memories 12a to 12d to the switch 5 in the previous cell transmission, the priority code of the lowest order ("11") is stored in the holding circuits 15a to 15d. ) Is given and it is made to hold.

After that, the priority code addition control circuits 14a to 14d provide the cell output signals S2a to S2d to the corresponding buffer memories 12a to 12d, and the buffer memories 12a in synchronization with the cell output signals.
~ 12d is the oldest stored cell S1n ~ S1d
Is sent. That is, the buffer memory 12a has the destination “0”, the buffer memory 12b has the destination “0”, and the buffer memory 1
2c outputs the cell of the destination "2", and the buffer memory 12d outputs the cell of the destination "3" to the corresponding selector circuits 16a to 16d.

Further, the respective priority code addition control circuits 14a to 14d give the selection signals S4a to S4d shown in FIG. 9 to the corresponding selector circuits 16a to 16d in synchronization with the cell transmission signal. Each selector circuit 16a
~ Selector circuit 16d includes priority code addition control circuits 14a to 14
The switching operation is performed according to the selection signals S4a to S4d from d, and the priority code area FB1 at the predetermined position of the header HEA of the input cell
The priority code “11” is added to a to FB1d and FB0a to FB0d and given to the sorter 18.

The sorter 18 compares the sizes of a total of 4 bits including the destination code and the priority code of the four input cells S5a to S5d, and sorts the cells S61 to S64 sorted in ascending order to the gate circuits 171 to 174 and the priority code. Output to the detection circuit 19. At this time, the cell S5a (S61) from the selector circuit 16a is output from the cell output terminal oD1 of the sorter 18, and the cell S5b (S62) from the selector circuit 16b is output from the cell output terminal oD2.
Is output, the cell S5c (S63) from the selector circuit 16c is output from the cell output terminal oD3, and the cell S5d (S64) from the selector circuit 16d is output from the cell output terminal oD4. The cell S5a from the selector circuit 16a and the selector circuit 16b
4 bits are the same as cell S5b from
In this case, the sorter 18 is the selector circuit with the smaller number.
Treat cell S5a from 16a as small.

The priority code detection circuit 19 detects the destination codes of the cells S61 to S64 input from the cell input terminals H1 to H4, and the cells S63 (S5c) and S64 (S64 (S5) from the cell input terminals H3 and H4 that do not have the same destination.
5d) is given the highest priority, and the priority signal is output from the corresponding priority signal output terminals F3 and F4.
Further, the priority code detection circuit 19 compares the priority codes for the cells S61 (S5a) and S62 (S5b) from the cell input terminals H1 and H2 of the same destination. However, in this case, since the priority codes are also the same, the priority code detection circuit 19 compares the numbers of the cell input terminals H1 and H2, and with respect to the cell S61 (S5a) input from the cell input terminal H1 of a smaller number. And outputs the highest priority signal S71 from the corresponding priority signal output terminal F1 and outputs the highest priority cell input terminal H
The following priority is given to the cell S62 (S5b) input from 2 and the priority signal S72 is output from the corresponding priority signal output terminal F2.

As a result, the gate circuits 171, 173, and 174 operate to open, and cells S61 from the cell output terminals oD1, oD3, and oD4 of the sorter 18,
Only S63 and S64 are output to the switch 5. In this way, cells of the same destination are prevented from being given to the switch 5.

The priority code addition control circuits 14a, 14c and 14d include a sorter 1
The priority signals S7a (S71), S7c (S73) and S7d (S74) showing the highest priority are given through the eight return routes. These priority code addition control circuits 14a, 14c and 14d
When this priority signal is received, the cell update signal S3
a, S3c, S3d corresponding buffer memories 12a, 12c and 12d
To delete the oldest cell. Then the holding circuit
15a, 15c, and 15d are made to hold the priority code ("11") which shows that priority is the lowest.

On the other hand, the priority code addition control circuit 14b is supplied with the priority signal S72 (S7b) indicating the second highest priority via the return route of the sorter 18. Priority code addition control circuit
14b, without updating the cells of the buffer memory 12b,
A priority code indicating a priority one rank higher than the priority indicated by the priority signal, therefore, in this case, a priority code ("00") indicating the highest priority is formed to form a holding circuit.
Give to 15b and hold. Therefore, at this stage, the contents stored in the buffer memories 12a to 12d are as shown in FIG. 11 (B).

After performing such processing, each priority code addition control circuit 14
a to 14d are cell transmission signals S2 for the p + 1-th transmission.
a to S2D are given to the corresponding buffer memories 12a to 12d.

The cells S1a to S1d read from the buffer memories 12a to 12d in synchronization with this cell transmission signal are given to the selector circuits 16a to 16d. At this time, the cell of the destination "0" is transmitted from the buffer memories 12a and 12b, the cell of the destination "2" is transmitted from the buffer memory 12c, and the cell of the destination "3" is transmitted from the buffer memory 12d.

Since the above-mentioned priority code is held in the holding circuits 14a to 14d, the cell S1 from the buffer memories 12a, 12c and 12d.
A priority code (“11”) having the lowest priority is added to the a, S1c, and S1d by the selector circuits 16a, 16c, and 16d, while the cell S1b from the buffer memory 12b has the highest priority by the selector circuit 16b. A priority code ("00") having a higher rank is added.

The sorter 18 compares the size of four bits, which are the destination code and the priority code of the four input cells S5a to S5d, in total, rearranges the cells in ascending order, and rearranges the cells into a gate circuit.
It outputs to 171-174 and the priority code detection circuit 19. At this time, the selector circuit 1 from the cell output terminal oD1 of the sorter 18
Cell S5b (S61) is output from 6b and cell output terminal oD2
The cell S5a (S62) from the selector circuit 16a is output from the cell output terminal oD3 to the cell S5a from the selector circuit 16c.
c (S63) is output, and the cell output terminal oD4 outputs the cell S5d (S64) from the selector circuit 16d.

The priority code detection circuit 19 detects the destination code of the cells S61 to S64 input from the cell input terminals H1 to H4, and is the highest for the cells S63 and S64 from the cell input terminals H3 and H4 that do not have the same destination. The priority signal is given and the priority signal S73, S74 is output from the corresponding priority signal output terminals F3, F4. Also,
The priority code detection circuit 19, the cell input terminal H1 of the same destination,
The priority codes are compared with the cells S61 and S62 from H2, and the highest priority is given to the cell S61 having a high priority input from the cell input terminal H1 and the corresponding priority signal output terminal F1. Outputs the priority signal S71 from the cell input terminal H2, gives the next priority to the cell S62 having a low priority input from the cell input terminal H2, and outputs the priority signal S72 from the corresponding priority signal output terminal F2.

As a result, the gate circuits 171, 173, and 174 operate to open,
Buffer memory 12b via cell output terminal oD1 of sorter 18
From the buffer memory 12c via the cell output terminal oD3, and the cell S64 from the buffer memory 12d via the cell output terminal oD4 to the switch 5. In this way, cells of the same destination are prevented from being given to the switch 5.

The priority code addition control circuits 14b to 14d are connected to the priority signal S7 indicating the highest priority via the return route of the sorter 18.
b (S71), S7c (S73) and S7d (S74) are given. When these priority code addition control circuits 14b-14d receive the priority order signals, they give the cell update signals S3b-S3d to the corresponding buffer memories 12b-12d to delete the oldest cells. After that, the holding circuits 15b to 15d hold the priority code ("11") indicating that the priority is the lowest.

On the other hand, the priority code addition control circuit 14a is supplied with the priority signal S7a (S72) indicating the second highest priority via the return route of the sorter 18. Priority code addition control circuit
14a, without updating the cells of the buffer memory 12a,
A priority code indicating a priority one rank higher than the priority indicated by the priority signal, therefore, in this case, a priority code ("00") indicating the highest priority is formed to form a holding circuit.
It is given to 15a and held.

After performing such processing, each priority code addition control circuit 14
a to 14d are cell transmission signals S2 for the p + 2nd transmission.
a to S2D are given to the corresponding buffer memories 12a to 12d. The contents stored in the buffer memories 12a to 12d at this time are shown in FIG.

At the p + 2nd transmission, the priority codes held in the holding circuits 15a to 15d are different, but the buffer memories 12a to 1d are different.
Since the destinations of the cells transmitted from 2d are all different, the priority code detection circuit 19 detects all the priority signal output terminals F1 to F4.
Outputs the highest priority signal from each buffer memory
The cells from 12a-12d are provided to switch 5.

In the p + 3rd cell transmission, the priority codes added to the cells are all equal, but in this case as well, the destinations are all different, so the priority code detection circuit 19 outputs from all the priority signal output terminals F1 to F4. Outputs the highest priority signal,
The cells from each buffer memory 12a-12d are provided to the switch 5.

As described above, in the p-th and p + 1-th cell readings, cells of the same destination are output from the buffer memories 12a and 12b, but in the p-th time, cells from the buffer memory 12a are given priority and switched. 5, the cells from the buffer memory 12b are given priority and supplied to the switch 5 at the (p + 1) th time.

Therefore, according to the above-described embodiment, even if the destinations of the cells from the plurality of buffer memories are the same for a plurality of times in succession, the cells are alternately selected by changing the priority code to the switch 5. It is possible to provide the same, and it is possible to equalize the waiting time between the buffer memories without causing the sending waiting time of one buffer memory to be significantly longer than the sending waiting time of another buffer memory. As a result, the capacity of the buffer memory determined according to the waiting time can be reduced.

In the above-mentioned embodiment, the one applied to the 4-input × 4-output cell switching apparatus is shown, but the number of inputs and the number of outputs are not limited to this. Further, when the number of inputs and the number of outputs are selected from other than 4, the number of bits of the destination code and the priority code may be determined accordingly.

Further, in the above embodiment, the sorter 18 is provided to secure the route for returning the priority order signal to the priority code addition control circuit.However, the sorter 18 may be provided if another return route can be secured. You may omit it. For example, the selector circuits 16a to 16d add a code indicating the buffer memory number in addition to the priority code, give the added cells to the gate circuits 171 to 174 and the priority code detection circuit 19, and the priority code detection circuit 19 is the destination. And a priority code is formed from the priority code, and based on the code indicating the buffer memory number to which the formed priority signal is added, the priority signal is output to the gate circuit and the priority code addition control circuit corresponding to the buffer memory of that number. May be.

Further, in the above embodiment, the priority code is inserted into the empty area of the cell to provide the priority code detection circuit 19, but the priority code is provided to the priority code detection circuit 19 by a signal line different from that of the cell. You may do it. In this case, it is necessary to clarify the correspondence between the cell and the priority code and give it to the priority code detection circuit.

[Effects of the Invention] As described above, according to the present invention, even if the cell destinations from a plurality of buffer memories are the same a plurality of times in succession, the priority code is changed to update the priority order, and the same priority is obtained. It is possible to change the buffer memory that gives priority to the destination cell, select the cell and give it to the switch 5, uniformize the cell transmission between the buffer memories, and equalize the waiting time between the buffer memories. be able to. As a result, the capacity of the buffer memory determined according to the waiting time can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a buffer memory control unit 11 in an embodiment of the cell switching apparatus according to the present invention, and FIG.
FIG. 4 is a block diagram showing a conventional device, FIG. 3 is a table showing an example of cell storage in a buffer memory in the conventional device, FIG. 4 is a schematic diagram showing a cell format in the conventional device, and FIG. 5 is a destination code and a destination. 6 is a block diagram showing a detailed configuration of the switch 5, FIG. 7 is a block diagram showing a schematic configuration of the above embodiment, and FIG. 8 is a cell format after the priority code is inserted. A schematic diagram, FIG. 9 is a schematic diagram showing selection signals for the selector circuits 16a to 16d, FIG. 10 is a schematic diagram showing the relationship between the priority code and the priority order, and FIG. 11 is the buffer memory of the above embodiment. It is a graph which shows the cell accumulation change of 12a-12d. 5 ... Switch, 10 ... Cell switching device, 11 ... Buffer memory control unit, 12a-12d ... Buffer memory, 13 ... Cell sending control circuit, 14a-14d ... Priority code addition control circuit, 15a-15d …… Holding circuit, 16a to 16d …… Selector circuit, 171 to 174 …… Gate circuit, 18 …… Sort circuit, 19…
... Priority code detection circuit.

Claims (2)

[Claims] 1. A cell is accumulated and is transmitted without deleting the oldest cell when a cell transmission signal is given,
A plurality of buffer memories for deleting the oldest cell when a cell update signal is given, a cell sending signal output means for giving a cell sending signal to these buffer memories at a predetermined timing, and a cell outputted from the buffer memory. The priority code setting means for setting the priority code indicating the priority code is compared with the destination code of the cell output from the buffer memory, and the highest priority is set for the cells having no same destination code. However, for a plurality of cells having the same destination code, priority is set in order from the highest order according to the priority code for the cell set by the priority code setting means, and the destination code and the priority code are also the same. For each cell, the priority is set in order from the highest order according to the number assigned to the above buffer memory. A stage, a cell passing means for passing only the cell from the buffer memory having the highest priority set by the priority setting means, and a switch for exchanging the cell given from the cell passing means according to the destination code. A cell update signal output means for giving a cell update signal to the buffer memory that has output the cell with the highest priority set by the priority setting means and deleting the cell from the buffer memory, The priority code setting means sets the priority code of the lowest priority for the buffer memory which has output the cell having the highest priority set by the priority setting means, as the priority code for the next cell transmission. , The buffer memory which has output the cells to which the other priority is set by the priority setting means is one Cell switching apparatus, characterized in that the the to set the order priority code on the scan. 2. The priority code setting means inserts the set priority code into an empty area of a cell output from the buffer memory and gives the priority code to the priority order setting means. The cell exchange device according to item 1.