JPH07201145A - Disk device - Google Patents

Abstract

(57) [Summary] [Object] To provide a disk device of low power consumption, which is suitable for use in a floppy disk device. [Structure] Stepping motor 13 for driving a head carriage in the radial direction of a disk, and stepping motor 1
Stepping motor 1 by supplying exciting current to coil 3
A stepping motor drive IC 12 that rotationally drives 3;
A stepping motor 13 is provided in a disk device including a control IC 4 that controls the stepping motor drive IC 12 so that the exciting current has a predetermined cycle.
The control IC 4 controls so as to superimpose a pulse having a period extremely shorter than the predetermined period on the exciting current having a predetermined period according to the predetermined rotation period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk device, and more particularly to a disk device suitable for use in a floppy disk device.

[0002]

2. Description of the Related Art FIG. 5 is a timing chart showing drive waveforms of a stepping motor in an example of a conventional disk device.

In general, a floppy disk device, which is an example of a disk device, inputs a signal from a host computer to a control IC through an interface, and the control IC drives the spindle motor driving IC and the stepping motor according to the state of the input signal. The operation of the IC, recording / reproducing IC, etc. is controlled.

In FIG. 5, (A) is a step signal ST input from the host computer to the control IC.
Indicates. When the step signal ST is periodically input, the A-phase excitation pulse A ₁ (see FIG. 5B) which is inverted in synchronization with the rising of the step signal ST and the A-phase excitation pulse A
_The control IC generates a B-phase excitation pulse B ₁ (see FIG. 5D) whose phase is delayed by 90 ° with respect to ₁ .

A-phase excitation pulse A ₁ and B-phase excitation pulse B
₁ is input to the stepping motor drive IC and output through the output circuit, and is also inverted and the bar A
The phase excitation pulse A ₂ (see FIG. 5C) and the bar B phase excitation pulse B ₂ (see FIG. 5E) are output through the output circuit.

The first coil of the stepping motor is driven at both ends by the A-phase exciting pulse A ₁ and the bar A-phase exciting pulse A ₂ , and the second coil is at both ends of the B-phase exciting pulse B _1.
Also, the stepping motor is driven by the B-phase excitation pulse B _{2 and} the excitation current at a predetermined timing flows through each coil, thereby rotating the stepping motor.

As a result, the head carriage mechanism having the recording / reproducing head at the tip moves in the radial direction of the floppy disk to perform a seek operation for seeking a predetermined recording / reproducing position. The waveform of the current consumption I _M of the stepping motor during the seek operation is a rectangular wave waveform that periodically increases at a cycle of ½ of the step signal ST, as shown in FIG. (See (G)).

When the seek operation is stopped, the input of the step signal ST from the host computer is stopped, and the A-phase excitation pulse A ₁ and the B-phase excitation pulse B ₁ are both at high level (bar A-phase excitation pulse A ₂ and bar B-phase excitation pulse B
₍₂ are both at a low level), the rotation of the stepping motor is stopped, and a settling operation is performed to fix the head carriage mechanism at a predetermined position.

By the way, even during the settling time Ts during which the settling operation is performed, the high voltage signal HV which is input to the control IC and controls the on / off of the excitation of the coil of the stepping motor is maintained at the high level. Therefore, since the exciting current in the constant direction continues to flow in each coil of the stepping motor, the waveform of the consumption current I _M of the stepping motor during the settling operation is increased to a constant value as shown in FIG. 5 (G). Increase.

[0010]

However, in the above-mentioned conventional disk device, the current consumption I _M of the stepping motor during the seek operation of the head carriage mechanism (see FIG. 5).
(G)) increases periodically, and during settling operation, it greatly increases to a certain value, resulting in a large power consumption.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a disk device which solves the above problems and reduces the power consumption during seek operation and settling operation.

[0012]

In order to solve the above problems, according to the invention of claim 1, a motor for driving the head carriage in the radial direction of the disk, and an exciting current is supplied to a coil of the motor to provide the motor. In a disk device comprising: a drive unit that rotationally drives the drive unit, and a control unit that controls the drive unit so that the cycle of the exciting current is a predetermined cycle,
To the exciting current of the predetermined cycle according to the predetermined rotation cycle of the motor,
The control means controls so as to superimpose pulses having a period extremely shorter than the predetermined period.

According to another aspect of the present invention, the motor includes a motor for driving the head carriage in the radial direction of the disk and an output transistor, and an exciting current corresponding to the ON resistance of the output transistor is supplied to the coil of the motor. In a disk device including drive means for rotationally driving a motor and a control means for controlling the drive means so that the exciting current has a predetermined cycle, the control means adjusts the on-resistance of the transistor according to the predetermined cycle. A disk device characterized in that it is controlled so as to increase in a predetermined cycle.

[0014]

According to the invention of the constitution described in claim 1,
The exciting current supplied to the coil of the motor is a current obtained by superposing a pulse having an extremely shorter cycle than the exciting current of a predetermined cycle corresponding to a predetermined rotation cycle of the motor.
Therefore, the motor rotates at a predetermined rotation cycle and
Since the pulses are superposed, the exciting current increases or decreases at high speed according to the pulse period, and the average value of the exciting current during the period in which the pulses are superposed decreases.

According to the invention of the structure described in claim 2,
The ON resistance of the output transistor of the driving means is controlled so as to increase at a cycle corresponding to a predetermined cycle of the exciting current. On the other hand, since the exciting current has a rectangular waveform corresponding to the predetermined period and increases in the period corresponding to the predetermined period, the exciting current supplied to the coil of the motor by the driving unit is not increased during the period when the on resistance of the output transistor increases. It becomes difficult to flow and acts to decrease.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic block diagram of the device of the present invention.

In FIG. 1, reference numeral 1 is a host computer which is an external control device. The host computer may be a popular personal computer. From the host computer, various control signals such as a motor-on signal are input to the control IC 4 of the floppy disk device 3, which is a disk device, via the interface 2.

The control IC 4 supplies a recording signal to the recording / reproducing IC 6, and the recording signal is recorded on the floppy disk (not shown) by the recording head 7. The recorded signal of the floppy disk is detected by the reproducing head 8,
It is reproduced by the recording / reproducing IC 6 and supplied to the control IC 4.

The control IC 4 controls the operation of the spindle motor drive IC 10. The spindle motor drive IC 10 rotationally drives the spindle motor 11 whose spindle shaft is chucked by a floppy disk in response to a signal from the control IC 4.

Further, the control IC 4 controls the operation of the stepping motor drive IC 12 which will be described later. The stepping motor drive IC 12 rotates a stepping motor 13 that drives a head carriage mechanism (not shown) including the recording head 7 and the reproducing head 8 in the radial direction of the floppy disk in response to a signal from the control IC 4. To drive. Recording head 7 and reproducing head 8
Can be shared if there is no problem in terms of characteristics.

FIG. 2 is a detailed block diagram of the stepping motor drive IC 12.

The power save signal PS from the control IC 4 is input to the input terminal 21, the A-phase excitation pulse A ₁ is input to the input terminal 22, the B-phase excitation pulse B ₁ is input to the input terminal 23, and the high voltage signal HV is input to the input terminal 24. Each is supplied. The DC power supply voltage V is supplied from the external power supply circuit to the power supply terminal 25.
_DD (= 3.3V) is supplied. A resistor R _X is connected to the terminal 20.

Here, the stepping motor drive IC 12
The oscillator circuit 32 generates a sine wave of about 20 kHz, and the charge pump circuit 33
Supply to. The charge pump circuit 33 includes an oscillator circuit 32.
The DC voltage V _CH boosted based on the sine wave from is generated and output.

The above-mentioned resistor R _X is connected to the band cap reference circuit 34 via the terminal 20,
A reference voltage corresponding to the value of the resistor R _X is generated and output. The level control circuit 35 controls the level of the DC voltage V _CH generated by the charge pump circuit 33 based on this reference voltage.

The power save signal PS is input to the switch circuit 36 via the input terminal 21, and when the power save signal PS is at high level, the charge pump circuit 33 is controlled by the control signal from the level control circuit 35.
The level of the DC voltage V _CH from is controlled.

On the other hand, when the power save signal PS is at the low level, the DC voltage V _CH from the charge pump circuit 33 is not controlled by the control signal from the level control circuit 35, and the DC voltage V _CH at the normal boost level is a signal. It is supposed to be done. This normal boost level is the resistance R
_The level is higher than the level set and controlled by _X.

As described above, the control circuit 37 is supplied with the A-phase excitation pulse A ₁ and the B-phase excitation pulse B ₁ and the high voltage signal H via the terminals 22, 23 and 24.
V is input respectively. These respective signals are supplied to the H bridge circuit (1) 39 and the H bridge circuit (2) 40 at the output stage via the level shift circuit 38.

The H-bridge circuit (1) 39 and the H-bridge circuit (2) 40 each have an output transistor, and the ON resistance of the output transistor is inversely proportional to the DC voltage V _CH from the charge pump circuit 33. Controlled.

The H bridge circuit (1) 39 is an A phase excitation pulse.
Generate That is, the A-phase excitation pulse is applied to the output terminal 27.
Space A₁To the output terminal 28 with the inverted A-phase excitation pulse
Space A ₂Is output. Between both output terminals 27 and 28,
The coil 13a of the stepping motor 13 is connected
It

The H bridge circuit (2) 40 is a B phase excitation pulse.
Generate That is, the B-phase excitation pulse is applied to the output terminal 30.
Space B₁To the output terminal 31 with the inverted B-phase excitation pulse
Space B ₂Is output. Between both output terminals 30 and 31,
The coil 13b of the stepping motor 13 is connected
It

As a result, both coils 13a and 13b are excited, and the stepping motor 13 rotates at a predetermined cycle corresponding to the timing of the exciting pulse. Further, when the high voltage signal HV is set to the low level, the H bridge circuit (1) 39 and the H bridge circuit (2) 40 do not output each excitation pulse, and the excitation is turned on / off by the high voltage signal HV. Controlled.

The power supply terminals 26 and 29 are connected to an external power supply device (not shown) for the motor, and the motor power supply V _M from this external power supply device for the motor is the H bridge circuit (1) 39 and the H bridge circuit. (2) 40 is supplied.

Next, FIG. 3 is a timing chart of the first embodiment of the control by the control IC 4. 3, (A) is a step signal ST from the host computer, (B) is an A-phase excitation pulse A ₁ generated by the control IC 4, and (C) is a stepping motor drive IC 12
Bar A phase excitation pulse A ₂ to produce a, (D) is the B-phase exciting pulses B ₁ generated by the control IC 4, (E) the bar B-phase excitation pulse B ₂ generated by the stepping motor drive IC 12, (F) is The high voltage signals HV and (G) from the control IC indicate the motor current consumption I _M measured in the motor power supply line, respectively.

In the seek operation, when the step signal ST (FIG. 3 (A)) is periodically input from the host computer, the A-phase excitation pulse A ₁ (FIG. 3 ( B)) and the B-phase excitation pulse B whose phase is delayed by 90 ° with respect to the A-phase excitation pulse A ₁ .
₁ (FIG. 3 (D)) is generated by the control IC and supplied to the stepping motor IC 12.

By the way, the A-phase excitation pulse A ₁ is shown in FIG.
As shown in (B), a cycle of the step signal ST, that is, a pulse P having an extremely short cycle as compared with the cycle of the original excitation pulse is superposed for a certain period every half cycle of the step signal ST. That is, the pulse P is superposed for a certain period in the period before the A-phase excitation pulse A ₁ is inverted and the period before the B-phase excitation pulse B ₁ is inverted.

The bar A-phase excitation pulse A ₂ (FIG. 3 (C)) and the bar B-phase excitation pulse B ₂ (FIG. 3 (E)) are the inversions of the A-phase excitation pulse A ₁ and the B-phase excitation pulse B ₁ , respectively. It is supposed to be a waveform. As a result, the stepping motor 1
3 rotates at a predetermined cycle according to the timing of each excitation pulse. Further, the high voltage signal HV is maintained at the high level during the seek operation.

In the figure, when the settling operation is started at time t ₁ , the step signal ST is added to the high voltage signal HV.
Pulse P ', which has an extremely shorter period than the original exciting pulse period, is superimposed as shown in the figure. During this period, the exciting current rapidly increases and decreases.

Therefore, the motor rotates at a predetermined rotation cycle, and during the period in which the pulse P and the pulse P'are superposed, the exciting current increases or decreases at high speed according to the pulse cycle (see FIG. 3 (G)). ), The average value of the exciting current during the period in which the pulses are superposed decreases. Therefore, the current consumption of the motor decreases when the head carriage is driven, that is, when seeking and settling.

Conventionally, the power consumption during seek operation is 3.4 W
However, in this example, it was possible to reduce to 2.24 W. Also, the power consumption during the settling operation is 4.
The value of 0 W is reduced to 1.91 W in this embodiment.
That is, it could be reduced to less than half.

Next, FIG. 4 is a timing chart of the second embodiment of the control by the control IC 4. 4, (A) is a step signal ST from the host computer, (B) is an A-phase excitation pulse A ₁ generated by the control IC 4, and (C) is a stepping motor drive IC 12
Bar A phase excitation pulse A ₂ to produce a, (D) is the B-phase exciting pulses B ₁ generated by the control IC 4, (E) the bar B-phase excitation pulse B ₂ generated by the stepping motor drive IC 12, (F) is The power save signals PS and (G) from the control IC indicate the motor current consumption I _M measured in the motor power supply line, respectively.

Step signal ST from the host computer
When ((A) of FIG. 4) is periodically input, the A-phase excitation pulse A that is inverted in synchronization with the rising of the step signal ST
₁ (FIG. 4 (B)) and the B-phase excitation pulse B ₁ (FIG. 4 (D)) whose phase is delayed by 90 ° with respect to the A-phase excitation pulse A ₁ are generated by the control IC.

On the other hand, bar A phase excitation pulse A ₂ (see FIG. 4)
(C)) and bar B phase excitation pulse B ₂ (Fig. 4 (E))
Are A-phase excitation pulse A ₁ and B-phase excitation pulse B, respectively.
It is assumed to be a waveform with ₁ inverted. As a result, the stepping motor 13 rotates in a predetermined cycle according to the timing of each excitation pulse.

By the way, the power save signal PS (see FIG.
(F)) is A-phase excitation pulse A ₁ and B-phase excitation pulse B
At the same time that ₁ is inverted, it is set to low level, and is set to high level at a predetermined timing before A-phase excitation pulse A ₁ and B-phase excitation pulse B ₁ are inverted again.

During the high level period (set to 700 μsec) of the power save signal PS, the level of the DC voltage V _CH from the charge pump circuit 33 depends on the resistor R _X by the control signal from the level control circuit 35 described above. Switching is controlled by the switch circuit 36 so that the value is set. The value of the resistor R _X was set to 39 kΩ.

Therefore, during the high level period of the power save signal PS, the output DC voltage V _CH of the charge pump circuit 33 is reduced and set lower than the normal value. As a result, the ON resistance of the output transistors of the H-bridge circuit (1) 39 and the H-bridge circuit (2) 40 becomes large, and the exciting currents of the coils 13a and 13b become difficult to flow and decrease.

As a result, as shown in FIG. 4G, the motor current consumption I _M during the high level period of the power save signal PS.
The periodic increase of the
That is, the current consumption of the motor at the time of seek is reduced. Conventionally, the power consumption during the seek operation was 3.4 W, but in the present embodiment, it was possible to reduce it to 2.28 W.

Although the floppy disk device has been described in the above embodiment, the present invention may be applied to a hard disk device, for example.

[0048]

As described above, according to the first aspect of the invention, the exciting current of the coil is a current obtained by superimposing a pulse of an extremely short period on the exciting current of a predetermined period corresponding to the predetermined rotation period of the motor. As a result, the exciting current increases or decreases at high speed according to the pulse cycle, and the average value of the exciting current during the period in which the pulses are superimposed decreases, so that the current consumption of the motor when driving the head carriage decreases.

According to the second aspect of the present invention, the exciting current supplied to the coil of the motor by the driving means is less likely to flow and decreases during the period when the ON resistance of the output transistor of the driving means increases. It has features such as reduced current consumption of the motor during operation.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of a device of the present invention.

FIG. 2 is a detailed block diagram of a stepping motor drive IC 12.

FIG. 3 is a timing chart of the first embodiment of control by the control IC 4.

FIG. 4 is a timing chart of a second embodiment of control by the control IC4.

FIG. 5 is a timing chart showing drive waveforms of a stepping motor of an example of a conventional disk device.

[Explanation of symbols]

 3 Floppy disk device (FDD) 4 Control IC 6 Recording / reproducing IC 10 Spindle motor drive IC 12 Stepping motor drive IC 36 Switch circuit 37 Control circuit 39, 40 H bridge circuit

Claims (2)

[Claims] 1. A motor for driving a head carriage in a radial direction of a disk, a drive means for supplying an exciting current to a coil of the motor to drive the motor to rotate, and a period of the exciting current is set to a predetermined period. And a control means for controlling the drive means, so that a pulse having an extremely short cycle as compared with the predetermined cycle is superimposed on the exciting current having a predetermined cycle according to a predetermined rotation cycle of the motor. A disk device which is controlled by the control means. 2. A motor for driving the head carriage in the radial direction of the disk, and an output transistor. An exciting current according to the on-resistance of the output transistor is supplied to a coil of the motor to rotate the motor. In a disk device comprising a driving means for driving and a control means for controlling the driving means so that the exciting current has a predetermined cycle, the control means controls the on-resistance of the transistor according to the predetermined cycle. A disk device characterized in that it is controlled so as to increase in a predetermined cycle.