JPH07201284A - Vacuum transistor and its manufacture - Google Patents

Abstract

(57) [Abstract] [PROBLEMS] To provide a vacuum transistor capable of forming an emitter part with high accuracy and high reproducibility, and capable of shortening the distance between the emitter part and the base part, and a manufacturing method thereof. A vacuum transistor is formed on a compound semiconductor substrate 10 having (a) (111) B plane and (b) a substrate 10, and has a [-1, -1, 0] direction of the substrate, [-1, Formed in a regular triangular mask area 12 whose sides are orthogonal to the 0, -1] direction and the [0, -1, -1] direction, and (c) the mask area 14.
A triangular pyramid-shaped emitter that is formed of an equilateral triangular opening 14 and (d) a compound semiconductor crystal, and is formed on the opening 14 and each surface is composed of the {1,1,0} plane of the compound semiconductor crystal. Part 16 and (e) compound semiconductor crystal, which is formed on the substrate 10 outside the mask region 14, has a surface facing and parallel to each surface of the emitter part, and has a conductive layer 2 on the top surface.
0 and the base portion 18 and the (g) collector portion 32
Consists of.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vacuum transistor composed of a compound semiconductor and a method of manufacturing the same, to which a so-called selective epitaxial growth technique based on a metal organic chemical vapor deposition method is applied.

[0002]

2. Description of the Related Art A so-called vacuum transistor has been attracting attention as an electronic device capable of high-speed operation and high current density. In this vacuum transistor,
Electrons are emitted from the emitter section in a vacuum to cause the electrons to travel to the collector section, and the arrival of the electrons at the collector section is controlled by the base section. The key to improving the characteristics of the vacuum transistor lies in how accurately the shape of the electron-emitting portion of the emitter section can be reproduced.

Usually, the emitter of a vacuum transistor is
Using photolithography technology and etching technology,
It is formed by finely processing a metal material such as tungsten or molybdenum. The electron-emitting portion of the emitter section needs to have, for example, a pyramid apex or an edge shape.

Further, as the distance between the emitter section and the collector section is shorter, the electrons can be extracted into the vacuum with a lower potential difference, and the energy of the electrons when reaching the collector section can be reduced. . Therefore, the electrons are relaxed and the energy consumed is also reduced. By suppressing the energy of electrons as described above, low power consumption and low heat generation of the vacuum transistor are realized. Further, if the distance between the emitter section and the collector section is short, the distance through which electrons pass becomes short, and high-speed operation becomes possible. Moreover, as the distance between the electron path (electron passage) and the base is shorter, the mutual conductance g _m is also improved.

[0005]

The shape accuracy of the emitter section of the vacuum transistor and the accuracy of the distance between the emitter section, the base section and the collector section are greatly influenced by the photolithography technique and the etching technique. However,
With the current photolithography technology and etching technology, it is extremely difficult to form the emitter portion with high accuracy and high reproducibility. Further, it is extremely difficult to shorten the distance between the emitter portion, the base portion, and the collector portion, and to regulate these distances to constant values with high accuracy and high reproducibility.

Therefore, an object of the present invention is to provide a structure in which the emitter section can be formed with high accuracy and high reproducibility, and the distance between the emitter section, the base section and the collector section can be shortened. It is to provide a vacuum transistor having the same and a manufacturing method thereof.

[0007]

A vacuum transistor according to a first aspect of the present invention for achieving the above object comprises:
(A) a compound semiconductor substrate having a (111) B plane,
(B) The compound semiconductor substrate has a planar shape of an equilateral triangle formed on the (111) B plane, and each side of the equilateral triangle is
[-1, -1, 0] direction of compound semiconductor substrate, [-1,
A mask region orthogonal to the 0, −1] direction and the [0, −1, −1] direction, and (c) a mask region having a regular triangle shape in which each side is parallel to each side of the mask region. The formed opening and the (d) compound semiconductor crystal, which is formed on the (111) B surface of the compound semiconductor substrate exposed at the bottom of the opening and has a triangular pyramid shape, and each surface of the triangular pyramid. Is composed of an emitter portion composed of the {110} plane of the compound semiconductor crystal and (e) a compound semiconductor crystal, and is located outside the mask region and adjacent to the mask region.
1) A base portion formed on the surface B, having a surface facing and parallel to each surface of the emitter portion having a triangular pyramid shape, and having a conductive layer formed on the top surface, and (f) above the emitter portion. And a collector section provided opposite to the emitter section.

Second aspect of the present invention for achieving the above object
The vacuum transistor according to the aspect of (a) is (111) B.
A compound semiconductor substrate having a plane and (b) a (111) B plane of the compound semiconductor substrate, the longitudinal direction of which is coincident with the [0, -1,1] direction of the compound semiconductor substrate, and the width direction of which is the compound. Band-shaped first, second, third, and fourth mask regions that match the [2, -1, -1] direction of the semiconductor substrate;
(C) The width of the first or second mask region, which is made of a compound semiconductor crystal and is formed on the (111) B plane of the compound semiconductor substrate exposed between the first mask region and the second mask region. The shape when cut along a plane parallel to the direction is a parallelogram, the bottom and top of the parallelogram are perpendicular to the [1,1,1] direction of the compound semiconductor crystal, and the hypotenuse is the compound semiconductor crystal. Of (111) B of the compound semiconductor substrate, which is formed of an emitter portion orthogonal to the [0,1,1] direction of (1) and a (d) compound semiconductor crystal and is exposed between the second mask region and the third mask region. The shape of the parallelogram formed on the surface when cut along a plane parallel to the width direction of the second or third mask region is a parallelogram. 1, 1, 1] direction and the hypotenuse of the compound semiconductor crystal On the (111) B plane of the compound semiconductor substrate which is composed of a base portion orthogonal to the [0,1,1] direction and a (e) compound semiconductor crystal and is exposed between the third mask region and the fourth mask region. The parallelogram has a parallelogram shape when cut along a plane parallel to the width direction of the third or fourth mask region, and the lower and upper bottoms of the parallelogram are [1, The collector portion is orthogonal to the [1,1] direction and the hypotenuse is orthogonal to the [0,1,1] direction of the compound semiconductor crystal.

In the vacuum transistor according to the first and second aspects of the present invention, the compound semiconductor substrate, the emitter portion and the base portion can be made of GaAs.

A first aspect of the present invention for achieving the above object
In the method for manufacturing a vacuum transistor according to the aspect of (1), after the mask layer is formed on the (111) B surface of the (b) compound semiconductor substrate, the mask layer is selectively removed,
Each side is in the [-1, -1, 0] direction of the compound semiconductor substrate,
A mask area having an equilateral triangular plane shape orthogonal to the [-1, 0, -1] direction and the [0, -1, -1] direction is formed, and each side is parallel to each side of the mask area. Forming an opening having a regular equilateral triangle shape in the mask region, and (b) comprising a compound semiconductor crystal, having a triangular pyramid shape, and each side of the triangular pyramid has a {110} plane of the compound semiconductor crystal. And an emitter portion composed of (3) is epitaxially grown on the (111) B plane of the compound semiconductor substrate exposed at the bottom of the opening by metal organic chemical vapor deposition, and at the same time, it is made of a compound semiconductor crystal and has a triangular pyramid shape. A base portion having a surface facing and parallel to each surface of the emitter portion is epitaxially grown on the (111) B surface of the compound semiconductor substrate outside the mask region and adjacent to the mask region by a metal organic chemical vapor deposition method. Work When, characterized in that it comprises the step, providing opposed to the process and, (d) above the emitter, the emitter collector unit for forming a conductive layer on the top surface of the (c) the base unit.

A second aspect of the present invention for achieving the above object.
In the method of manufacturing a vacuum transistor according to the aspect of (1), after the mask layer is formed on the (111) B surface of the compound semiconductor substrate, the mask layer is selectively removed so that the longitudinal direction of the compound semiconductor substrate is The width direction is the same as the [0, -1,1,] direction and the width direction is [2, -1,-] of the compound semiconductor substrate.
1] the first, second, third and fourth strips, which coincide with the direction
Forming a mask region, and (b) a compound semiconductor crystal, and the shape when cut by a plane parallel to the width direction of the first or second mask region is a parallelogram. The lower and upper bottoms of the compound semiconductor crystal [1,
Compound semiconductor substrate in which an emitter portion orthogonal to the [1,1] direction and whose hypotenuse is orthogonal to the [0,1,1] direction of the compound semiconductor crystal is exposed between the first mask region and the second mask region. On the (111) B surface of the film is grown epitaxially by metalorganic vapor phase epitaxy, and at the same time, the shape is parallel when cut by a surface made of a compound semiconductor crystal and parallel to the width direction of the second or third mask region. It is a quadrilateral, and the lower and upper bases of the parallelogram are [1, 1, 1
1] direction, and the hypotenuse is [0,
A base portion orthogonal to the [1, 1] direction is epitaxially grown on the (111) B surface of the compound semiconductor substrate exposed between the second mask region and the third mask region by a metal organic chemical vapor deposition method. Further, at the same time, the shape of the compound semiconductor crystal is a parallelogram when cut along a plane parallel to the width direction of the third or fourth mask region, and the lower and upper bases of the parallelogram are Compound semiconductor crystal [1, 1,
1] direction, and the hypotenuse is [0,
A base portion orthogonal to the [1,1] direction is epitaxially grown on the (111) B surface of the compound semiconductor substrate exposed between the third mask region and the fourth mask region by a metal organic chemical vapor deposition method. It is characterized by comprising a process.

In the method of manufacturing a vacuum transistor according to the first and second aspects of the present invention, a compound semiconductor substrate,
The emitter portion and the base portion can be made of GaAs.

[0013]

In the present invention, the compound semiconductor crystal is selectively epitaxially grown on the (111) B plane of the compound semiconductor substrate excluding the mask region. Therefore, it is possible to form the emitter portion and the base portion (and also the collector portion in some cases) having the correct shape and size by forming the mask region having the predetermined shape and size. As a result, the emitter section can be formed with high accuracy and high reproducibility, and the distance between the emitter section, the base section and the collector section can be shortened.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described based on embodiments with reference to the drawings.

Example 1 Example 1 relates to a vacuum transistor according to the first aspect of the present invention and a method for manufacturing the vacuum transistor according to the first aspect. Schematic diagrams of the vacuum transistor of Example 1 are shown in FIGS. 1 and 2. In FIG. 1A,
FIG. 2 is a schematic partial plan view of the vacuum transistor taken along the line AA in FIG. 1B. In addition, FIG. 1B is a schematic partial cross-sectional view when the vacuum transistor is cut along the line BB in FIG. Further, FIG. 2A and FIG. 3A are schematic partial plan views when the vacuum transistor is cut along the line II-II and the line III-III in FIG. 2 (B) and FIG. 3 (B) are similar to FIG. 2 (A) and FIG.
It is a typical partial cross section at the time of cutting a vacuum transistor along line BB of (A) of.

The vacuum transistor of the first embodiment is, for example, G
a compound semiconductor substrate 10 made of aAs and having a (111) B plane, and (111) B of the compound semiconductor substrate 10.
A mask region 12 formed on the surface, an opening 14 formed in the mask region 12, an emitter portion 16, a base portion 1
8 and a collector section 32.

The mask region 12 is made of, for example, SiO ₂ or SiN, and has an equilateral triangular plane shape. Each side of the equilateral triangle is [−1, −
1,0] direction, [−1,0, −1] direction and [0, −]
It is orthogonal to the [1, -1] direction. The opening 14 formed in the mask region 12 has an equilateral triangle shape. Each side of this equilateral triangle is parallel to each side of the mask region 12,
Moreover, it is located equidistant from each side of the mask region 12. At the bottom of the opening 14, (111) of the compound semiconductor substrate 10 is formed.
Side B is exposed. Here, the (111) B plane means a state in which the outermost surface of the compound semiconductor substrate 10 made of, for example, GaAs is made of an As atomic layer.

The emitter section 16 is made of a compound semiconductor crystal (specifically, for example, GaAs crystal). The compound semiconductor substrate 10 has a triangular pyramid shape and is formed on the (111) B surface of the compound semiconductor substrate 10 exposed at the bottom of the opening 14. Each surface of the triangular pyramid is a {110} plane (for example, (-1, 0, -1) plane, (0,
(-1, -1) plane and (-1, -1, 0) plane).

The base portion 18 is made of a compound semiconductor crystal (specifically, for example, GaAs crystal), and is used as the mask region 12.
Compound semiconductor substrate 1 adjacent to the mask region 12 outside the substrate
It is formed on the 0 (111) B surface. Then, each surface 16A, 16B of the emitter section 16 having a triangular pyramid shape,
Surfaces 18A, 18B, 18C facing and parallel to 16C
Have. These planes 18A, 18B and 18C are, for example, (1,0,1) plane, (0,1,1) plane and (1,1,1) plane.
0) plane. A conductive layer 20 is formed on the top surface of the base portion 18.

The collector section 32 is provided above the emitter section 16 so as to face the emitter section 16. The collector portion 32 is formed of, for example, a conductive material formed on the insulating substrate 30 such as glass.

A positive potential is applied to the conductive layer 20 of the base portion 18 while an appropriate voltage is applied to the emitter portion 16.
Thus, the electrons emitted from the emitter section 16 are controlled by the potential applied to the conductive layer 20 of the base section 18 and reach the collector section 32. Therefore, the current flowing from the collector portion 32 to the emitter portion 16 is applied to the base portion 18
It can be controlled by the potential applied to.

The emitter 16 has the shape of a triangular pyramid, and each surface 16A, 16B, 16C of this triangular pyramid ((B) of FIG. 1).
(Reference) is composed of the {110} plane of the compound semiconductor crystal. Therefore, the vertex 16D of the triangular pyramid is accurately defined by the three surfaces 16A, 16B, 16C. Therefore, if the length of one side of the equilateral triangle of the opening 14 is determined, the height of the apex 16D of the emitter 16 is also accurately defined.
The angle formed between these surfaces 16A, 16B and 16C and the surface of the compound semiconductor substrate 10 is 35 degrees. Therefore,
The distance from the apex 16D of the emitter section 16 to the collector section 32 can be accurately and accurately defined.

As shown in FIG. 1B, each surface 18A, 18 of the base portion 18 which faces and is parallel to each surface 16A, 16B, 16C of the emitter portion 16 having a triangular pyramid shape.
The angle formed by B and 18C with the surface of the compound semiconductor substrate 10 is 35 degrees. Therefore, each surface 16A, 16B, 16C of the emitter section 16 having a triangular pyramid shape and each surface 18A, 18 of the base section 18 facing and parallel to these surfaces.
The distance between B and 18C depends on the width of the mask region 12 (the width defined by the outer side of the mask region 12 and the side of the opening 14). Therefore, if the mask region 12 having an accurate width is formed, the distance between these surfaces can be accurately and reproducibly defined.

A method of manufacturing the vacuum transistor of Example 1 will be described below with reference to FIGS. The emitter 16 and the base 18 are basically formed by a so-called selective epitaxial growth technique based on the metal organic chemical vapor deposition (MOCVD) method. Also, MOC
The supply amount of the raw material gas in the VD method is represented by the partial pressure in the MOCVD reactor. The total pressure inside the MOCVD reactor was 0.1 atm.

[Step-100] (Compound semiconductor substrate 1
Preparation of 0) First, on a (111) B surface of a compound semiconductor substrate 10 made of, for example, GaAs, SiO _{2 having} a thickness of about 0.1 μm is formed.
Alternatively, the mask layer 12A made of SiN is deposited by the CVD method or the like (see the schematic perspective view of FIG. 4). Next, the mask layer 12A is selectively removed using a normal photolithography technique and an etching technique to form a mask region 12 having an equilateral triangular plane shape (see FIG. 5). Each side of the equilateral triangle is orthogonal to the [-1, -1, 0] direction, the [-1, 0, -1] direction, and the [0, -1, -1] direction of the compound semiconductor substrate 10. . At the same time, an opening 14 having an equilateral triangle shape and each side of the equilateral triangle being parallel to each side of the mask area 12 is formed in the mask area 12.

Incidentally, FIG. 5A shows the compound semiconductor substrate 10.
5B is a schematic partial plan view of FIG.
FIG. 4A is a schematic partial cross-sectional view of the compound semiconductor substrate 10 or the like when the compound semiconductor substrate 10 or the like is cut along the line BB in (A). In addition, in order to clarify the mask region 12 in the plan view, the mask region 12 is shaded. The same applies to the following plan views.

[Step-110] (Formation of Emitter 16 and Base 18) Next, a compound semiconductor crystal (for example, GaAs crystal) having a triangular pyramid shape, and each surface of the triangular pyramid is a compound semiconductor. The emitter section 16 composed of the crystal {110} plane is epitaxially grown on the (111) B plane of the compound semiconductor substrate 10 exposed at the bottom of the opening 14 by the metal organic chemical vapor deposition method (MOCVD method). At the same time, surfaces 18A, 18 which are made of a compound semiconductor crystal (for example, GaAs crystal) and which face the respective surfaces 16A, 16B, 16C of the emitter section 16 having a triangular pyramid shape.
The base portion 18 having B and 18C is epitaxially grown outside the mask region 12 and on the (111) B surface of the compound semiconductor substrate 10 adjacent to the mask region 12 by the MOCVD method. The conditions of MOCVD are illustrated below. Substrate heating temperature: 800 ° C. Ga raw material gas: TMG (trimethylgallium) supply amount: 3 × 10 ⁻⁶ atm As raw material gas: arsine Raw material gas partial pressure ratio: 200 The raw material gas partial pressure ratio is the MOCVD reaction apparatus inside. It means the pressure ratio of As source gas / Ga source gas.

Under such conditions, the compound semiconductor crystal (for example, GaAs crystal) is formed into (111) of the compound semiconductor substrate 10.
By selectively epitaxially growing on the B surface, the compound semiconductor crystal grows only on the compound semiconductor substrate 10 and in a direction (or an oblique direction) perpendicular to the compound semiconductor substrate 10, and the crystal growth on the mask region 12. do not do. Alternatively, even if the compound semiconductor crystal grows on the mask region 12, the crystal grows only in the vicinity of the edge of the mask region 12. Therefore, so-called selective epitaxial growth can be achieved.

On the (111) B surface of the compound semiconductor substrate exposed at the bottom of the opening, the emitter 16 is MOCVD-formed.
It is formed by epitaxial growth by the method. At this time, a part of the emitter section 16 is formed so that the [-1, -1, 0] direction of the compound semiconductor crystal is parallel to the [-1, -1, 0] direction of the compound semiconductor substrate. Epitaxially grows in the direction toward the center. Similarly,
A part of the emitter section 16 is located at the center of the opening 14 so that, for example, the [0, -1, -1] direction of the compound semiconductor crystal is parallel to the [0, -1, -1] direction of the compound semiconductor substrate. Epitaxially grows in the direction. Further, a part of the emitter section 16 is located at the center of the opening 14 so that, for example, the [-1, 0, -1] direction of the compound semiconductor crystal is parallel to the [-1, 0, -1] direction of the compound semiconductor substrate. Epitaxially grows in the direction toward the part.

By the epitaxial growth of such a compound semiconductor crystal, the shape of the emitter 16 becomes a triangular pyramid, and each surface 16A, 16B, 16C of the triangular pyramid has a {110} plane of the compound semiconductor crystal, for example, (-1, 0, -1) surface,
It is composed of a (0, -1, -1) plane and a (-1, -1,0) plane.

On the other hand, (111) of the compound semiconductor substrate 10 outside the mask region 12 and adjacent to the mask region 12
The base portion 18 is epitaxially grown on the B surface by the MOCVD method. At this time, for example, the [1,1,0] direction of the compound semiconductor crystal is [−1, −] of the compound semiconductor substrate.
A part of the base portion 18 is epitaxially grown in a direction toward the center of the opening 14 so as to be parallel to the [1, 0] direction. Similarly, a compound semiconductor crystal, for example, [0,
[1, 1] direction is [0, -1, -1] of compound semiconductor substrate
A part of the base portion 18 is epitaxially grown in a direction toward the center of the opening 14 so as to be parallel to the direction. Further, a part of the base portion 18 is located at the center of the opening 14 so that, for example, the [1, 0, 1] direction of the compound semiconductor crystal is parallel to the [-1, 0, -1] direction of the compound semiconductor substrate. Epitaxially grows in the direction.

By the epitaxial growth of such a compound semiconductor crystal, the emitter 16 having a triangular pyramid shape is formed.
18A, 18B, 18C facing and parallel to each of the surfaces 16A, 16B, 16C, ie, {110} planes such as (1,0,1) plane, (0,1,1) plane and (1,1) plane. ，
0) plane is formed.

FIG. 2A and FIG. 2B, and FIG. 3A and FIG. 3B are schematic partial plan views and partial cross-sectional views showing a state during the epitaxial growth of the emitter portion 16 and the base portion 18. It shows in (B).

By the above selective epitaxial growth,
As shown in the schematic partial cross-sectional view of FIG. 6A, the emitter section 16 and the base section 18 are formed. The sectional view of FIG. 6 is a schematic partial sectional view of the compound semiconductor substrate 10 or the like when the compound semiconductor substrate 10 or the like is cut along a line similar to the line BB of FIG. Is.

[Step-120] (Formation of Conductive Layer 20) When the emitter 16 has a triangular pyramid shape, the MOC is formed.
The conditions of the VD method are switched to the conditions exemplified below, and the conductive layer 20 made of n-GaAs is formed on the top surface of the base portion 18 (see FIG. 6B). Since the emitter 16 is already formed in the shape of a triangular pyramid, no further crystal growth occurs in this step. Substrate heating temperature: 800 ° C. Ga source gas: TMG (trimethylgallium) supply amount: 3 × 10 ⁻⁶ atm As source gas: arsine source gas partial pressure ratio: 200 n-type dopant: Si ₂ H ₆ supply amount: 1 × 10 ^-8 Atm Then, the conductive layer 20 is selectively removed to form a wiring portion on the conductive layer 20 (not shown).

[Step-130] (Formation of Collector Section 32) After that, the collector section 32 is provided above the emitter section 16 at a position facing the emitter section 16. Collector section 32
Can be formed, for example, by forming a conductive material layer such as ITO on the insulating substrate 30 such as glass by a vacuum deposition method or the like, and then etching the conductive material layer into a desired shape. Finally, the vacuum transistor is completed by assembling the insulating base 30 and the compound semiconductor substrate 10.

Example 2 Example 2 relates to a vacuum transistor according to the second aspect of the present invention and a method for manufacturing the vacuum transistor according to the second aspect. The vacuum transistor of Example 2 is schematically shown in FIG. FIG. 7A is a schematic partial plan view of the vacuum transistor, and FIG.
FIG. 8 is a schematic partial cross-sectional view of the vacuum transistor taken along line BB in FIG. 7A.

The vacuum transistor of the second embodiment is, for example, G
a compound semiconductor substrate 10 made of aAs and having a (111) B plane, strip-shaped first, second, third and fourth mask regions 40, 42, 44, 46, and an emitter section 50.
And a base portion 52 and a collector portion 54.

The strip-shaped first, second, third and fourth mask regions 40, 42, 44 and 46 are made of, for example, SiO ₂ or SiN, and are formed of (111) of the compound semiconductor substrate 10.
It is formed on the B surface, the longitudinal direction thereof coincides with the [0, -1, 1] direction of the compound semiconductor substrate 10, and the width direction thereof coincides with the [2, -1, -1] direction of the compound semiconductor substrate 10. They match (see Figure 8).

The emitter section 50 is made of a compound semiconductor crystal (eg, GaAs crystal) and is exposed between the first mask region 40 and the second mask region 42 on the (111) B plane of the compound semiconductor substrate 10. Has been formed. And
The shape of the parallelogram when cut along a plane parallel to the width direction of the first or second mask region is a parallelogram, and the bottom and top bottoms 50B of the parallelogram are [1, 1, 1
1] direction and the hypotenuses 50A and 50D are orthogonal to the [0, 1, 1] direction of the compound semiconductor crystal (see the enlarged partial cross-sectional view of FIG. 7C).

The base portion 52 is also made of a compound semiconductor crystal (for example, GaAs crystal) and is exposed between the second mask region 42 and the third mask region 44 on the (111) B plane of the compound semiconductor substrate 10. Has been formed. The shape of the parallelogram when cut along a plane parallel to the width direction of the second or third mask region is a parallelogram, and the lower and upper bases of the parallelogram are [1, 1, 1] direction, and the hypotenuse (for example, reference numeral 52A) is orthogonal to the [0,1,1] direction of the compound semiconductor crystal.

The collector portion 54 is also made of a compound semiconductor crystal (for example, GaAs crystal) and is exposed between the third mask region 44 and the fourth mask region 46 on the (111) B plane of the compound semiconductor substrate 10. Has been formed. And
The shape of the parallelogram when cut along a plane parallel to the width direction of the third or fourth mask region is a parallelogram, and the bottom and top of the parallelogram are [1,1,1] of the compound semiconductor crystal. It is orthogonal to the direction, and the hypotenuse (for example, reference numeral 54A) is orthogonal to the [0,1,1] direction of the compound semiconductor crystal.

A positive potential is applied to the base portion 52 while an appropriate voltage is applied to the emitter portion 50. As a result, the electrons emitted from the edge portion 50A of the emitter portion 50 are controlled by the potential applied to the base portion 52,
The collector section 54 is reached. Therefore, the current flowing from the collector 54 to the emitter 50 can be controlled by the potential applied to the base 52.

The edge portion 50C of the emitter portion 50 is, for example, (-)
1, 0, -1) plane 50D is constituted by a ridge intersecting. Therefore, the edge portion 50C of the emitter portion 50 is accurately defined. The angle formed by the (0,1,1) plane 50D and the surface of the compound semiconductor substrate 10 is 35 degrees.

A slope of the base portion 52 (for example, reference numeral 5)
2A) and the slope of the collector portion 54 (for example, reference numeral 5).
4A) and the surface of the compound semiconductor substrate 10 form an angle of 3
It is 5 degrees. Therefore, the distance between the first mask region 40 and the second mask region 42, the distance between the second mask region 42 and the third mask region 44, and the third mask region 44 and the fourth mask region 44.
If the distance between the mask regions 46 is accurately defined, the distance between the emitter portion 50, the base portion 52, and the collector portion 54 can be accurately and reproducibly controlled.

Hereinafter, a method of manufacturing the vacuum transistor of Example 2 will be described with reference to FIG. The emitter 5
0, the base portion 52, and the collector portion 54 are formed by the metal organic chemical vapor deposition method (MOCVD method) as in the first embodiment.
The so-called selective epitaxial growth technology based on is applied. Further, the supply amount of the raw material gas in the MOCVD method is represented by the partial pressure in the MOCVD reactor. MO
The total pressure in the CVD reactor was 0.1 atm.

[Step-200] (Compound semiconductor substrate 1
Preparation of 0) First, on a (111) B surface of a compound semiconductor substrate 10 made of, for example, GaAs, SiO _{2 having} a thickness of about 0.1 μm is formed.
Alternatively, the mask layer 12A made of SiN is deposited by the CVD method or the like (see the schematic perspective view of FIG. 4). Next, the mask layer 12A is selectively removed using a normal photolithography technique and an etching technique to remove the first strip-shaped mask,
Second, third and fourth mask regions 40, 42, 44, 4
6 is formed (see the schematic perspective view of FIG. 8). In these mask regions, the longitudinal direction coincides with the [0, -1, 1] direction of the compound semiconductor substrate 10 and the width direction coincides with the [2, -1, -1] direction of the compound semiconductor substrate 10. There is.

[Step-210] (Formation of Emitter Section 50, Base Section 52, and Collector Section 54) Next, the emitter section 50, the base section 52, and the collector section 54 made of a compound semiconductor crystal (for example, GaAs crystal).
Of the compound semiconductor substrate 10 exposed between the mask regions.
On the (111) B surface of the metal-organic vapor phase epitaxy method (MOCVD
Method) for epitaxial growth. The conditions of MOCVD are illustrated below. Substrate heating temperature: 800 ° C. Ga source gas: TMG (trimethylgallium) supply amount: 3 × 10 ⁻⁶ atm As source gas: arsine source gas partial pressure ratio: 200

Under such conditions, the compound semiconductor crystal (for example, GaAs crystal) is formed into (111) of the compound semiconductor substrate 10.
By the selective epitaxial growth on the B surface, the compound semiconductor crystal grows only on the compound semiconductor substrate 10 and in a direction (or an oblique direction) perpendicular to the compound semiconductor substrate 10, and does not grow on the mask region. . Alternatively, even if the compound semiconductor grows on the mask region, the crystal grows only in the vicinity of the edge of the mask region. Therefore, so-called selective epitaxial growth can be achieved.

On the (111) B plane of the compound semiconductor substrate exposed between the mask regions, the emitter section 50, the base section 52 and the collector section 54 are formed by epitaxial growth by MOCVD. At this time, the compound semiconductor crystal is epitaxially grown so that, for example, the [0,1,1] direction of the compound semiconductor crystal made of GaAs is a slope and the (111) plane is a top surface. As a result, the emitter section 5 is formed in a plane including the width direction of the mask region.
0, the base portion 52 and the collector portion 54 are cut into parallelograms in cross section.

Thereafter, electrodes (not shown) are formed on the emitter section 50, the base section 52 and the collector section 54.

Although the present invention has been described based on the preferred embodiments, the present invention is not limited to these embodiments. The various conditions described in the embodiments are examples and can be changed as appropriate. Crystal planes and directions are examples,
It can be replaced with an equivalent crystal plane or orientation. In the embodiment, GaAs is formed on the compound semiconductor substrate made of GaAs.
A compound semiconductor crystal made of I was epitaxially grown. In addition, as a combination of a compound semiconductor substrate and a compound semiconductor crystal, as a compound semiconductor substrate, I
A combination of nP and AlGaInAs can be used as the compound semiconductor crystal.

In the vacuum transistor according to the first aspect of the present invention, if a fluorescent material layer is formed on the surface of the collector portion 32, for example, a display device capable of displaying images, characters and the like with high density can be easily provided. Can be made.

[0054]

According to the present invention, the emitter section can be formed with high accuracy and high reproducibility, and the distance between the emitter section, the base section and the collector section can be shortened. In the present invention, 1
A vacuum transistor can be manufactured by forming a mask layer once, applying a photolithography technique and an etching technique once, and further performing a selective epitaxial growth by the MOCVD method once, and the conventional vacuum transistor has a complicated photolithography technique. The manufacturing process is extremely simple as compared with the case where an etching technique or a film forming technique is required. Further, unlike the conventional technique, it is possible to form the emitter portion, the base portion, and the collector portion having highly accurate shapes and dimensions without strictly controlling the shape, size, direction, etc. of the mask region. Therefore, it is not necessary to control the photolithography technique or the etching technique itself very accurately.

[Brief description of drawings]

FIG. 1 is a schematic diagram of a vacuum transistor of Example 1.

2A and 2B are a schematic partial plan view and a partial cross-sectional view of the vacuum transistor taken along the line II-II in FIG.

FIG. 3 is a schematic plan view and a partial cross-sectional view of the vacuum transistor taken along the line III-III in FIG.

FIG. 4 is a schematic partial plan view of a compound semiconductor substrate or the like for explaining a method of manufacturing the vacuum transistor of Example 1.

5A and 5B are schematic partial plan views and partial cross-sectional views of the emitter section and the like for explaining the method of manufacturing the vacuum transistor of the first example, following FIG.

6A and 6B are schematic partial plan views and partial cross-sectional views of the emitter section and the like for explaining the method for manufacturing the vacuum transistor of the first example, following FIG.

FIG. 7 is a schematic diagram of a vacuum transistor of Example 2.

FIG. 8 is a schematic perspective view of a part of a compound semiconductor substrate and the like for explaining a method of manufacturing a vacuum transistor of Example 2.

[Explanation of symbols]

 10 Compound Semiconductor Substrate 12, 40, 42, 44, 46 Mask Region 12A Mask Layer 14 Opening 16,50 Emitter 18,52 Base Part 20 Conductive Layer 30 Insulating Substrate 32,54 Collector Part

Claims (6)

[Claims] 1. (a) a compound semiconductor substrate having a (111) B plane; and (b) an equilateral triangular planar shape formed on the (111) B plane of the compound semiconductor substrate. Each side of
[-1, -1, 0] direction of compound semiconductor substrate, [-1,
A mask area orthogonal to the 0, -1] direction and the [0, -1, -1] direction; and (c) the mask area having a shape of an equilateral triangle in which each side is parallel to each side of the mask area. An opening formed in the inside of the compound semiconductor crystal, and (d) is formed on the (111) B plane of the compound semiconductor substrate exposed at the bottom of the opening and has a triangular pyramid shape. Each surface of the compound semiconductor crystal is composed of the {110} plane emitter portion, and (e) the compound semiconductor crystal.
1) a base portion formed on the surface B, having a surface facing and parallel to each surface of the emitter portion having a triangular pyramid shape, and having a conductive layer formed on the top surface; and (f) the emitter portion. A vacuum transistor, characterized in that it comprises a collector section provided above and facing the emitter section. 2. (a) A compound semiconductor substrate having a (111) B plane, and (b) a compound semiconductor substrate formed on the (111) B plane of the compound semiconductor substrate and having a longitudinal direction of [0, -1]. , 1] direction and the width direction is [2,-
A strip-shaped first, second, third, and fourth mask regions, which coincide with the [1, −1] direction, and (c) a compound semiconductor crystal, and the first mask region and the second mask region. The parallelogram is formed on the (111) B plane of the compound semiconductor substrate exposed between and is a parallelogram when cut along a plane parallel to the width direction of the first or second mask region. An emitter portion whose lower and upper bases are orthogonal to the [1,1,1] direction of the compound semiconductor crystal, and whose hypotenuse is orthogonal to the [0,1,1] direction of the compound semiconductor crystal; The semiconductor crystal is formed on the (111) B plane of the compound semiconductor substrate exposed between the second mask region and the third mask region and is parallel to the width direction of the second or third mask region. The shape when cut by a plane is a parallelogram. The upper bottom is composed of a base portion orthogonal to the [1,1,1] direction of the compound semiconductor crystal, and a hypotenuse orthogonal to the [0,1,1] direction of the compound semiconductor crystal, and (e) a compound semiconductor crystal. , Formed on the (111) B plane of the compound semiconductor substrate exposed between the third mask region and the fourth mask region and cut along a plane parallel to the width direction of the third or fourth mask region. The parallelogram has a parallelogram, and the lower and upper bases of the parallelogram are orthogonal to the [1,1,1] direction of the compound semiconductor crystal, and the hypotenuse is [0,1,1] of the compound semiconductor crystal. 1] A vacuum transistor comprising a collector section orthogonal to the direction. 3. The vacuum transistor according to claim 1 or 2, wherein the compound semiconductor substrate, the emitter section and the base section are made of GaAs. 4. (a) A mask layer is formed on the (111) B plane of the compound semiconductor substrate, and then the mask layer is selectively removed, so that each side has [-1,
-1,0] direction, [-1,0, -1] direction and [0,-]
1, -1] direction, and a mask region having a regular triangular plane shape orthogonal to the direction is formed, and at the same time, an opening having a regular triangle shape in which each side is parallel to each side of the mask region is formed in the mask region. (B) a compound semiconductor crystal having a triangular pyramid shape, and each surface of the triangular pyramid has an emitter portion composed of the {110} plane of the compound semiconductor crystal and a bottom portion of the opening. On the (111) B surface of the compound semiconductor substrate exposed to the wafer by epitaxial growth by metalorganic vapor phase epitaxy, and at the same time, a surface made of a compound semiconductor crystal and facing and parallel to each surface of the emitter portion having a triangular pyramid shape. A step of epitaxially growing a base portion having the above-mentioned structure on the (111) B surface of the compound semiconductor substrate outside the mask region and adjacent to the mask region by a metal organic chemical vapor deposition method; Forming a conductive layer on the top surface, (d) above the emitter section, a method for manufacturing a vacuum transistor, characterized in that comprising the step, of providing to the collector portion faces the emitter section. 5. (a) A mask layer is formed on the (111) B plane of the compound semiconductor substrate, and then the mask layer is selectively removed, so that the longitudinal direction of the compound semiconductor substrate is [0, -1]. , 1] direction and the width direction of the strip-shaped first, second, third and fourth mask regions match the [2, -1, -1] direction of the compound semiconductor substrate. And (b) a compound semiconductor crystal, and the shape of the parallelogram when cut along a plane parallel to the width direction of the first or second mask region is a parallelogram. A first mask region and a second mask region are provided with an emitter portion which is orthogonal to the [1,1,1] direction of the compound semiconductor crystal and whose hypotenuse is orthogonal to the [0,1,1] direction of the compound semiconductor crystal. On the (111) B surface of the compound semiconductor substrate exposed between At the same time, the shape is a parallelogram when it is made of a compound semiconductor crystal and cut along a plane parallel to the width direction of the second or third mask region. The base is orthogonal to the [1,1,1] direction of the compound semiconductor crystal and the hypotenuse is orthogonal to the [0,1,1] direction of the compound semiconductor crystal. The (111) B surface of the compound semiconductor substrate exposed between the mask region and the mask region is epitaxially grown by the metal organic chemical vapor deposition method, and at the same time, the width of the third or fourth mask region is formed of the compound semiconductor crystal. The shape when cut along a plane parallel to the direction is a parallelogram, and the bottom and top of the parallelogram are orthogonal to the [1,1,1] direction of the compound semiconductor crystal, and the hypotenuse is the compound. [0,1,1] of semiconductor crystal The base portion perpendicular to the direction, of the compound semiconductor substrate exposed between the third mask region and the fourth mask region (111) B
A method of manufacturing a vacuum transistor, comprising the steps of: epitaxially growing on the surface by a metal organic chemical vapor deposition method. 6. The method of manufacturing a vacuum transistor according to claim 4, wherein the compound semiconductor substrate, the emitter portion and the base portion are made of GaAs.