JPH07201873A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [Summary] [Object] The most main feature of the present invention is to enable effective gettering of impurities in a method of manufacturing a bipolar transistor in which heat treatment is required to be suppressed. [Structure] For example, in the case of a bipolar transistor using trench isolation, carbon is ion-implanted into a region where a trench is to be formed to form a gettering site 17. Then, the gettering site 17 is used to getter oxygen and metal impurities in the surface region of the semiconductor substrate. After the gettering, the gettering site 17 is etched to remove a region containing excess oxygen and metal impurities. After that, by forming the element in the portion where the oxygen concentration is locally reduced, the yield is high and the element can be stably manufactured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device including at least one element on a main surface of a semiconductor substrate, and particularly to a method of manufacturing a bipolar transistor.

[0002]

2. Description of the Related Art As is well known, oxygen having a controlled concentration is introduced into a silicon (Si) substrate on which a semiconductor device is formed. This oxygen forms oxygen precipitation nuclei in the heat treatment process in the manufacturing process, and functions as a gettering site for impurity contamination in the process.

However, when the oxygen concentration is high, crystal defects are likely to occur, and there has been a problem that the mechanical strength of the substrate decreases as the oxygen concentration in the substrate increases.

In particular, when trench isolation is used, the bottom of the trench reaches a Si substrate containing a relatively high concentration of oxygen. Therefore, crystal defects are likely to occur at the edge portion of the trench due to the stress caused by the trench isolation.

Therefore, in a bipolar type device or the like, since there is such a problem of the oxygen concentration in the Si substrate, an epitaxial layer having a low oxygen concentration is formed on the main surface of the substrate, and a semiconductor is formed in the epitaxial layer. It is designed to form an element.

In this case, when the epitaxial layer is formed,
There was a defect that a high concentration of metal impurities was incorporated into the layer as compared with the Si substrate.

Although the oxygen concentration immediately after film formation is low,
Oxygen in the Si substrate diffuses into the epitaxial layer due to the heat treatment during the semiconductor manufacturing process, and the oxygen concentration gradually increases. When the oxygen concentration in the element formation portion becomes high, crystal defects and junction leaks are likely to occur.

Further, when the Si substrate is damaged by ion implantation or the like during the manufacturing process, in the recovery process (at the time of heat treatment), metal impurities are gettered by the damaged region, so that the oxygen concentration is increased. Similarly to the above, crystal defects and junction leaks are likely to occur.

As a countermeasure against these problems, a method of controlling oxygen precipitation by combining a heat treatment at a relatively low temperature and a heat treatment at a relatively high temperature has been taken, but as the device becomes faster, the junction depth becomes shallower. Along with this, the redistribution of impurities due to heat treatment, for example, seeping from the embedded portion, cannot be ignored.

[0010]

As described above, in the prior art, when manufacturing a semiconductor device such as a high speed device which requires suppression of heat treatment, impurities such as a semiconductor substrate cannot be effectively gettered. There was a problem.

Therefore, an object of the present invention is to provide a semiconductor device manufacturing method capable of selectively reducing the impurity concentration in a semiconductor substrate and manufacturing a semiconductor device in a stable and high yield. .

[0012]

In order to achieve the above object, in the method of manufacturing a semiconductor device of the present invention, in the case where at least one element is included on the main surface of the semiconductor substrate, From the main surface of the semiconductor substrate, a step of implanting impurity ions having a gettering effect into the semiconductor substrate, a step of performing a gettering by performing a heat treatment after the implantation of the impurity ions, and after the heat treatment, at least the above And a step of removing a part of the region into which the impurity ions are implanted.

Further, in the method of manufacturing a semiconductor device of the present invention, when at least one element is included on the main surface of the semiconductor substrate, the getter is formed in the semiconductor substrate from the main surface of the semiconductor substrate. A step of implanting impurity ions having a ring effect; a step of performing a gettering by performing a heat treatment after the impurity ion implantation; and a step of removing at least a part of the region where the impurity ion implantation is performed after the heat treatment. And the step of forming an element on the main surface of the semiconductor substrate.

[0014]

According to the present invention, the above-mentioned means can suppress the fluctuation of the generation probability due to the occurrence of crystal defects and the like, so that the semiconductor manufacturing process can be stabilized.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

1 to 20 schematically show the manufacturing process of the bipolar transistor according to the present invention.

That is, when manufacturing this bipolar transistor, for example, a P-type silicon (Si) substrate 1 is used.
The N ⁺ buried layer 11 is formed on the O.sub.0, and then the epitaxial layer 12 is formed (FIG. 1).

The P-type Si substrate 10 has a plane orientation of (100) and a boron concentration of about 2.0 × 10 ¹⁵ c.
m ^-2, the oxygen concentration is a 1.5 × 10 ¹⁸ cm ^-2 order.

In the N ⁺ buried layer 11, antimony is used as the impurity introduced, and the peak concentration is about 2.0 × 1.
The diffusion depth is 0 ¹⁹ cm ^-2 and the diffusion depth is about 2.0 μm.

Phosphorus is used as the impurity introduced into the epitaxial layer 12, and the impurity concentration is about 1.5 × 10 ^16.
cm ^-2 , and the film thickness is about 0.8 μm.

Then, on the main surface of the semiconductor substrate formed as described above, a thermal oxide film 13 and a CVD (C
(hemal vapor Deposition)
After the nitride film 14 and the CVD oxide film 15 are formed, the resist 16 is further formed (FIG. 2).

The thermal oxide film 13 has a thickness of about 50 μm.
It is supposed to be m.

The CVD nitride film 14 is formed of, for example, LP-.
It is formed by the CVD (low pressure CVD) method and has a film thickness of about 100 nm.

The CVD oxide film 15 is formed of, for example, AP-.
It is formed by a CVD (normal pressure CVD) method and has a film thickness of about 800 nm.

The resist 16 has a film thickness of about 1.5.
μm, and an opening is provided corresponding to a region where a trench is to be formed later by using a normal photolithography technique.

Next, the CVD oxide film 15, the CVD nitride film 14, and the thermal oxide film 13 exposed in the opening of the resist 16 are sequentially removed by anisotropic etching, and thereafter, for gettering. Ion implantation of impurity ions is performed (FIG. 3).

As the implanted ion species (impurity ions),
For example, carbon and boron can be considered, but carbon is used in this embodiment.

Here, it is necessary to use sufficiently high energy when implanting the impurity ions for gettering. When the acceleration energy is low, a gettering site is formed around the element forming portion, so that the gettering causes the oxygen / metal concentration of the element forming portion to increase, which causes deterioration of characteristics.

In the case of carbon, when ion implantation is performed by using, for example, an acceleration energy of 300 KeV, the peak depth of impurity ions is about 0.6 μm, the half value width is about 0.08 μm, and the surface area is about 0.4 μm. It is effective to getter metal impurities in the range.

Although depending on the application, when a gettering site shallower than this is formed, the influence of the surface region on the element forming portion cannot be ignored.

In the case of this embodiment, the N ⁺ buried layer 11 is present at a depth of about 0.8 to 3.8 μm from the main surface. Therefore, in order to getter oxygen from the P-type Si substrate 10, it is desirable to form the gettering site so that the peak depth of the impurity ions comes to a depth of about 2.5 to 4.0 μm. . The acceleration energy in this case is about 2.0 to 3.0 MeV.

Therefore, the conditions in this embodiment for ion-implanting carbon are, for example, acceleration energy of 2.3 MeV.
The implantation amount is about 1.0 × 10 ¹⁴ cm ^-2 .

In the present embodiment, at the same time as carbon ion implantation, phosphorus ion implantation for forming the N ⁺ diffusion layer for extracting the collector is performed.

Ion implantation of phosphorus is performed under, for example, two conditions. One of the conditions is that the acceleration energy is about 300 KeV and the implantation amount is about 1.0 × 10 ¹⁴ cm ^{−. 2} and other conditions are acceleration energy of about 50 KeV and injection amount of about 1.0 × 10
It is said to be ¹⁵ cm ^-2 .

Incidentally, when boron is used as an impurity ion for gettering, it is necessary to pay attention to the following points in addition to the above.

For example, if a gettering site is to be formed in a shallow region, it will be difficult to control the impurity concentration in the element formation portion due to self-diffusion of boron.

Further, since the crystal defects formed at the gettering site may reach the element forming portion, delicate adjustment is required for heat treatment for gettering.

Further, the gettering effect is inferior to that of carbon.

When the ion implantation is completed, the resist 16 is then removed and a heat treatment for gettering is performed, whereby the gettering sites 17 and N are obtained.
^{+ The} diffusion layer 18 is formed (FIG. 4).

The heat treatment for gettering is a major factor in determining the size of gettering sites formed by impurity ions for gettering, that is, the size of crystal defects and the gettering effect.

In this heat treatment, nucleation is performed in the range of about 700 to 1000 ° C., so that in the case of normal electric furnace annealing, large variations occur due to differences in the wafer setting position and the like.

If the residence time in this temperature range is too long, a huge crystal defect will be generated, and a large amount of crystal defects will remain in the element forming portion, which will conversely deteriorate the crystallinity.

That is, what is essential in the heat treatment for gettering is the control of the annealing time in the above temperature range and the adjustment of the residence time at high temperature, that is, the adjustment of the nucleation amount and the recovery degree of the formed crystal defects. Is.

Generally, in the process of recovering crystal defects,
A large amount of vacancies are released from the defective portion into the substrate, and impurities are gettered by the defective portion.

In the case of this embodiment, the heat treatment for gettering is performed in two steps.

For example, in the first stage, RTP (Rapi
High-temperature / short-time RTA (Rapid Thermal An) using a d Thermal Process device.
The second stage is FA (Furnace Anneal) using an ordinary electric furnace.

The above-mentioned RTA is suitable for such a treatment, because the heating ramp rate and the treatment time can be precisely controlled in the single-wafer treatment.

FA is also suitable for recovering the crystal defects generated by the above RTA over a long period of time.

In practice, it is necessary to set an appropriate processing temperature and processing time in consideration of the redistribution of impurities in the N ⁺ buried layer 11.

Therefore, in this embodiment, the RTA ramp rate is about 50 ° C./s, the processing temperature is about 1150 ° C.,
The processing time is about 20 seconds.

Further, FA has a treatment temperature of about 1000 ° C.,
The processing time is about 60 minutes.

Then, using the CVD oxide film 15 as a mask, a part of the semiconductor substrate is removed by anisotropic etching or the like to form the trench portion 19 (FIG. 5).

Further, the CVD oxide film 15 is removed and the thermal oxide film 20 is formed around the formed trench portion 19.

The trench portion 19 has an etching depth of about 5.0 μm.

Since most of the gettering site 17 is removed at the same time when the trench portion 19 is formed, it is possible to prevent reverse contamination from the gettering site 17 in a later step.

That is, in a semiconductor device using trench isolation, carbon ion implantation or the like is performed in a region where a trench is to be formed, and oxygen or metal impurities are gettered in the ion implantation region by heat treatment. As a result, the oxygen concentration and the metal impurity concentration in the semiconductor substrate, particularly in the surface region, can be locally controlled, so that the oxygen concentration in the element forming portion can be locally reduced.

Therefore, after the gettering, the gettering site 17 is RIE (reactive ion etching).
Etching is performed by, for example, removing a region containing excess oxygen and metal impurities, and forming an element isolation portion in that region, so that reverse contamination from the gettering site 17 is prevented and the oxygen concentration is locally reduced. It is possible to form elements in the reduced portion.

As described above, impurities can be effectively gettered in a device or the like which requires suppression of heat treatment.

When forming an element, first, a polysilicon film 21 having a thickness of, for example, 2 μm is formed on the main surface of the semiconductor substrate including the trench portion 19 (FIG. 6).

Then, unnecessary portions of the formed polysilicon film 21 are removed by, for example, mechanochemical etching, and the polysilicon 21 is only formed in the trench portion 19.
a is left and the element isolation portion is formed (FIG. 7).

Then, a resist block 22 is formed on the element forming portion on the main surface of the semiconductor substrate (FIG. 8).

In the case of this embodiment, only for the base / emitter portion and the collector portion of the bipolar transistor,
The resist block 22 is formed.

Then, using the resist block 22 as a mask, the main surface of the semiconductor substrate is etched by about 0.8 μm by anisotropic etching or the like to form a recess portion, and thereafter, the recess portion is oxidized by about 100 nm. Thus, the oxide film 23 is formed (FIG. 9).

Then, after the resist block 22 is removed, a polysilicon film 24 having a thickness of, for example, 1.5 μm is deposited on the main surface of the semiconductor substrate (FIG. 10).

Then, unnecessary portions of the formed polysilicon film 24 are removed by, for example, mechanochemical etching, and the polysilicon 24a remains only in the recessed portion (FIG. 11).

Next, the surface of the polysilicon film 24a buried in the recess is thermally oxidized by about 0.3 μm to form a thermal oxide film 25 (FIG. 12).

Then, the CVD nitride film 14 and the thermal oxide film 13 in the element forming portion are sequentially removed to expose the epitaxial layer 12 in the element portion, and then the polysilicon film 26 for the base electrode and the CVD oxide film 27 are removed. , 300 nm each
It is formed in order with a certain thickness (FIG. 13).

The polysilicon film 26 is set to P type by introducing boron during or after film formation.

Next, the formed CVD oxide film 27 is formed.
After the unnecessary portion of the polysilicon film 26 is removed and the base electrode 28 is formed, boron ion implantation for forming the internal base is performed (FIG. 14).

Then, a 200 nm-thick CVD oxide film is formed on the main surface of the semiconductor substrate, and anisotropic etching is performed to form oxide film sidewalls 29 on the sidewalls of base electrode 28. Formed (Fig. 1
5).

Then, an emitter polysilicon film 30 having a thickness of 300 nm, for example, is formed on the main surface of the semiconductor substrate (FIG. 16).

The emitter polysilicon film 30
Is arsenic introduced during or after film formation,
Set to type.

Then, unnecessary portions of the formed emitter polysilicon film 30 are selectively removed (FIG. 17).

Then, after CVD oxide film 31 is formed on the main surface of the semiconductor substrate, heat treatment is performed to activate the base / emitter (FIG. 18).

Next, the formed CVD oxide film 31 is formed.
Opening 32 for forming emitter, base and collector electrodes
a, 32b, and 32c are formed (FIG. 19).

Finally, by depositing an electrode material such as aluminum (Al) on the main surface of the semiconductor substrate and removing unnecessary portions, the emitter electrode 33a, the base electrode 33b and the collector electrode 33c are formed. Each is formed (FIG. 20).

In this way, while preventing the reverse contamination from the gettering site 17 in the subsequent step, the element is formed in the portion where the oxygen concentration is locally reduced, so that the bipolar transistor is stable and has a high yield. A transistor is obtained.

That is, according to the present embodiment, since the oxygen concentration in the epitaxial layer 12 and the substrate interface region can be controlled, oxygen diffusion into the epitaxial layer 12 can be reduced, and crystal defects and junction leaks are generated. Can be suppressed.

Further, since it becomes possible to control the oxygen concentration in the epitaxial layer 12 and the substrate interface region, the oxygen concentration in the periphery of the trench portion 19 can be reduced, and the mechanical strength is increased. It becomes possible to suppress the occurrence of defects at 19.

Further, since it becomes possible to control contamination by the metal impurities in the epitaxial layer 12, it is possible to suppress the occurrence of crystal defects and junction leaks there.

As described above, the fluctuation of the generation probability due to the occurrence of crystal defects can be suppressed.

That is, the oxygen concentration in the semiconductor substrate immediately below the epitaxial layer can be selectively reduced at a relatively early stage of the semiconductor manufacturing process. As a result, the oxygen concentration in the element forming portion on the semiconductor substrate can be locally controlled, and the semiconductor manufacturing process can be stabilized. Therefore, it is possible to suppress the occurrence of crystal defects and junction leaks, and to produce a stable and high-yield bipolar transistor without bleeding from the buried portion.

In the above embodiment, the bipolar transistor has been described as an example, but the present invention is not limited to this and can be applied to the manufacture of various semiconductor devices other than the above structure.

Besides, it goes without saying that various modifications can be made without departing from the spirit of the present invention.

[0085]

As described above in detail, according to the present invention, the concentration of impurities in the semiconductor substrate can be selectively reduced, and the semiconductor device can be manufactured stably and in high yield. A method can be provided.

[Brief description of drawings]

FIG. 1 is a sectional view showing an outline of a manufacturing process of a bipolar transistor according to an embodiment of the present invention.

FIG. 2 is a sectional view showing an outline of a manufacturing process of a bipolar transistor.

FIG. 3 is a sectional view showing an outline of a manufacturing process of a bipolar transistor.

FIG. 4 is a sectional view showing an outline of the manufacturing process of the bipolar transistor.

FIG. 5 is a sectional view showing an outline of a manufacturing process of a bipolar transistor, similarly.

FIG. 6 is a sectional view showing an outline of a manufacturing process of a bipolar transistor.

FIG. 7 is a sectional view showing an outline of a manufacturing process of a bipolar transistor, similarly.

FIG. 8 is a sectional view showing an outline of a manufacturing process of a bipolar transistor, similarly.

FIG. 9 is a sectional view showing an outline of a manufacturing process of a bipolar transistor, similarly.

FIG. 10 is a sectional view showing an outline of a manufacturing process of a bipolar transistor, similarly.

FIG. 11 is a sectional view showing an outline of a manufacturing process of a bipolar transistor, similarly.

FIG. 12 is a sectional view showing an outline of a manufacturing process of a bipolar transistor.

FIG. 13 is a sectional view showing an outline of a manufacturing process of a bipolar transistor, similarly.

FIG. 14 is a sectional view showing an outline of a manufacturing process of a bipolar transistor, similarly.

FIG. 15 is a sectional view showing an outline of a manufacturing process of a bipolar transistor, similarly.

FIG. 16 is a sectional view showing an outline of a manufacturing process of a bipolar transistor, similarly.

FIG. 17 is a sectional view showing an outline of a manufacturing process of a bipolar transistor, similarly.

FIG. 18 is a sectional view showing an outline of a manufacturing process of a bipolar transistor, similarly.

FIG. 19 is a cross-sectional view schematically showing the manufacturing process of the bipolar transistor.

FIG. 20 is a sectional view showing an outline of a manufacturing process of a bipolar transistor, similarly.

[Explanation of symbols]

10 ... P-type Si substrate, 11 ... N ⁺ buried layer, 12 ... Epitaxial layer, 13, 20, 25 ... Thermal oxide film, 14 ...
CVD nitride film, 15, 27, 31 ... CVD oxide film, 16
... Resist, 17 ... Gettering site, 18 ... N ⁺ diffusion layer, 19 ... Trench portion, 21, 24, 26 ... Polysilicon film, 22 ... Resist block, 23 ... Oxide film, 2
8 ... Base electrode, 29 ... Oxide film side wall, 30 ...
Emitter polysilicon film, 33a ... emitter electrode, 3
3b ... Base electrode, 33c ... Collector electrode.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 29/73

Claims (4)

[Claims] 1. A method of manufacturing a semiconductor device including at least one element on a main surface of a semiconductor substrate, wherein impurity ions having a gettering effect are implanted into the semiconductor substrate from the main surface of the semiconductor substrate. And a step of performing gettering by performing heat treatment after implanting the impurity ions, and a step of removing at least a part of the region into which the impurity ions are implanted after the heat treatment. Of manufacturing a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein carbon or boron is used as the impurity ions. 3. The impurity ions are at least 300
The method of manufacturing a semiconductor device according to claim 1, wherein the implantation is performed using an acceleration energy of KeV or higher. 4. A method of manufacturing a semiconductor device including at least one element on a main surface of a semiconductor substrate, wherein impurity ions having a gettering effect are implanted into the semiconductor substrate from the main surface of the semiconductor substrate. A step of performing heat treatment by performing heat treatment after implanting the impurity ions, and a step of removing at least a part of the region into which the impurity ions have been implanted after the heat treatment, and thereafter, the semiconductor substrate And a step of forming an element on the main surface of the semiconductor device.