JPH07201972A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH07201972A JPH07201972A JP33664593A JP33664593A JPH07201972A JP H07201972 A JPH07201972 A JP H07201972A JP 33664593 A JP33664593 A JP 33664593A JP 33664593 A JP33664593 A JP 33664593A JP H07201972 A JPH07201972 A JP H07201972A
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- oxide film
- silicon oxide
- groove
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 126
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 94
- 239000000758 substrate Substances 0.000 claims abstract description 50
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 45
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 45
- 239000010703 silicon Substances 0.000 claims abstract description 45
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 16
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 14
- 238000002955 isolation Methods 0.000 claims abstract description 10
- 239000012212 insulator Substances 0.000 claims abstract description 9
- KGBXLFKZBHKPEV-UHFFFAOYSA-N boric acid Chemical compound OB(O)O KGBXLFKZBHKPEV-UHFFFAOYSA-N 0.000 claims abstract description 4
- 239000004327 boric acid Substances 0.000 claims abstract 2
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 30
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 11
- 239000007864 aqueous solution Substances 0.000 claims description 10
- 239000007791 liquid phase Substances 0.000 claims description 6
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 4
- 239000002253 acid Substances 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 229920006395 saturated elastomer Polymers 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims description 2
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims 1
- 238000000206 photolithography Methods 0.000 claims 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 10
- 238000001312 dry etching Methods 0.000 abstract description 3
- 238000007796 conventional method Methods 0.000 description 6
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 206010036790 Productive cough Diseases 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 210000003802 sputum Anatomy 0.000 description 1
- 208000024794 sputum Diseases 0.000 description 1
Landscapes
- Element Separation (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特に素子分離領域の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing an element isolation region.
【０００２】[0002]
【従来の技術】従来の技術として例えば〔特開平４−２
４５６６２号公報〕に記載された発明があり、以下にこ
の基本的な概念に基づいた従来の技術を、図３（ａ）乃
至（ｃ）を用いてまず説明する。2. Description of the Related Art As a conventional technique, for example, [Japanese Patent Laid-Open No. 4-2
No. 45662], a conventional technique based on this basic concept will be described below with reference to FIGS. 3 (a) to 3 (c).
【０００３】まず、図３（ａ）に示す様に、半導体シリ
コン基板１上に部分的にレジストパターン２を形成し、
このレジストパターン２をマスクとして半導体シリコン
基板１をエッチングし、所望の深さの溝３を形成する。
次に図３（ｂ）に示す様に、珪弗化水素酸に二酸化シリ
コンを溶解した飽和水溶液４に（ＣＨ3 ）4 ＮＯＨを添
加し、この二酸化シリコンを析出させ、その結果析出し
た二酸化シリコンは溝３内に選択的に堆積し、溝３はシ
リコン酸化膜５で埋め込まれる。この場合、シリコン酸
化膜５はシリコン上にのみ堆積し、レジスト上には堆積
しない。次に図３（ｃ）に示す様に、レジストパターン
２を除去し、従来の技術による素子分離領域が形成され
る。First, as shown in FIG. 3A, a resist pattern 2 is partially formed on a semiconductor silicon substrate 1,
The semiconductor silicon substrate 1 is etched using the resist pattern 2 as a mask to form a groove 3 having a desired depth.
Next, as shown in FIG. 3B, (CH 3 ) 4 NOH was added to a saturated aqueous solution 4 in which silicon dioxide was dissolved in hydrofluoric acid, and this silicon dioxide was deposited. As a result, the deposited silicon dioxide was deposited. Are selectively deposited in the trench 3, and the trench 3 is filled with the silicon oxide film 5. In this case, the silicon oxide film 5 is deposited only on silicon, not on the resist. Next, as shown in FIG. 3C, the resist pattern 2 is removed to form an element isolation region according to the conventional technique.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、この方
法では露呈したシリコンを核として等方的にシリコン酸
化膜５が堆積するため、約１ミクロンメートル以下の微
細な幅の溝（左側）とそれ以上の広い幅の溝（右側）が
混在する場合、微細な幅の溝では溝の側面から横方向に
堆積するシリコン酸化膜５の影響がでるため、微細な幅
の溝とそれ以上の広い幅の溝に埋め込まれるシリコン酸
化膜の膜厚が異なり、半導体シリコン基板表面が平坦に
なるように素子分離領域が形成されない。例えば、幅
０．５μｍ、深さ１μｍの微細な溝と、深さ１μｍで幅
が０．５μｍより広い溝を同時に埋め込む場合、微細の
幅の溝は０．２５μｍの厚さのシリコン酸化膜の堆積で
溝の側面から横方向に堆積するシリコン酸化膜が接触し
溝は完全に埋め込まれるが、広い幅の溝では横方向から
の堆積がないため０．２５μｍの厚さのシリコン酸化膜
が堆積しただけにすぎず、この時点で幅０．５μｍの幅
の溝とそれ以上の広い幅の溝で０．７５μｍの段差が生
じる結果となる。However, in this method, since the silicon oxide film 5 isotropically deposits using exposed silicon as a nucleus, a groove having a fine width of about 1 micrometer or less (left side) and more than that. When a groove with a wide width (on the right side) is mixed, a groove with a fine width is affected by the silicon oxide film 5 deposited laterally from the side surface of the groove, so that a groove with a fine width and a wider width than that are formed. The thickness of the silicon oxide film embedded in the groove is different, and the element isolation region is not formed so that the surface of the semiconductor silicon substrate becomes flat. For example, when a fine groove having a width of 0.5 μm and a depth of 1 μm and a groove having a depth of 1 μm and a width of more than 0.5 μm are simultaneously embedded, the fine width groove is formed of a silicon oxide film having a thickness of 0.25 μm. In the deposition, the silicon oxide film laterally deposited from the side surface of the groove comes into contact and completely fills the groove. However, in a wide groove, there is no lateral deposition, so a silicon oxide film with a thickness of 0.25 μm is deposited. Not only that, but at this point, a step of 0.75 μm occurs between the groove having a width of 0.5 μm and the groove having a wider width than that.
【０００５】また、微細な幅の溝では形成するシリコン
酸化膜のステップカバリッジが良好でないため、溝の側
面から横方向に堆積するシリコン酸化膜が溝の上部で接
触して蓋が出来てしまい、その結果図３（ｂ），（ｃ）
に示す様に溝の内部に空間１８ができ、完全に溝の埋め
込む事が不可能となる。Further, since the step coverage of the silicon oxide film formed in the groove having a fine width is not good, the silicon oxide film deposited laterally from the side surface of the groove comes into contact with the upper part of the groove to form a lid. As a result, FIG. 3 (b), (c)
As shown in FIG. 5, a space 18 is formed inside the groove, which makes it impossible to completely embed the groove.
【０００６】従って、このような従来の方法では、目的
として掲げる「微細な幅の溝とそれ以上の広い幅の溝に
シリコン酸化膜を均一に埋め込むことができるため、平
坦化のために講ずる工程が必要でなくなり、工程が簡単
になり、均一な素子分離が形成できる」という主要な課
題は、未解決になっている。Therefore, in such a conventional method, the silicon oxide film can be uniformly buried in the groove having a fine width and the groove having a wider width, which is the purpose, and therefore, the steps taken for planarization. Is not required, the process is simplified, and uniform element isolation can be formed. "
【０００７】本発明の目的は、このような未解決問題を
解決し、良好な素子分離領域が形成されるようにする半
導体装置の製造方法を提供することにある。It is an object of the present invention to provide a method for manufacturing a semiconductor device which solves such an unsolved problem and allows a good element isolation region to be formed.
【０００８】[0008]
【課題を解決するための手段】本発明の第１の構成は、
半導体シリコン基板の主面上に、第１のシリコン酸化
膜、第１のシリコン窒化膜を順に形成する工程と、素子
分離領域となる部分の前記第１のシリコン窒化膜と前記
第１のシリコン酸化膜と前記半導体シリコン基板を選択
的にエッチングを行い溝を形成する工程と、前記エッチ
ングで用いたフォトレジストを除去した後、シリコンが
露呈した部分を前記第１のシリコン窒化膜をマスクとし
て熱酸化し第２のシリコン酸化膜を形成する工程と、前
記溝の側壁に前記第２のシリコン窒化膜サイドウォール
を形成する工程と、前記第１のシリコン窒化膜と前記第
２のシリコン窒化膜サイドウォールとをマスクとして前
記溝の底面を選択的に熱酸化し前記溝の底面に第３のシ
リコン酸化膜を形成する工程と、前記第１のシリコン窒
化膜と前記第２のシリコン窒化膜サイドウォールとを除
去する工程と、前記第１のシリコン酸化膜と前記第２の
シリコン酸化膜を除去する工程と、前記第３のシリコン
酸化膜を核としてこの上に第４のシリコン酸化膜を液相
成長させ前記溝を前記第４のシリコン酸化膜により埋め
込む工程とを含むことを特徴とする。The first structure of the present invention is as follows.
A step of sequentially forming a first silicon oxide film and a first silicon nitride film on the main surface of the semiconductor silicon substrate, and a portion of the first silicon nitride film and the first silicon oxide film that will be element isolation regions. A step of selectively etching the film and the semiconductor silicon substrate to form a groove; and, after removing the photoresist used in the etching, the exposed portion of silicon is thermally oxidized using the first silicon nitride film as a mask. A step of forming a second silicon oxide film, a step of forming the second silicon nitride film side wall on the side wall of the groove, a step of forming the first silicon nitride film and the second silicon nitride film side wall. With the mask as a mask to selectively thermally oxidize the bottom surface of the groove to form a third silicon oxide film on the bottom surface of the groove, the first silicon nitride film and the second silicon film. A step of removing the con-nitride film side wall, a step of removing the first silicon oxide film and the second silicon oxide film, and a fourth silicon layer formed on the third silicon oxide film as a nucleus. Liquid phase growing an oxide film and filling the groove with the fourth silicon oxide film.
【０００９】本発明の第２の構成は、第１のシリコン酸
化膜上にシリコン単結晶あるいはシリコン多結晶が形成
されたシリコン−オン−インシュレイター半導体基板の
一主面上に、写真食刻法を用いてフォトレジストパター
ンを形成する工程と、前記パターンをマスクとしてシリ
コン基板をエッチングし、前記第１のシリコン酸化膜を
露呈させ、表面から前記第１のシリコン酸化膜まで貫通
する溝を構成する工程と、前記溝を前記露呈した第１の
シリコン酸化膜を核として第２のシリコン酸化膜を液相
成長させ前記溝を埋め込む工程と、前記フォトレジスト
パターンを除去する工程とを含むことを特徴とする。A second structure of the present invention is a photo-etching method on one main surface of a silicon-on-insulator semiconductor substrate in which a silicon single crystal or a silicon polycrystal is formed on a first silicon oxide film. A step of forming a photoresist pattern using, and exposing the first silicon oxide film by etching the silicon substrate using the pattern as a mask to form a groove penetrating from the surface to the first silicon oxide film. A step of liquid phase growing a second silicon oxide film by using the exposed first silicon oxide film as a nucleus to fill the groove, and a step of removing the photoresist pattern. And
【００１０】[0010]
【実施例】図１（ａ）乃至（ｄ）は、本発明の第１の実
施例の半導体装置の製造方法の主要な工程を順に示した
半導体基板の断面図である。この実施例は、まず図１
（ａ）に示す様に、半導体シリコン基板１上の全面に膜
厚１乃至１００ｎｍの第１のシリコン酸化膜６を熱酸化
法で形成し、次にこの表面に膜厚５０乃至５００ｎｍの
第１のシリコン窒化膜７を化学気相成長法により形成し
た後、フォトレジストパターン８を形成し、フォトレジ
ストパターン８をマスクとして第１のシリコン窒化膜
７、第１のシリコン酸化膜６、半導体シリコン基板１を
順次エッチングし、半導体シリコン基板１上に半導体シ
リコン基板１の表面からの深さ約１乃至２００ｎｍの溝
３を形成する。1A to 1D are sectional views of a semiconductor substrate showing, in order, the main steps of a method of manufacturing a semiconductor device according to a first embodiment of the present invention. This embodiment is first shown in FIG.
As shown in (a), a first silicon oxide film 6 having a film thickness of 1 to 100 nm is formed on the entire surface of the semiconductor silicon substrate 1 by a thermal oxidation method, and then a first silicon oxide film 6 having a film thickness of 50 to 500 nm is formed on this surface. Of the first silicon nitride film 7, the first silicon oxide film 6, and the semiconductor silicon substrate using the photoresist pattern 8 as a mask after the silicon nitride film 7 is formed by the chemical vapor deposition method. 1 is sequentially etched to form a groove 3 having a depth of about 1 to 200 nm from the surface of the semiconductor silicon substrate 1 on the semiconductor silicon substrate 1.
【００１１】次に、このフォトレジストパターン８を除
去した後に、図１（ｂ）に示す様に、第１のシリコン窒
化膜７をマスクとして、溝３の内壁に露呈した半導体シ
リコン基板１に熱酸化を行い膜厚約１乃至５０ｎｍの第
２のシリコン酸化膜９を形成した後、シリコン半導体基
板１上の全表面に膜厚約１０〜２００ｎｍの第２のシリ
コン窒化膜を化学気相成長法により形成し、次に異方性
のドライエッチングを用いてこの第２のシリコン窒化膜
をエッチバックし、溝３の側壁にシリコン窒化膜サイド
ウォール１０を形成することにより、シリコン半導体基
板１の表面と溝３の側壁とがすべてシリコン窒化膜で覆
われ、溝３の底面のみ第２のシリコン酸化膜９が露呈し
た構造になる。Next, after removing the photoresist pattern 8, as shown in FIG. 1B, the semiconductor silicon substrate 1 exposed on the inner wall of the groove 3 is heated by using the first silicon nitride film 7 as a mask. After the second silicon oxide film 9 having a film thickness of about 1 to 50 nm is formed by oxidation, a second silicon nitride film having a film thickness of about 10 to 200 nm is formed on the entire surface of the silicon semiconductor substrate 1 by chemical vapor deposition. Surface of the silicon semiconductor substrate 1 is formed by etching back the second silicon nitride film by anisotropic dry etching to form the silicon nitride film sidewall 10 on the sidewall of the groove 3. The sidewall of the trench 3 is entirely covered with the silicon nitride film, and the second silicon oxide film 9 is exposed only on the bottom surface of the trench 3.
【００１２】尚、この時、溝３の底部の半導体シリコン
基板１が露呈するまでエッチングしても良い。At this time, etching may be performed until the semiconductor silicon substrate 1 at the bottom of the groove 3 is exposed.
【００１３】次に図１（ｃ）に示す様に、第１のシリコ
ン窒化膜７とシリコン窒化膜サイドウォール１０とをマ
スクとして溝３の底面のみに露呈した半導体シリコン基
板１を、温度約１０００℃のＨ2 −Ｏ2 雰囲気中で熱酸
化を行い、選択的に膜厚約５乃至１００ｎｍ程度の第３
のシリコン酸化膜１１を形成し、第１のシリコン窒化膜
７とシリコン窒化膜サイドウォール１０とを燐酸でエッ
チングし除去した後、第１のシリコン酸化膜６と第２の
シリコン酸化膜９をバッファード弗酸でエッチング除去
し、溝３の底面のみに第３のシリコン酸化膜１１を残留
させ、半導体シリコン基板１と溝３の側壁のシリコンを
露呈させる。この工程で第１のシリコン酸化膜６と第２
のシリコン酸化膜９をバッファード弗酸でエッチング除
去し、溝３の底面のみに第３のシリコン酸化膜１１を残
留させるためには第３のシリコン酸化膜１１の膜厚は、
少なくとも第１のシリコン酸化膜６と第２のシリコン酸
化膜９の膜厚の２倍以上に設定することが望ましい。Next, as shown in FIG. 1C, the semiconductor silicon substrate 1 exposed only on the bottom surface of the groove 3 with the first silicon nitride film 7 and the silicon nitride film sidewalls 10 as a mask is heated to a temperature of about 1000. Thermal oxidation is performed in an H 2 —O 2 atmosphere at a temperature of 3 ° C. to selectively form a third film having a film thickness of about 5 to 100 nm.
A silicon oxide film 11 is formed, the first silicon nitride film 7 and the silicon nitride film sidewall 10 are removed by etching with phosphoric acid, and then the first silicon oxide film 6 and the second silicon oxide film 9 are buffered. It is removed by etching with hydrofluoric acid to leave the third silicon oxide film 11 only on the bottom surface of the groove 3 to expose the semiconductor silicon substrate 1 and the silicon on the sidewalls of the groove 3. In this process, the first silicon oxide film 6 and the second silicon oxide film 6
In order to remove the third silicon oxide film 9 by etching with buffered hydrofluoric acid and leave the third silicon oxide film 11 only on the bottom surface of the groove 3, the thickness of the third silicon oxide film 11 is
It is desirable to set at least twice the film thickness of the first silicon oxide film 6 and the second silicon oxide film 9.
【００１４】次に図１（ｄ）に示すように、温度を例え
ば３５℃に設定した珪弗化水素酸（Ｈ2 ＳｉＦ4 ）に二
酸化シリコン（ＳｉＯ2 ）を飽和溶解させた水溶液１２
に、半導体シリコン基板１を浸漬し、ほう酸（Ｈ3 ＢＯ
3 ）水溶液を滴下する事により二酸化シリコンを溝３底
部の第３のシリコン酸化膜１１上のみに選択的に堆積さ
せ、少なくとも半導体シリコン基板１の表面よりも上ま
でシリコン酸化膜を成長させ、第４のシリコン酸化膜１
３を形成する。この場合、第４のシリコン酸化膜１３は
半導体シリコン基板１の表面から約１０乃至５０ｎｍ上
方に突出している。Next, as shown in FIG. 1D, an aqueous solution 12 in which silicon dioxide (SiO 2 ) is saturatedly dissolved in hydrosilicofluoric acid (H 2 SiF 4 ) whose temperature is set to, for example, 35 ° C.
Then, the semiconductor silicon substrate 1 is dipped in boric acid (H 3 BO
3 ) Silicon dioxide is selectively deposited only on the third silicon oxide film 11 at the bottom of the groove 3 by dropping an aqueous solution, and the silicon oxide film is grown at least above the surface of the semiconductor silicon substrate 1, Silicon oxide film 1 of 4
3 is formed. In this case, the fourth silicon oxide film 13 projects above the surface of the semiconductor silicon substrate 1 by about 10 to 50 nm.
【００１５】また、この場合、二酸化シリコンの堆積は
シリコン酸化膜１１上のみで起こり、シリコン表面では
起こらないため、第４のシリコン酸化膜１３は溝３の底
面の第３のシリコン酸化膜１１をいわゆる核にして順次
上方に向かって成長し、従って溝３の幅に依存すること
がなく溝３を均一、平坦に埋め込むことができる。以上
により、本発明の第１の実施例による半導体装置の製造
方法が示された。Further, in this case, since the deposition of silicon dioxide occurs only on the silicon oxide film 11 and does not occur on the silicon surface, the fourth silicon oxide film 13 forms the third silicon oxide film 11 on the bottom surface of the groove 3. The so-called nuclei sequentially grow upward, so that the groove 3 can be uniformly and flatly embedded without depending on the width of the groove 3. The method for manufacturing the semiconductor device according to the first embodiment of the present invention has been described above.
【００１６】次に本発明の第２の実施例を図２（ａ）乃
至（ｄ）の断面図を参照して説明する。この第２の実施
例は、一例としてＳＩＭＯＸ（Ｓｅｐａｒａｔｉｏｎ
ｂｙＩｍｐｌａｎｔｅｄ Ｏｘｙｇｅｎ）技術を用いて
形成したシリコン−オン−インシュレイター半導体基板
を用いる。Next, a second embodiment of the present invention will be described with reference to the sectional views of FIGS. 2 (a) to 2 (d). In the second embodiment, SIMOX (Separation) is used as an example.
A silicon-on-insulator semiconductor substrate formed by using a byImplemented Oxygen) technique is used.
【００１７】まずこの実施例では、ＳＩＭＯＸ技術で形
成したシリコン基板は、図２（ａ）に示す様に、通常用
いられるシリコン基板中に埋め込み、シリコン酸化膜層
１５が形成された構造をとる。この実施例は一例として
シリコン基板表面から深さ約０．３μｍの所に、厚さ約
０．５μｍの埋め込みシリコン酸化膜層１５が形成され
た構造を持つシリコン−オン−インシュレイター半導体
基板１４を用いることとする。First, in this embodiment, the silicon substrate formed by the SIMOX technique has a structure in which a silicon oxide film layer 15 is formed by embedding it in a silicon substrate which is normally used, as shown in FIG. In this embodiment, as an example, a silicon-on-insulator semiconductor substrate 14 having a structure in which a buried silicon oxide film layer 15 having a thickness of about 0.5 μm is formed at a depth of about 0.3 μm from the surface of the silicon substrate is shown. I will use it.
【００１８】次に図２（ｂ）に示す様に、シリコン−オ
ン−インシュレイター半導体基板１４上にフォトレジス
トパターン８を形成し、このパターン８をマスクにして
シリコン−オン−インシュレイター半導体基板１４をド
ライエッチングを用いてエッチングし、埋め込みシリコ
ン酸化膜層１５を部分的に露呈させ、シリコン−オン−
インシュレイター半導体基板１４に、この半導体基板１
４表面から埋め込み、シリコン酸化膜層１５まで貫通す
る溝１６を形成する。Next, as shown in FIG. 2B, a photoresist pattern 8 is formed on the silicon-on-insulator semiconductor substrate 14, and the pattern 8 is used as a mask to form the silicon-on-insulator semiconductor substrate 14. Is etched using dry etching to partially expose the buried silicon oxide film layer 15, and silicon-on-
This semiconductor substrate 1 is added to the insulator semiconductor substrate 14.
A groove 16 is buried from the surface to penetrate the silicon oxide film layer 15.
【００１９】次に図２（ｃ）に示すように、温度を例え
ば３５℃に設定した珪弗化水素酸（Ｈ2 ＳｉＦ4 ）に二
酸化シリコン（ＳｉＯ2 ）を飽和溶解させた水溶液１２
にこの半導体基板１４を浸漬し、ほう酸（Ｈ3 ＢＯ3 ）
水溶液を滴下する事により二酸化シリコンを溝１６底部
の埋め込みシリコン酸化膜層１５上のみに選択的に堆積
させ、少なくともこの半導体基板１４の表面よりも上ま
でシリコン酸化膜を成長させ、シリコン酸化膜１７で溝
１６を埋め込む。この場合、シリコン酸化膜１７は半導
体基板１４の表面から約１０〜５０ｎｍ上方に突出して
いる。また、この場合、二酸化シリコンの堆積は、シリ
コン酸化膜上のみで起こり、シリコン表面とフォトレジ
ストパターン８との表面では起こらないため、シリコン
酸化膜１７は溝１６の底面の埋め込みシリコン酸化膜層
１５をいわゆる核にして順次上方に向かって成長し、従
って溝１６の幅、または深さに依存することがなく溝１
６を均一、平坦に埋め込むことができる。Next, as shown in FIG. 2C, an aqueous solution 12 in which silicon dioxide (SiO 2 ) is saturatedly dissolved in hydrosilicofluoric acid (H 2 SiF 4 ) whose temperature is set to, for example, 35 ° C.
The semiconductor substrate 14 is dipped in boric acid (H 3 BO 3 )
By dropping an aqueous solution, silicon dioxide is selectively deposited only on the buried silicon oxide film layer 15 at the bottom of the groove 16, and the silicon oxide film is grown at least above the surface of the semiconductor substrate 14, so that the silicon oxide film 17 is formed. The groove 16 is filled with. In this case, the silicon oxide film 17 projects above the surface of the semiconductor substrate 14 by about 10 to 50 nm. Further, in this case, since the deposition of silicon dioxide occurs only on the silicon oxide film and does not occur on the surface of the silicon and the surface of the photoresist pattern 8, the silicon oxide film 17 has the buried silicon oxide film layer 15 on the bottom surface of the groove 16. Are so-called nuclei and grow upward in sequence, so that the groove 1 does not depend on the width or depth of the groove 16.
6 can be embedded uniformly and flatly.
【００２０】次に図２（ｄ）に示す様に、フォトレジス
トパターン８を除去する。以上により、本発明の第２の
実施例による半導体装置の製造方法が示された。Next, as shown in FIG. 2D, the photoresist pattern 8 is removed. The method for manufacturing the semiconductor device according to the second embodiment of the present invention has been described above.
【００２１】[0021]
【発明の効果】以上のように、本発明によれば、溝を埋
め込むシリコン酸化膜は、シリコン表面あるいはレジス
トパターン表面では成長せず、溝の底部に形成されたシ
リコン酸化膜を核にしてシリコン酸化膜上のみに選択的
に順次上方に向かって成長するため、従来の技術の様
に、微細な幅の溝と広い幅の溝との違いにより溝に埋め
込まれるシリコン酸化膜の膜厚が異なり、シリコン基板
表面が平坦にならなかったり、溝の側面から横方向に成
長するシリコン酸化膜が溝の上部で接触して蓋が出来て
しまい、その結果溝の内部に空間ができ、完全に溝を埋
め込む事が不可能となるという現象が起きることはな
く、簡略な工程で、微細な幅の溝と広い幅の溝のどちら
も、また溝の深さによらず、溝の内部に空間が出来るこ
となく良好に、均一，平坦にシリコン酸化膜で埋め込む
ことが出来る。As described above, according to the present invention, the silicon oxide film filling the groove does not grow on the silicon surface or the resist pattern surface, and the silicon oxide film formed at the bottom of the groove serves as a nucleus. Since the film grows selectively and sequentially upward only on the oxide film, the thickness of the silicon oxide film embedded in the groove is different due to the difference between the groove having a fine width and the groove having a wide width as in the conventional technique. , The surface of the silicon substrate is not flat, or the silicon oxide film that grows laterally from the side surface of the groove comes into contact with the top of the groove to form a lid, and as a result, a space is created inside the groove and the groove is completely formed. There is no phenomenon that it becomes impossible to embed, and in a simple process, there is a space inside the groove for both the fine width groove and the wide width groove and regardless of the groove depth. Good, uniform without being able to It can be embedded in the silicon oxide film in sputum.
【００２２】すなわち、本発明は、工程が簡略であり、
微細な素子分離領域の形成に用いて好適であるため、超
高密度半導体集積回路の製造に適し、もってその製造の
低コスト化、高歩留まりに寄与するという効果を持つ。That is, according to the present invention, the steps are simple,
Since it is suitable for use in forming a minute element isolation region, it is suitable for manufacturing an ultra-high-density semiconductor integrated circuit, and thus has the effect of contributing to the manufacturing cost reduction and high yield.
【図１】（ａ）乃至（ｄ）は本発明の第１の実施例の半
導体装置の製造方法の主要な工程を順に示した基板の断
面図である。1A to 1D are cross-sectional views of a substrate showing, in sequence, main steps of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.
【図２】（ａ）乃至（ｄ）は本発明の第２の実施例の半
導体装置の製造方法の主要な工程を順に示した基板の断
面図である。FIG. 2A to FIG. 2D are cross-sectional views of a substrate showing, in sequence, the main steps of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.
【図３】（ａ）乃至（ｃ）は従来の技術による半導体装
置の製造方法の主要な工程を順に示した基板の断面図で
ある。3A to 3C are cross-sectional views of a substrate showing, in sequence, the main steps of a method for manufacturing a semiconductor device according to a conventional technique.
１ 半導体シリコン基板 ２ レジストパターン ３，１６ 溝 ４ 珪弗化水素酸に二酸化シリコンを溶解した飽和水
溶液 ５，１７ シリコン酸化膜 ６ 第１のシリコン酸化膜 ７ 第１のシリコン窒化膜 ８ フォトレジストパターン ９ 第２のシリコン酸化膜 １０ シリコン窒化膜サイドウォール １１ 第３のシリコン酸化膜 １２ 珪弗化水素酸（Ｈ2 ＳｉＦ4 ）に二酸化シリコ
ン（ＳｉＯ2 ）を飽和溶解させた水溶液 １３ 第４のシリコン酸化膜 １４ シリコン−オン−インシュレイター半導体基板 １５ 埋め込みシリコン酸化膜 １８ 空間1 Semiconductor Silicon Substrate 2 Resist Pattern 3,16 Groove 4 Saturated Aqueous Solution in which Silicon Dioxide is Dissolved in Hydrofluoric Acid 5,17 Silicon Oxide Film 6 First Silicon Oxide Film 7 First Silicon Nitride Film 8 Photoresist Pattern 9 Second silicon oxide film 10 Silicon nitride film sidewall 11 Third silicon oxide film 12 Aqueous solution in which silicon dioxide (SiO 2 ) is saturated dissolved in hydrosilicofluoric acid (H 2 SiF 4 ) 13 Fourth silicon oxide Film 14 Silicon-on-insulator semiconductor substrate 15 Embedded silicon oxide film 18 Space
Claims (5)
シリコン酸化膜、第１のシリコン窒化膜を順に形成する
工程と、素子分離領域となる部分の前記第１のシリコン
窒化膜と前記第１のシリコン酸化膜と前記半導体シリコ
ン基板を選択的にエッチングを行い溝を形成する工程
と、前記エッチングで用いたフォトレジストを除去した
後、シリコンが露呈した部分を前記第１のシリコン窒化
膜をマスクとして熱酸化し第２のシリコン酸化膜を形成
する工程と、前記溝の側壁に前記第２のシリコン窒化膜
サイドウォールを形成する工程と、前記第１のシリコン
窒化膜と前記第２のシリコン窒化膜サイドウォールとを
マスクとして前記溝の底面を選択的に熱酸化し前記溝の
底面に第３のシリコン酸化膜を形成する工程と、前記第
１のシリコン窒化膜と前記第２のシリコン窒化膜サイド
ウォールとを除去する工程と、前記第１のシリコン酸化
膜と前記第２のシリコン酸化膜を除去する工程と、前記
第３のシリコン酸化膜を核としてこの上に第４のシリコ
ン酸化膜を液相成長させ前記溝を前記第４のシリコン酸
化膜により埋め込む工程とを含むことを特徴とする半導
体装置の製造方法。1. A step of sequentially forming a first silicon oxide film and a first silicon nitride film on a main surface of a semiconductor silicon substrate, and a portion of the first silicon nitride film to be an element isolation region and the first silicon nitride film. A step of selectively etching the first silicon oxide film and the semiconductor silicon substrate to form a groove, and a portion where silicon is exposed after the photoresist used in the etching is removed is the first silicon nitride film. Using as a mask to form a second silicon oxide film by thermal oxidation, a step of forming the second silicon nitride film side wall on the side wall of the groove, the first silicon nitride film and the second silicon nitride film. A step of selectively thermally oxidizing the bottom surface of the groove using the silicon nitride film sidewall as a mask to form a third silicon oxide film on the bottom surface of the groove; and the first silicon nitride film. A step of removing the second silicon nitride film side wall; a step of removing the first silicon oxide film and the second silicon oxide film; and a step of removing the third silicon oxide film as a nucleus on the step. A step of liquid phase growing a fourth silicon oxide film and filling the groove with the fourth silicon oxide film.
晶あるいはシリコン多結晶が形成されたシリコン−オン
−インシュレイター半導体基板の一主面上に、写真食刻
法を用いてフォトレジストパターンを形成する工程と、
前記パターンをマスクとしてシリコン基板をエッチング
し、前記第１のシリコン酸化膜を露呈させ、表面から前
記第１のシリコン酸化膜まで貫通する溝を構成する工程
と、前記溝を前記露呈した第１のシリコン酸化膜を核と
して第２のシリコン酸化膜を液相成長させ前記溝を埋め
込む工程と、前記フォトレジストパターンを除去する工
程とを含むことを特徴とする半導体装置の製造方法。2. A photoresist pattern is formed on a main surface of a silicon-on-insulator semiconductor substrate having a silicon single crystal or a silicon polycrystal formed on a first silicon oxide film by photolithography. Forming process,
Etching the silicon substrate using the pattern as a mask to expose the first silicon oxide film to form a groove penetrating from the surface to the first silicon oxide film; and the first exposing the groove. A method of manufacturing a semiconductor device, comprising: a step of liquid phase growing a second silicon oxide film using a silicon oxide film as a nucleus to fill the groove; and a step of removing the photoresist pattern.
シリコン酸化膜または前記第２のシリコン酸化膜の膜厚
の２倍以上の膜厚に形成する請求項１記載の半導体装置
の製造方法。3. The manufacturing of a semiconductor device according to claim 1, wherein the third silicon oxide film is formed to have a film thickness twice or more the film thickness of the first silicon oxide film or the second silicon oxide film. Method.
は、珪弗化水素酸（Ｈ2 ＳｉＦ4 ）に、二酸化シリコン
（ＳｉＯ2 ）を飽和溶解させた水溶液に、ほう酸（Ｈ3
ＢＯ3 ）水溶液を添加し、二酸化シリコンの過飽和状態
を作り、前記水溶液にシリコン基板を浸漬する事により
二酸化シリコンがシリコン基板上に形成されたシリコン
酸化膜上のみに選択的に堆積する現象を利用する請求項
１または請求項２に記載の半導体装置の製造方法。4. In the selective liquid phase growth of the silicon oxide film, boric acid (H 3 ) is added to an aqueous solution in which silicon dioxide (SiO 2 ) is saturated and dissolved in hydrosilicofluoric acid (H 2 SiF 4 ).
BO 3 ) aqueous solution is added to create a supersaturated state of silicon dioxide, and the silicon substrate is immersed in the aqueous solution to selectively deposit silicon dioxide only on the silicon oxide film formed on the silicon substrate. The method for manufacturing a semiconductor device according to claim 1, wherein
成長では、前記溝を一様に埋め込み、更に基板の表面よ
りも上まで成長させる請求項１または請求項２に記載の
半導体装置の製造方法。5. The semiconductor device according to claim 1, wherein in the selective liquid phase growth of the silicon oxide film serving as the nucleus, the groove is uniformly filled and further grown above the surface of the substrate. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33664593A JPH07201972A (en) | 1993-12-28 | 1993-12-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33664593A JPH07201972A (en) | 1993-12-28 | 1993-12-28 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07201972A true JPH07201972A (en) | 1995-08-04 |
Family
ID=18301312
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33664593A Pending JPH07201972A (en) | 1993-12-28 | 1993-12-28 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07201972A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6191008B1 (en) | 1998-06-30 | 2001-02-20 | Hyundai Electronics Industries Co., Ltd. | Method of forming SOI substrate which includes forming trenches during etching of top semiconductor layer |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0661343A (en) * | 1992-08-04 | 1994-03-04 | Nec Corp | Manufacture of semiconductor device |
| JPH06204332A (en) * | 1993-01-05 | 1994-07-22 | Nec Corp | Manufacture of semiconductor device |
-
1993
- 1993-12-28 JP JP33664593A patent/JPH07201972A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0661343A (en) * | 1992-08-04 | 1994-03-04 | Nec Corp | Manufacture of semiconductor device |
| JPH06204332A (en) * | 1993-01-05 | 1994-07-22 | Nec Corp | Manufacture of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6191008B1 (en) | 1998-06-30 | 2001-02-20 | Hyundai Electronics Industries Co., Ltd. | Method of forming SOI substrate which includes forming trenches during etching of top semiconductor layer |
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