JPH07202052A - Method for manufacturing semiconductor integrated circuit device - Google Patents

Abstract

(57) [Abstract] [Purpose] An LSI including a plurality of types of transistors having different characteristics is formed on a semiconductor substrate. [Structure] For example, a bipolar transistor and a CMOSF
Like ET, two or more types of transistors are formed on separate silicon thin film layers 3a and 3b, and the plurality of silicon thin film layers 3a and 3b are bonded on the silicon wafer 2 to connect the transistors. At this time, the sidewall spacer 11a is formed on the side wall of the one silicon thin film layer 3b.
Is provided and the other silicon thin film layer 3a is arranged so as to be in contact with the end portion of the sidewall spacer 11a, whereby the silicon thin film layers 3a and 3b are aligned with high precision.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technology of a semiconductor integrated circuit device, and particularly effective when applied to a semiconductor integrated circuit device having an integrated circuit composed of a plurality of types of transistors on one semiconductor substrate. It is about technology.

[0002]

2. Description of the Related Art A bipolar-CMOS LSI having both high speed of a bipolar transistor, high integration of a complementary MISFET (CMOSFET) and low power consumption.
In recent years, application to high-speed memory LSIs, high-speed logic LSIs, etc. has been increasing.

However, in a bipolar-CMOS LSI in which a bipolar transistor and a MISFET having different structures and characteristics are formed on the same semiconductor substrate, a bipolar transistor or an MISFET is used.
Since the number of manufacturing steps is larger than that of SI, there is a problem that manufacturing takes a long time and the manufacturing yield decreases.

For example, in the case of a bipolar LSI using a U-groove for element isolation, the required number of steps is about 300, whereas a bipolar-CM using a U-groove for element isolation is also used.
In the case of OSLSI, it is about 500 processes, which is about 50% more than that of bipolar LSI. Compared only by the number of dry etching processes in which pattern defects that greatly affect the yield are particularly problematic, there are 8 processes for bipolar and 10 processes for CMOS, whereas there are about 14 processes for bipolar-CMOS. It is estimated that the number of pattern defects also increases in proportion to.

When forming a bipolar transistor and a MISFET on the same semiconductor substrate, MISFE
An unnecessary epitaxial layer is required for T, and the influence of heat treatment during the manufacturing of the bipolar transistor is affected by MISFE.
Constraints on the process also increase, such as having to change the order of the processes so as not to reach T.
Therefore, for example, in the manufacturing process of a bipolar transistor, SICOS (SIdewall base COn) has many steps.
tact Structure) process and SEPT (Selective Etchi
It is almost impossible to form a bipolar-CMOS LSI on the same semiconductor substrate by combining the ng of Polysilicon Technology) process and the CMOS process.

[0006]

As described above, when two or more types of transistors having different structures and characteristics are to be formed on the same semiconductor substrate, the number of steps is increased and the product development efficiency is significantly impaired. At the same time, as the number of processes increases, stress and crystal defects accumulate on the substrate, which reduces the manufacturing yield. Further, there are limits to improving the performance and the degree of integration of the device because process restrictions are also increased.

It is an object of the present invention to form an integrated circuit composed of two or more kinds of semiconductor elements on the same semiconductor substrate without prolonging the manufacturing period or decreasing the manufacturing yield. To provide.

Another object of the present invention is to provide a technique capable of forming an integrated circuit composed of two or more kinds of semiconductor elements on the same semiconductor substrate without significantly increasing the number of manufacturing steps. .

Another object of the present invention is to provide a technique capable of forming an integrated circuit composed of two or more kinds of semiconductor elements on the same semiconductor substrate without deteriorating the performance and the degree of integration of the semiconductor elements. To do.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0011]

The typical ones of the inventions disclosed in the present application will be outlined below.

(1). A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein a first semiconductor element is formed on each main surface of a plurality of first semiconductor thin film layers formed on a first semiconductor substrate, After forming the second semiconductor element on the main surface of each of the plurality of second semiconductor thin film layers formed on the second semiconductor substrate, a part of the plurality of first semiconductor thin film layers is removed from the first semiconductor substrate. A part of the plurality of second semiconductor thin film layers is removed from the second semiconductor substrate, an insulating film is deposited on the first semiconductor substrate, and then the insulating film is etched to form the insulating film on the first semiconductor substrate. Sidewall spacers are formed on the sidewalls of the remaining first semiconductor thin film layer, and the second semiconductor thin film layer removed from the second semiconductor substrate is removed from the first semiconductor thin film layer on the first semiconductor substrate. Place it in the area and After positioning so as to contact the sidewall spacer, the first semiconductor element formed on the main surface of the first semiconductor thin film layer and the second semiconductor element formed on the main surface of the second semiconductor thin film layer are connected by wiring. To connect.

(2) In the method of manufacturing a semiconductor integrated circuit device according to claim 3, a sidewall spacer is formed on a sidewall of the first semiconductor thin film layer remaining on the first semiconductor substrate by etching the insulating film. Instead of the above-mentioned means for forming, the insulating film is etched to leave the insulating film on the upper surface and the side wall of the first semiconductor thin film layer, and the second semiconductor thin film layer removed from the second semiconductor substrate is replaced with the second semiconductor thin film layer. The first semiconductor thin film layer is placed on a region of the first semiconductor substrate from which the first semiconductor thin film layer has been removed and positioned so as to come into contact with the insulating film remaining on the sidewall of the first semiconductor thin film layer. The first semiconductor element formed on the main surface and the second semiconductor element formed on the main surface of the second semiconductor thin film layer are connected by wiring.

(3) In the method of manufacturing a semiconductor integrated circuit device according to claim 4, the first semiconductor is replaced with the above-mentioned means for forming a sidewall spacer or an insulating film on the side wall of the first semiconductor thin film layer. The photoresist used for removing a part of the thin film layer from the first semiconductor substrate is left on the sidewall of the first semiconductor thin film layer, and the second semiconductor thin film layer removed from the second semiconductor substrate is the second semiconductor thin film layer. The first semiconductor thin film layer is placed on a region of the semiconductor substrate where the first semiconductor thin film layer is removed and positioned so as to come into contact with the photoresist remaining on the sidewall of the first semiconductor thin film layer. The first semiconductor element formed on the surface and the second semiconductor element formed on the main surface of the second semiconductor thin film layer are connected by wiring.

[0015]

According to the above-mentioned means (1), the distance from the side wall of the first semiconductor thin film layer to the end of the side wall spacer can be controlled with high accuracy. The two semiconductor thin film layers can be positioned on the first semiconductor substrate with high accuracy.

According to the above-mentioned means (2), the distance from the side wall of the first semiconductor thin film layer to the end of the insulating film can be controlled with high accuracy, and therefore the second semiconductor substrate removed from the second semiconductor substrate can be controlled. The semiconductor thin film layer can be positioned on the first semiconductor substrate with high accuracy.

According to the above-mentioned means (3), the distance from the side wall of the first semiconductor thin film layer to the end of the photoresist can be controlled with high accuracy, so that the second semiconductor layer removed from the second semiconductor substrate can be controlled. The semiconductor thin film layer can be positioned on the first semiconductor substrate with high accuracy.

According to the above means (1) to (3),
By forming different types of semiconductor elements on different semiconductor thin film layers, the number of manufacturing steps can be reduced compared to the case where these semiconductor elements are formed on the same semiconductor substrate, which improves the manufacturing yield. To do.

According to the above means (1) to (3),
By forming different kinds of semiconductor elements in different semiconductor thin film layers, there is no process limitation as in the case of forming these semiconductor elements on the same semiconductor substrate.
The performance and the degree of integration of each semiconductor element are not deteriorated.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numeral, and the repeated description thereof will be omitted.

(Embodiment 1) This embodiment is a bipolar-C
This is applied to a MOS LSI, and its manufacturing method will be described below in the order of steps with reference to FIGS.

First, as shown in FIG.
Insulator) Substrate 1 is prepared. The SOI substrate 1 includes a silicon wafer 2 and an adhesive layer 4 on the silicon wafer 2.
And a large number of silicon thin film layers that are bonded to each other through. In FIG. 1, these many silicon thin film layers are represented by two silicon thin film layers 3b and 3b. These silicon thin film layers 3b and 3b are separated from each other by a groove 6 in which a silicon oxide film 5 is embedded.

To manufacture the SOI substrate 1, for example, a silicon wafer 2 having a thickness of about 500 μm can be formed on the main surface with a thickness of 0.1 μm.
A silicon oxide film having a thickness of about 5 to 1.0 μm is formed by a thermal oxidation method and is used as the adhesive layer 4. Next, a second silicon wafer (not shown) is superposed on the silicon wafer 2 and heat-bonded to each other, and then the surface of the second silicon wafer is polished to reduce the thickness to about 1 to 2 μm.

Then, the surface of the second silicon wafer is etched to form grooves 6 having a width of about 1.0 μm in a grid pattern, and the silicon thin film layers 3 separated from each other by the grooves 6 are formed.
b, 3b are obtained. After that, C is applied to the entire surface of the SOI substrate 1.
A silicon oxide film 5 is deposited by the VD method to fill the groove 6, and finally the silicon oxide film 5 on the silicon thin film layers 3b and 3b is removed by etch back.

Next, as shown in FIG. 2, semiconductor elements, such as CMOSFETs, are formed on the main surfaces of the silicon thin film layers 3b and 3b by a conventional method. Although not shown, the same SOI as the SOI substrate 1 shown in FIG.
Another substrate is prepared separately, and a bipolar transistor is formed on each main surface of the silicon thin film layer according to a conventional method. As described above, in this embodiment, the CMOSFET is formed on the silicon thin film layer 3b of the first SOI substrate 1,
A bipolar transistor is formed on the silicon thin film layer of the second SOI substrate prepared separately.

Next, as shown in FIG. 3, the silicon oxide film 5 buried in the trench 6 of the SOI substrate 1 is removed by etching, and then the entire surface of the SOI substrate 1 including the inside of the trench 6 is covered with C.
A silicon nitride film 7 is deposited by the VD method. The silicon nitride film 7 is formed on the silicon thin film layer 3b by SOI in a process described later.
It is for protecting the surface of the silicon thin film layer 3b from the etching liquid used when lifting off from the substrate 1,
The film thickness is about 50 nm or more.

Next, as shown in FIG. 4, the surface of the silicon thin film layers 3b and 3b is covered with a photoresist 8 and the silicon nitride film 7 at the bottom of the groove 6 and the adhesive layer 4 thereunder are covered with this as a mask. Anisotropic etching is performed to form openings 9 reaching the surface of the silicon wafer 2. This etching is performed by plasma etching using a fluorocarbon-based etching gas such as CHF ₃ or CF ₄ . The opening 9 is not located near the silicon thin film layer 3b left on the SOI substrate 1 (the silicon thin film layer 3b on the right side in the figure) but on the silicon thin film layer 3b to be lifted off.
It is formed in the vicinity of (the silicon thin film layer 3b on the left side of the figure).

Next, after the photoresist 8 is removed, as shown in FIG. 5, the silicon thin film layer 3 on the left side of FIG.
The adhesive layer 4 on the bottom of b is isotropically wet-etched by using, for example, an etching solution containing hydrofluoric acid (for example, hydrofluoric acid-ammonium fluoride buffer solution). At this time, the silicon thin film layer 3b (on the right side in the figure) left on the SOI substrate 1
And the adhesive layer 4 on the bottom of the photoresist 10 on its surface and sidewalls so as not to be etched.
Cover with. By doing this, as shown in FIG.
Only the silicon thin film layer 3b on the left side of the figure is lifted off from the surface of the silicon wafer 2.

Next, after the photoresist 10 is removed, as shown in FIG. 7, an insulating film having a reflow property, such as BPSG (Boro Phospho Sili), is formed on the entire surface of the SOI substrate 1.
A cateGlass) film 11 is deposited by the CVD method. As the insulating film having a reflow property, other than the BPSG film 11, for example, a PSG (Phospho Silicate Glass) film, a BSG (Boro)
Known materials such as Silicate Glass) film can be used.

Next, as shown in FIG. 8, the BPSG film 11 is processed by anisotropic etching such as RIE (Reactive Ion Etching) to form a sidewall of the silicon thin film layer 3b remaining on the SOI substrate 1. The sidewall spacer 11a is formed. At this time, by controlling the film thickness, film quality, etching conditions, etc. of the BPSG film 11, the distance (d) from the side wall of the silicon thin film layer 3b to the end of the side wall spacer 11a is controlled within an error of ± about 0.05 μm or less. It is possible to control in the range of. After that, a silicon oxide film is deposited by a CVD method in an empty area of the main surface of the SOI substrate 1 from which the silicon thin film layer 3b has been removed in the above process, and this is used as the adhesive layer 4 which also serves to adjust the altitude difference.

Next, as shown in FIG. 9, a silicon thin film layer 3a is placed in an empty area of the main surface of the SOI substrate 1, and its side wall is in contact with the side wall spacer 11a on the side wall of the silicon thin film layer 3b. To position. This silicon thin film layer 3a is removed from the above-mentioned second SOI substrate (not shown), and a bipolar transistor is formed on its main surface.

As described above, in this embodiment, the SOI substrate 1
The silicon thin film layer 3a is placed in an empty area of the main surface of the substrate and positioned so that its side wall is in contact with the side wall spacer 11a. As described above, the distance (d) from the side wall of the silicon thin film layer 3b to the end of the side wall spacer 11a can be controlled with high accuracy. Therefore, according to this embodiment,
Silicon thin film layer 3 removed from another SOI substrate
It is possible to position a on the SOI substrate 1 with high accuracy.

Next, as shown in FIG. 10, the SOI substrate 1
Is heat-treated to reflow the sidewall spacers 11a, and the bottom surface of the silicon thin film layer 3a is fixed to the silicon wafer 2 via the adhesive layer 4. When the side wall spacer 11a is reflowed, its shape and dimensions are changed, so the position of the silicon thin film layer 3a is slightly displaced from the position before reflow. However, by controlling the temperature during reflow, this deviation amount is extremely small. It is possible to control within the error range.

Next, as shown in FIG. 11, the SOI substrate 1
A silicon oxide film 12 is deposited on the upper surface by a CVD method, and this is etched back to flatten the surface of the groove 6, and then the bipolar transistor formed on the main surface of the silicon thin film layer 3a and the main surface of the silicon thin film layer 3b. Formed on the
And the wiring 13 are connected to each other, and finally the surface of the SOI substrate 1 is covered with a passivation film 14 to complete a bipolar-CMOS LSI.

Example 2 In the above example, the sidewall spacer 11 formed on the sidewall of the silicon thin film layer 3b was used.
Although the silicon thin film layer 3a removed from another SOI substrate is positioned on the SOI substrate 1 using a, the silicon thin film layer 3a is positioned by a method different from this in this embodiment.

The manufacturing method of this embodiment is the same as that shown in FIGS.
The steps shown up to, that is, the steps from removing a part of the silicon thin film layer 3b from the main surface of the SOI substrate 1 to depositing the BPSG film 11 on the entire surface of the SOI substrate 1 are
This is the same as the first embodiment.

Next, in the present embodiment, as shown in FIG. 12, S etching is performed by using the photoresist 15 as a mask.
The BPSG film 11 on the empty area of the main surface of the OI substrate 1 is removed, and the BPS film is formed on the upper and side walls of the silicon thin film layer 3b.
The G film 11 is left. At this time, the distance (d) from the sidewall of the silicon thin film layer 3b to the end of the BPSG film 11 is controlled within a margin of error by controlling the film thickness, film quality, etching conditions, etc. of the BPSG film 11. Is possible. Then, CVD is performed on an empty area of the main surface of the SOI substrate 1.
A silicon oxide film is deposited by the method, and this is used as the adhesive layer 4 which also serves to adjust the height difference.

Next, as shown in FIG. 13, the silicon thin film layer 3a removed from the second SOI substrate is placed in the empty area of the main surface of the SOI substrate 1 and the side wall thereof is BPSG.
Position so that it contacts the end of the membrane 11. As described above, since the distance (d) from the side wall of the silicon thin film layer 3b to the end of the BPSG film 11 can be controlled with high accuracy, the silicon thin film layer 3a is formed on the SOI substrate 1 as in the first embodiment.
It can be positioned with high accuracy.

Next, as shown in FIG. 14, the SOI substrate 1
Is heat-treated to reflow the BPSG film 11, and
The bottom surface of the silicon thin film layer 3a is fixed to the silicon wafer 2 via the adhesive layer 4. When the BPSG film 11 is reflowed, its shape and dimensions are changed.
Position slightly shifts from the position before reflow, but BP
By controlling the film thickness, film quality, and reflow temperature of the SG film 11, it is possible to control this amount of deviation within a very small error range.

Since the subsequent steps are almost the same as those in the first embodiment, the description thereof will be omitted.

(Embodiment 3) In this embodiment, the above-mentioned embodiment 1 is used.
The silicon thin film layer 3a is positioned by a method different from that of the second embodiment.

The manufacturing method of this embodiment is the same as that shown in FIGS.
The steps shown up to this point, that is, the steps until a part of the silicon thin film layer 3b is removed from the main surface of the SOI substrate 1 are the same as those in the first and second embodiments. At this time,
As shown in FIG. 5, the surface and the sidewall of the silicon thin film layer 3b left on the SOI substrate 1 are covered with the photoresist 10.

Next, in this embodiment, as shown in FIG. 16, the silicon thin film layer 3a removed from the second SOI substrate is placed in the empty area of the main surface of the SOI substrate 1, and the side wall of the silicon thin film layer 3a is formed by photolithography. It is positioned so as to come into contact with the end of the resist 10. Photoresist 1 from the side wall of the silicon thin film layer 3b
Since the distance to the end of 0 can be controlled with high accuracy, the silicon thin film layer 3a can be positioned on the SOI substrate 1 with high accuracy, as in the first and second embodiments.

Next, after the photoresist 10 is removed, a silicon oxide film 16 is deposited on the entire surface of the SOI substrate 1 as shown in FIG. 17, and the surface thereof is etched back to be planarized. Since the subsequent steps are almost the same as those in the first and second embodiments, the description thereof will be omitted.

(Embodiment 4) FIG. 18 is a plan view of a semiconductor substrate 1 on which a bipolar-CMOS LSI of this embodiment is formed, and FIG. 19 is a sectional view taken along the line AA 'of FIG.

On the silicon wafer 2 of the semiconductor substrate 1 having the SOI structure, the silicon thin film layers 3a, 3b, 3 are formed.
c are bonded together via an adhesive layer 4, and a groove 6 is provided between the respective silicon thin film layers 3a, 3b and 3c.

On the main surface of the silicon thin film layer 3a, for example, 2
A bipolar transistor manufactured in a layered polysilicon bipolar process is formed. A CMOSFET is formed on the main surface of the silicon thin film layer 3b. Further, on the main surface of the silicon thin film layer 3c, for example, SEPT
A high-speed bipolar transistor manufactured by the process (or SICOS process) is formed. These bipolar transistors and CMOSFETs have wiring 13
Are connected to each other by the two, so that two kinds of bipolar transistors and CMOSFETs are formed on the silicon wafer 2.
A bipolar-CMOS LSI composed of the above is formed.

The silicon thin film layer 3a is formed by forming a bipolar transistor on a second SOI substrate (not shown) and then bonding the same on the silicon wafer 2 by the method described in the first, second or third embodiment. . Further, the silicon thin film layer 3c is formed by forming a bipolar transistor on a third SOI substrate (not shown) and then bonding the same on the silicon wafer 2 by the method described in the first, second or third embodiment.

According to this embodiment, the bipolar transistor manufactured by the two-layer poly-silicon bipolar process and the SE
An SOI substrate 1 is a bipolar-CMOS LSI including a high-speed bipolar transistor manufactured by a PT process (or a SICOS process) and a CMOSFET.
It is possible to form on top.

FIG. 20 is a plan view showing a layout when the silicon thin film layer 3a removed from another SOI substrate is bonded onto the SOI substrate 1. One location to match the accuracy of the bonding location (Fig. (A))
It is possible to change from 4 to 4 places (Fig. (D)).

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

In the first to fourth embodiments, the bipolar-CMO is used.
Although the method of manufacturing the SLSI has been described, the present invention is not limited to this, and can be widely applied to the case of forming an LSI including two or more types of semiconductor elements on the same semiconductor substrate.

Although the SOI substrate is used in the first to fourth embodiments, the present invention is not limited to this. For example, an ordinary silicon wafer whose back surface is polished to have a thickness of about several μm is used as a silicon thin film layer. You may use.

The present invention can also be used to repair defects in LSI. That is, after forming a transistor in each of a large number of silicon thin film layers formed on one semiconductor substrate, the silicon thin film layer including a defective transistor is removed, and a non-defective product formed on another semiconductor substrate in the empty region. A silicon thin film layer may be attached.

[0055]

The effects obtained by the typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, when the second semiconductor thin film layer removed from the second semiconductor substrate is bonded onto the first semiconductor substrate, the actual position and the designed position of the second semiconductor thin film layer. Since it is possible to significantly reduce the error between the second semiconductor thin film layer and the second semiconductor element (eg, bipolar transistor) formed on the main surface of the second semiconductor thin film layer, and the first semiconductor element formed on the main surface of the first semiconductor thin film layer. (For example, CMOSFE
It is possible to reliably connect T) with T.

(2) According to the present invention, the bipolar-CMOS LSI can be formed on the semiconductor substrate without increasing the manufacturing steps of the bipolar transistor or the CMOSFET and reducing the manufacturing yield.

(3) According to the present invention, the bipolar-CMOS LS is formed on the semiconductor substrate without deteriorating the performance and the degree of integration of the bipolar transistor and the CMOSFET.
I can be formed.

[Brief description of drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 3 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 4 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 5 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 6 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 7 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 8 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 9 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 10 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 11 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 12 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 13 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 14 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 15 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 16 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 17 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 18 is a plan view of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device which is another embodiment of the present invention.

19 is a cross-sectional view taken along the line AA ′ in FIG.

FIG. 20 is a plan view showing a layout when a semiconductor thin film layer removed from a semiconductor substrate is attached to another semiconductor substrate.

[Explanation of symbols]

 1 SOI Substrate 2 Silicon Wafer 3a Silicon Thin Film Layer 3b Silicon Thin Film Layer 3c Silicon Thin Film Layer 4 Adhesive Layer 5 Silicon Oxide Film 6 Groove 7 Silicon Nitride Film 8 Photoresist 9 Open Hole 10 Photoresist 11 BPSG Film 11a Sidewall Spacer 12 Silicon Oxide Film 13 Wiring 14 Passivation film 15 Photoresist 16 Silicon oxide film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location // H01L 21/762

Claims (6)

[Claims] 1. A method of manufacturing a semiconductor integrated circuit device, comprising the following steps (a) to (e): (a) A first semiconductor element is formed on each main surface of a plurality of first semiconductor thin film layers formed on a first semiconductor substrate, and each of a plurality of second semiconductor thin film layers formed on a second semiconductor substrate is formed. Forming a second semiconductor element on the main surface, (b) removing a part of the plurality of first semiconductor thin film layers from the first semiconductor substrate,
Removing a part of the plurality of second semiconductor thin film layers from the second semiconductor substrate, (c) depositing an insulating film on the first semiconductor substrate, and then etching the insulating film to form the first semiconductor Forming a sidewall spacer on the sidewall of the first semiconductor thin film layer remaining on the substrate; (d) the second
The sidewall spacer formed on the sidewall of the first semiconductor thin film layer by mounting the second semiconductor thin film layer removed from the semiconductor substrate on a region of the first semiconductor substrate from which the first semiconductor thin film layer is removed. And (e) after bonding the second semiconductor thin film layer on the first semiconductor substrate, the first semiconductor element and the second semiconductor element formed on the main surface of the first semiconductor thin film layer. A step of connecting the second semiconductor element formed on the main surface of the semiconductor thin film layer by wiring. 2. In the step (c), a reflowable insulating film is deposited on the first semiconductor substrate, and in a subsequent step, the first semiconductor substrate is heat-treated to reflow the sidewall spacers. A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein 3. A method of manufacturing a semiconductor integrated circuit device, which comprises the following steps (a) to (e): (a) A first semiconductor element is formed on each main surface of a plurality of first semiconductor thin film layers formed on a first semiconductor substrate, and each of a plurality of second semiconductor thin film layers formed on a second semiconductor substrate is formed. Forming a second semiconductor element on the main surface, (b) removing a part of the plurality of first semiconductor thin film layers from the first semiconductor substrate,
Removing a part of the plurality of second semiconductor thin film layers from the second semiconductor substrate, (c) depositing an insulating film on the first semiconductor substrate, and then etching the insulating film to form the first semiconductor Leaving the insulating film on the upper surface and the side wall of the first semiconductor thin film layer remaining on the substrate, (d) by using the second semiconductor thin film layer removed from the second semiconductor substrate as the first
Placing on a region of the semiconductor substrate from which the first semiconductor thin film layer has been removed, and positioning so as to contact the insulating film remaining on the sidewall of the first semiconductor thin film layer; (e) the second semiconductor thin film layer Is bonded to the first semiconductor substrate, and then the first semiconductor element formed on the main surface of the first semiconductor thin film layer and the second semiconductor element formed on the main surface of the second semiconductor thin film layer are wired. The process of connecting by. 4. A method of manufacturing a semiconductor integrated circuit device, which comprises the following steps (a) to (d). (a) A first semiconductor element is formed on each main surface of a plurality of first semiconductor thin film layers formed on a first semiconductor substrate, and each of a plurality of second semiconductor thin film layers formed on a second semiconductor substrate is formed. Forming a second semiconductor element on the main surface, (b) removing a part of the plurality of first semiconductor thin film layers from the first semiconductor substrate by etching using a photoresist as a mask, Removing a part of the thin film layer from the second semiconductor substrate, (c) removing the second semiconductor thin film layer removed from the second semiconductor substrate to the first semiconductor thin film layer on the first semiconductor substrate The second semiconductor thin film layer on the first semiconductor thin film layer, and then positioning the second semiconductor thin film layer on the sidewall of the first semiconductor thin film layer so as to contact with the photoresist. Bonded on a semiconductor substrate A step of connecting the first semiconductor element formed on the main surface of the first semiconductor thin film layer and the second semiconductor element formed on the main surface of the second semiconductor thin film layer by wiring. 5. A bipolar transistor is formed on the main surface of the first semiconductor thin film layer on the first semiconductor substrate, and a complementary MISFET is formed on the main surface of the second semiconductor thin film layer on the second semiconductor substrate. Then, the bipolar transistor and the complementary MISFET are connected by the wiring, and the bipolar-CMOS L is formed on the first semiconductor substrate.
5. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein SI is formed. 6. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the semiconductor substrate is an SOI substrate.