JPH07202191A - Vertical power MOS semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Abstract] [Purpose] The injection amount of the N-type body and the injection amount of the low concentration N-type region of the Zener diode can be set to optimum values. [Structure] After depositing a polysilicon film 14, N-type impurities are implanted into the entire surface of the polysilicon film. Next, in order to form an N type body, an opening is formed in the N type body region, and in order to make the polysilicon film 14 a gate electrode and a Zener diode, the polysilicon film 14 and the gate oxide film 12 are formed by lithography and etching. Are patterned, and N-type impurities are implanted into the patterned polysilicon film 14 and the epitaxial layer 4 using the patterned polysilicon film 14 as a mask. Then, thermal diffusion is performed to form the N-type body 16. At this time, the N-type impurity implanted in the step (C) is further implanted into the polysilicon film 14 by the N-type impurity implanted in the step (D).
N of higher concentration than the N-type body 16 due to addition of N-type impurities
It becomes the type polysilicon layer 40N.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a vertical power MOSFET.
The present invention relates to a power MOS semiconductor device having a zener diode for protecting the gate electrode between the gate electrode and the source thereof and a method for manufacturing the same.

[0002]

2. Description of the Related Art A vertical power MOSFET having a gate electrode protecting Zener diode between a gate electrode and a source.
A method of manufacturing the above will be described with reference to FIGS. 1 and 2. (A) P-type epitaxial layer 4 is grown on the surface of P-type silicon substrate 2, silicon oxide film 6 is formed on epitaxial layer 4, and lithography and etching are performed so that an opening is formed in a region where an N-type well is formed. The oxide film 6 is patterned by. N-type impurities are introduced into the epitaxial layer 4 using the oxide film 6 as a mask to form an N-type well 8.

(B) A field oxide film 10 is formed on the N-type well 8 by the selective oxidation method.
On the surface of the epitaxial layer exposed from the gate oxide film 12
To form. (C) A polysilicon film 14 is deposited on the gate oxide film 12 and the field oxide film 10.

(D) An opening is formed in the N-type body region to form an N-type body, and the polysilicon film 14 and the gate oxide are formed by lithography and etching in order to use the polysilicon film 14 as a gate electrode and a Zener diode. The membrane 12 is patterned. N-type impurities are implanted into the patterned polysilicon film 14 and the epitaxial layer 4 using the polysilicon film 14 as a mask. Then, thermal diffusion is performed to form the N-type body 16.

(E) Next, a resist pattern 18 having an opening in the N-type body region is formed by lithography,
Using this as a mask, N-type impurities are implanted at high concentration into the N-type body. Then, the resist 18 is removed, and thermal diffusion is performed to form an N-type region 20 for contact.

(F) Next, the contact N-type region 20 and the region 14N which becomes the low concentration N-type region by the Zener diode.
A resist pattern 22 for covering is formed by lithography, and P-type impurities are implanted using the resist pattern 22 as a mask. After that, heat treatment is performed to activate the implanted ions.
Thereby, the source region 24 and the high concentration P-type region 14P of the Zener diode are formed. As a result, the polysilicon gate electrode 26 also becomes P-type, and a high-concentration P-type region 14P and a low-concentration N-type region 14N are formed in the Zener diode region.

(G) After removing the resist 22, a PSG film or a BPSG film is deposited as an interlayer insulating film 28 to form contact holes or through holes. An aluminum or aluminum alloy film is deposited thereon and patterned by lithography and etching to form a metal wiring 30 for a source electrode and a metal wiring 32 for an input.

Formation of the N-type body 16 and polysilicon film 14 for forming a low concentration N-type region of the Zener diode.
The N-type impurity implantation into is simultaneously formed in the step (D) of FIG. Therefore, the completed power MOSF
In ET, the impurity concentration of the N-type body 16 and the impurity concentration of the low-concentration N-type polysilicon region 14N of the Zener diode are the same.

[0009]

The impurity concentration of the N-type body 16 has a great influence on the basic characteristics such as the threshold voltage Vth, the breakdown voltage, and the on-resistance Ron of the MOSFET, so that the concentration needs to be optimized. On the other hand, the Zener diode is composed of a high-concentration P-type polysilicon region and a low-concentration N-type polysilicon region, but it has been found that the characteristics after the breakdown greatly affect the impurity concentration of the low-concentration N-type polysilicon region. ing. Therefore, it is also necessary to optimize the ion implantation amount for the low concentration N-type polysilicon region 14N.

That is, it is preferable that the implantation amount of the N-type body and the implantation amount of the low-concentration N-type region of the Zener diode are set independently and optimally, but if they are manufactured by the conventional method, these are set independently. It is not possible, and the injection amount will always be the same. Therefore, optimizing one sacrifices the other.

An object of the present invention is to provide a manufacturing method capable of setting an implantation amount of an N-type body and an implantation amount of a low concentration N-type region of a Zener diode to optimum values. Another object of the present invention is to provide a vertical power MOS semiconductor device having the optimum characteristics thus obtained.

[0012]

[Means for Solving the Problems] Vertical power MO of the present invention
In the S semiconductor device, an N-type body is formed on the surface of the P-type epitaxial layer on the surface of the semiconductor substrate, and a P-type source region is formed on the surface within the N-type body at a position apart from the boundary between the N-type body and the epitaxial layer. And a gate electrode is formed via a gate oxide film on the N-type body region sandwiched between the source region and the exposed portion of the epitaxial layer on the surface of the epitaxial layer.
A FET is formed, and a Zener diode formed of a high-concentration P-type polysilicon region and a low-concentration N-type polysilicon region which are in contact with each other is connected between the gate electrode and the source region, and The impurity concentrations of the N-type body and the low-concentration N-type polysilicon region of the Zener diode are set to different concentrations according to their respective characteristics. In a preferred mode of this vertical power MOS semiconductor device, this power MOS semiconductor device is formed together with other MOSFETs on the same semiconductor substrate.

The manufacturing method of the present invention uses P on the surface of a semiconductor substrate.
An N-type body is formed on the surface of the N-type epitaxial layer, and a P-type source region is formed on the surface inside the N-type body at a position away from the boundary of the N-type body. A vertical power MOSFET is formed by forming a gate electrode via a gate oxide film on an N-type body region sandwiched between the exposed portion of the layer and a high-concentration P-type polysilicon region in contact with each other. And a low-concentration N-type polysilicon region are formed in the zener diode connected between the gate electrode and the source region. When manufacturing a vertical power MOS semiconductor device, the zener diode serves as the zener diode and the gate electrode. A step of implanting an N-type impurity over the entire surface of the polysilicon film after depositing the polysilicon film and before patterning the polysilicon film; After patterning, an N type impurity is implanted to make the polysilicon film have an impurity concentration for the low concentration N type polysilicon region of the Zener diode, and an N type body is formed in the epitaxial layer. , Are provided.

[0014]

The amount of implantation of the low concentration N-type region of the Zener diode is the sum of the two ion implantation steps of steps (B) and (C) of FIG. On the other hand, the implantation amount of the N-type body is the implantation amount in the single ion implantation step of step (D). If the implantation amount of the N-type body is set to an optimum value, the implantation amount of the ion implantation process in the step (D) is set to the implantation amount of the N-type body.
Generally, the implantation amount of the low concentration N-type region of the Zener diode is larger than that, and the implantation amount further required for optimization is performed in the ion implantation step of step (C).

[0015]

EXAMPLE FIG. 3 shows a vertical power MOS semiconductor device of an example. An N-type body 16 is formed on the surface of the P-type epitaxial layer 4 on the surface of the silicon substrate 2,
The N-type body 16 and the epitaxial layer 4 on the surface inside
A P-type source region 24 is formed at a position away from the boundary between and. The source region 2 is formed on the surface of the epitaxial layer 4.
4 and the exposed portion of the epitaxial layer 4, a polysilicon gate electrode 26 is formed on the N type body 16 sandwiched between the gate oxide film 12 and the vertical power MOSFE.
T is configured.

On the field oxide film 10, a Zener diode having a high concentration P type polysilicon region 40P and a low concentration N type polysilicon region 40N which are in contact with each other is formed. The Zener diode is connected between the gate electrode 26 and the source region 16 via aluminum metal wirings 30 and 32.

The impurity concentrations of the N-type body 16 and the low-concentration N-type polysilicon region 40N of the Zener diode are set to different concentrations according to their respective characteristics. Reference numeral 28 denotes an interlayer insulating film such as a PSG film or a BPSG film. The metal wiring 30 of the source electrode is connected to the source region 24 and the contact region 20 through a contact hole of the interlayer insulating film 28, and the metal wiring 30 is an interlayer insulating film. It is connected to one electrode of the Zener diode through 28 through holes. The other electrode of the Zener diode is connected to the input metal wiring 32 through the through hole of the interlayer insulating film 28. The metal wiring 32 is connected to the gate input terminal and the gate electrode 26 of the MOSFET.
Is also connected to.

Next, a method of manufacturing the embodiment of FIG. 3 will be described with reference to FIGS. (A) A P-type epitaxial layer 4 is grown on the surface of the P-type silicon substrate 2. A silicon oxide film 6 having a thickness of 2000 to 6000Å is formed on the epitaxial layer 4, and the oxide film 6 is patterned by lithography and etching so as to have an opening in a region where an N-type well is formed. N-type impurities are introduced into the epitaxial layer 4 using the oxide film 6 as a mask to form an N-type well 8.

(B) A field oxide film 10 is formed on the N-type well 8 to a thickness of 5000 to 10000Å by the selective oxidation method. Thereafter, a gate oxide film 12 having a thickness of 300 to 1000Å is formed on the surface of the epitaxial layer exposed from the field oxide film 10.

(C) After depositing a polysilicon film 14 on the gate oxide film 12 and the field oxide film 10 to a thickness of about 5000 Å, N-type impurities are implanted into the entire surface of the polysilicon film. The N-type impurity may be phosphorus or arsenic. For example, phosphorus is used with an energy of 30 to 50 KeV and a dose of 1 × 10.
¹³ to 1 × 10 ¹⁴ / cm ^{2 is} injected. As a result, the polysilicon film 14 becomes a low concentration N-type polysilicon film 40N.

(D) Next, in order to form an N type body, an opening is formed in the N type body region, and in order to make the polysilicon film 14 a gate electrode and a Zener diode, a polysilicon film is formed by lithography and etching. 14 and gate oxide 12 are patterned.

A patterned polysilicon film 14,
N-type impurities are implanted into the epitaxial layer 4 using the mask as a mask. The implantation at this time may be either phosphorus or arsenic, but, for example, phosphorus ions may be used at an energy of 30 to 50 KeV.
Then, a dose amount of 1 × 10 ¹³ to 1 × 10 ¹⁴ / cm ^{2 is} injected. Then, thermal diffusion at 1100 to 1200 ° C. is performed to form the N-type body 16. At this time, in the polysilicon film 14, the N-type impurity injected in the step (C) is further added to the N-type impurity injected in the step (C), and the N-type polysilicon having a higher concentration than the N-type body 16 is added. It becomes the layer 40N.

(E) Next, a resist pattern 18 having an opening in the N-type body region is formed by lithography,
Using this as a mask, N-type impurities are implanted at high concentration into the N-type body. The N-type impurity at this time may be phosphorus or arsenic.
Implantation is performed at × 10 ¹⁵ to 1 × 10 ¹⁶ / cm ² . Then, the resist 18 is removed, and thermal diffusion at 1100 to 1200 ° C. is performed to form an N-type region 20 for contact.

(F) Next, the contact N-type region 20 and the region 40N which becomes the low concentration N-type region by the Zener diode.
A resist pattern 22 for covering is formed by lithography, and P-type impurities are implanted using the resist pattern 22 as a mask. The P-type impurity may be boron or BF ₂ , but, for example, the energy of boron is 30 to 50 KeV, and the dose is 1 × 10 ^{15 to} 5.
Inject at × 10 ¹⁵ / cm ² . Then, heat treatment at 850 to 1000 ° C. is performed to activate the implanted ions.
Thereby, the source region 24 and the high concentration P-type region 40P of the Zener diode are formed. As a result, the polysilicon gate electrode 26 also becomes P-type, and a high-concentration P-type region 40P and a low-concentration N-type region 40N are formed in the Zener diode region. The heat treatment temperature at this time must be set so that the implanted boron does not penetrate through the gate oxide film 12.

(G) After removing the resist 22, a PSG film or a BPSG film is formed as an interlayer insulating film 28 in a range of 5000-10.
Deposit to a thickness of 000Å to form contact holes and through holes. An aluminum or aluminum alloy film is deposited thereon and patterned by lithography and etching to form a metal wiring 30 for a source electrode and a metal wiring 32 for an input.

The power MOSFET shown in FIG. 3 can also be used alone. However, this MOSFET can be formed together with other MOSFETs on the same silicon substrate.

[0027]

According to the present invention, the impurity concentration of the N-type body of the power MOSFET and the impurity concentration of the low-concentration N-type polysilicon region of the Zener diode can be made different and can be set to optimum values independent of each other. Therefore, it is possible to optimize the basic characteristics of the MOSFET by controlling the dose amount of the N-type body, and at the same time, to optimize the basic characteristics such as the breakdown characteristics of the Zener diode and the leak current, thereby increasing the vertical power MOS semiconductor device. The characteristics of can be improved.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a front half of a conventional method for manufacturing a power MOSFET.

FIG. 2 is a process sectional view showing a second half of a conventional method for manufacturing a power MOSFET.

FIG. 3 is a cross-sectional view showing a power MOSFET of one embodiment.

FIG. 4 is a process sectional view showing a front half of a manufacturing method according to an embodiment.

FIG. 5 is a process cross-sectional view showing the second half of the manufacturing method according to the embodiment.

[Explanation of symbols]

 2 Silicon substrate 4 P type epitaxial layer 12 Gate oxide film 16 N type body 24 Source region 26 Gate electrode 40N Low concentration N type region of Zener diode 40P High concentration P type region of Zener diode

Claims (3)

[Claims] 1. An N-type body is formed on a surface of a P-type epitaxial layer on a surface of a semiconductor substrate, and a P-type source region is formed on a surface in the N-type body at a position apart from a boundary between the N-type body and the epitaxial layer. And a gate electrode is formed via a gate oxide film on the N type body region sandwiched between the source region and the exposed portion of the epitaxial layer on the surface of the epitaxial layer.
T is formed, and a Zener diode formed of a high-concentration P-type polysilicon region and a low-concentration N-type polysilicon region which are in contact with each other is connected between the gate electrode and the source region, and A vertical power MOS semiconductor device in which the impurity concentrations of the N-type body and the low-concentration N-type polysilicon region of the Zener diode are set to be different from each other according to their respective characteristics. 2. The power MOS semiconductor device is another MO.
The vertical power MOS semiconductor device according to claim 1, which is formed on the same semiconductor substrate together with the SFET. 3. An N-type body is formed on a surface of a P-type epitaxial layer on a surface of a semiconductor substrate, and a P-type source region is formed on a surface within the N-type body at a position apart from a boundary of the N-type body. On the N-type body region sandwiched between the source region and the exposed portion of the epitaxial layer on the surface of the epitaxial layer, a gate electrode is formed via a gate oxide film to form a vertical power MOSFET. A method of manufacturing a vertical power MOS semiconductor device in which a Zener diode including a high-concentration P-type polysilicon region and a low-concentration N-type polysilicon region in contact with each other is connected between the gate electrode and the source region. After depositing the polysilicon film to be the Zener diode and the gate electrode, and before patterning the polysilicon film, N-type impurities are formed on the entire surface of the polysilicon film. Implanting step, and after patterning the polysilicon film, implanting an N-type impurity to make the polysilicon film have an impurity concentration for the low-concentration N-type polysilicon region of the Zener diode, and in the epitaxial layer. And a step of implanting an impurity to form an N-type body.