JPH07202671A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To obtain an output buffer circuit having a structure which is suitable for maintaining/controlling the characteristics of the rise time and the fall time of the output waveform which depends on an external load capacity value in an optimum state. CONSTITUTION:The output of an output buffer circuit 1 where the control for changing the output impedance at the time of a rise and a fall is possible is supplied to the inputs of an external output terminal 2 and an internal buffer gate 3. A control circuit 5 compares the phases of the output signal and the input signal 4 of the buffer gate 3, generates the control information on the output buffer circuit based on this phase difference information and supplies the information to the buffer circuit 1. The change of the waveform appearing at the terminal 2 by the value of external load capacity in which the capacity value connected with the external output terminal 2 is indefinite where the rise time and the fall time of the waveform change is outputted as the change of a phase by the input threshold that the buffer gate 3 has.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, maintain the characteristics of the output waveform rise time and fall time that depend on the external load capacitance value in an optimal state.
The present invention relates to an output buffer circuit having a structure suitable for controlling.

[0002]

2. Description of the Related Art Conventionally, as an output buffer circuit capable of maintaining and controlling the rising and falling characteristics of this type,
As disclosed in Japanese Unexamined Patent Publication No. 4-258014, a configuration in which an output signal is fed back to an operational amplifier circuit and the level is compared with a reference waveform signal, thereby controlling the output impedance of a MOS transistor in an output stage; As shown in Japanese Patent Laid-Open No. 4-154314, the rising waveform and the falling waveform of the output signal are first differentiated, and then the peak value of the differentiated pulse is held, and further the overload / appropriate load / underload is determined by the peak value. A configuration is known in which the determination is made and the output impedance of the output stage is controlled.

[0003]

However, in any of the examples, these conventional output buffer circuits capable of maintaining and controlling the rising and falling characteristics are capable of detecting the state of the rising and falling waveforms and the output impedance. Is controlled using an analog circuit, it is relatively difficult to design and manufacture, and it is difficult to secure stable characteristics because it is easily affected by fluctuations in element constants. However, there is a problem in that it cannot be mounted on an integrated circuit in which only the circuit can be mounted.

An object of the present invention is to provide an output buffer circuit which eliminates the above-mentioned drawbacks.

[0005]

In order to achieve the above object, the output buffer circuit of the present invention provides the output waveform of the output buffer to the input of the phase difference detecting means via the buffer gate, and the output waveform of the phase difference detecting means is A signal input to the output buffer circuit is given to the other input, and a signal for controlling the output impedance of the output buffer circuit is generated based on the phase difference information obtained from this.

In particular, in the present invention, the phase difference detecting means, the control signal generating means, and the output impedance varying means are realized by digital circuits instead of analog circuits.

[0007]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an output buffer circuit according to an embodiment of the present invention. The output of the output buffer circuit 1 whose output impedance at rising and falling can be changed is connected to the input of the external output terminal 2 and the internal buffer gate 3. The control circuit 5 compares the phases of the output signal of the buffer gate 3 and the input signal 4, and generates control information of the output buffer circuit based on the phase difference information,
This control output is supplied to the control input of the buffer circuit 1.
The rising time and the falling time of the waveform appearing at the terminal 2 change depending on the value of the external load capacitance having an uncertain capacitance value connected to the terminal 2. This change in waveform appears as a change in phase at the output of the buffer gate 3 due to the input threshold value of the buffer gate 3. In the control circuit 5, the phase difference between the input signal 4 and the output of the gate 3 is detected by a digital circuit, and the buffer circuit 1 is detected by the digital circuit.
, The buffer circuit 1 digitally changes the output impedance.

FIG. 2 is a specific circuit diagram of the output buffer circuit of FIG.

In the figure, all drains of P-channel MOS transistors 6 and 11 to 1N and N-channel MOS transistors 7 and 21 to 2N are connected to a common external output terminal 2. The gates of all these MOS transistors are inverter gates. 8 outputs. The source of the MOS transistor 6 is connected to the power supply, and the sources of the MOS transistors 11 to 1N are connected to the power supply via the drains and sources of the P-channel MOS transistors 31 to 3N. Further, the gates of the MOS transistors 31 to 3N are independent internal input terminals 5 respectively.
1 to 5N, the source of the MOS transistor 7 is grounded, and the sources of the MOS transistors 21 to 2N are N.
Drain of channel MOS transistors 41 to 4N-
It is grounded through the source. On the other hand, the gates of the MOS transistors 41 to 4N are connected to the independent internal input terminals 61 to 6N, respectively, and the input of the inverter gate 8 is connected to the internal input terminal 10. The rising time and the falling time of the waveform appearing at the terminal 2 change depending on the value of the external load capacitance whose capacitance value connected to the terminal 2 is indefinite. This change in waveform appears as a change in phase at the terminal 9 due to the input threshold value of the inverter gate 3. In the control circuit 5, the signal given to the terminal 4 and the terminal 9
The phase difference is detected by a digital circuit, and a control signal for the buffer circuit 1 is generated by the digital circuit. By this control signal, MOS transistors 31 to 3N and 41
By opening and closing ~ 4N, the output impedance is changed stepwise independently at the time of rising and falling.

FIG. 3 is a circuit diagram showing an example of the circuit 5 for detecting the phase difference and generating the control information of the output buffer based on the detected phase difference. Clock pulses are supplied from a sufficiently high-speed clock source to the binary counters 5A1 and 5A2 provided independently for rising and falling respectively only during the phase difference between the input signals connected to the terminals 4 and 5, The phase difference is obtained as a binary value. Decoders 5C1 and 5C having pre-defined logical tables
Then, the buffer circuit 1 is controlled by the logical value obtained here.

[0012]

As described above, according to the present invention, the external output waveform is fed back by the internal buffer gate to convert the rising time and the falling time into phase information at the output of the internal buffer gate. With such a method, it is possible to detect a phase difference, generate control information, and change the output impedance. As a result, it is possible to realize an output buffer circuit that can easily maintain and control the characteristics of the output waveform in an optimum state without using any analog circuit unlike the conventional method described above.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a specific circuit diagram of an embodiment of the present invention.

FIG. 3 is a circuit diagram showing an example of a control circuit.

[Explanation of symbols]

1 Output buffer circuit whose output impedance can be changed 2 External output terminal 3 Internal buffer gate 4 Input signal 5 Circuit for generating control information 6, 11-1N, 31-3N P-channel MOS transistor 7, 21-2N, 41-4N N-channel MOS transistor 8 Inverter gate 9 Internal output terminal 10 Internal input terminal 51-5N, 61-6N Internal control information input terminal

Claims (2)

[Claims] 1. An output of an output buffer circuit whose output impedance at rising and falling can be changed is supplied to an external output terminal and an input of an internal buffer gate, and the output signal of this internal buffer gate and the output buffer are given. A semiconductor integrated circuit characterized by comparing phases of input signals, generating control information of the output buffer circuit based on the phase difference information, and controlling the output buffer circuit by the control information. 2. There are two or more P-channel MOS transistors and two or more N-channel MOS transistors, the drains of all these MOS transistors are connected to a common external output terminal, and the gates of all these transistors are provided. Is connected to the output of the inverter gate, the source of at least one of the P-channel MOS transistors is directly connected to the power supply, and the remaining P-channel MOS transistor is connected.
The sources of the transistors are connected to the power supply through the drains and sources of the P-channel MOS transistors, which are separately provided, and the P-channels M, which are separately provided, are provided.
The gates of the OS transistors are connected to independent internal input terminals, the sources of at least one of the N-channel MOS transistors are directly connected to ground, and the sources of the remaining N-channel MOS transistors are N-channel MOSs provided separately. The drain-source of the transistor is connected to the ground, the gates of the separately provided N-channel MOS transistors are connected to independent internal input terminals, respectively, and the input of the inverter gate is connected to the internal input terminal, and the buffer gate is connected. 2. The semiconductor integrated circuit according to claim 1, wherein a CMOS output buffer circuit having a configuration in which an input of the above is connected to an external output terminal and an output of a buffer gate is connected to an internal output terminal is used as the output buffer circuit.