JPH07203673A - Switching power supply - Google Patents

Switching power supply

Info

Publication number
JPH07203673A
JPH07203673A JP1315394A JP1315394A JPH07203673A JP H07203673 A JPH07203673 A JP H07203673A JP 1315394 A JP1315394 A JP 1315394A JP 1315394 A JP1315394 A JP 1315394A JP H07203673 A JPH07203673 A JP H07203673A
Authority
JP
Japan
Prior art keywords
switching element
power supply
switching
transformer
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1315394A
Other languages
Japanese (ja)
Other versions
JP3339955B2 (en
Inventor
Hiroyuki Haga
浩之 芳賀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shindengen Electric Manufacturing Co Ltd
Original Assignee
Shindengen Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shindengen Electric Manufacturing Co Ltd filed Critical Shindengen Electric Manufacturing Co Ltd
Priority to JP01315394A priority Critical patent/JP3339955B2/en
Publication of JPH07203673A publication Critical patent/JPH07203673A/en
Application granted granted Critical
Publication of JP3339955B2 publication Critical patent/JP3339955B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PURPOSE:To reduce loss and noise of a switching power supply for feeding a load with DC power by turning a series circuit of a rectifier circuit connected with a main power supply and a choke ON/OFF through a switching element and then rectifying and smoothing the output from the series circuit. CONSTITUTION:The primary coil n1 of a transformer T1 is inserted in series with a switching element SW1 and the secondary coil n2 of the transformer T1 is connected with a series circuit of an auxiliary switching element SW2 and an auxiliary power supply. The auxiliary switching element SW2 is turned OFF before the main switching element SW1 is turned ON in order to discharge the parasitic capacitor of the main switching element or an equivalent capacitor upon turn OFF of the main switching element SW1 thus attaining the objects.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はスイッチング電源装置の
スイッチング損失、及びスイッチングノイズの低減等に
関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to reduction of switching loss and switching noise of a switching power supply device.

【0002】(2)(2)

【従来の技術】スイッチング電源装置、例えば昇圧チョ
ッパは図5に示す各部から構成される。図においてPS
1は主直流電源、L1はチョ−ク、D1はダイオ−ド、C1
はコンデンサである。SW1は主スイッチング素子で、
例えばFETトランジスタが用いられる。CsはSW1の
寄生容量である。このスイッチング電源装置は、主スイ
ッチング素子SW1のスイッチングによりチョ−クL1に
エネルギ−を蓄積、放出し、その出力をダイオ−ドD
1、コンデンサC1で整流、平滑して負荷に出力するもの
である。
2. Description of the Related Art A switching power supply device, such as a step-up chopper, is composed of the respective parts shown in FIG. PS in the figure
1 is a main DC power supply, L1 is a choke, D1 is a diode, C1
Is a capacitor. SW1 is the main switching element,
For example, a FET transistor is used. Cs is the parasitic capacitance of SW1. This switching power supply device stores and releases energy in a choke L1 by switching the main switching element SW1 and outputs its output to a diode D.
1. The capacitor C1 rectifies and smoothes and outputs to the load.

【0003】[0003]

【発明が解決しようとする課題】ところで一般によく知
られるように、主スイッチング素子SW1のタ−ンオン
およびタ−ンオフに際しては損失を発生する。例えば主
スイッチング素子のタ−ンオン時であるが、タ−ンオン
の直前において、寄生容量Csは図6(a)に示すよう
に、出力電圧にほぼ等しい電圧で充電されている。そし
てこの寄生容量Csの充電電荷は、図6(b)、(c)
に示すようにタ−ンオン時に主スイッチング素子SW1
を通して放電される。この時寄生容量Csに蓄積されて
いたエネルギ−は主スイッチング素子SW1で消費さ
れ、変換効率を低下させる。また主スイッチング素子S
W1のタ−ンオン直前において、図6(d)、(e)に
示すようにダイオ−ドD1には負荷電流が流れており、
この状態でSW1がタ−ンオンして、D1に逆電圧が印加
される。順電流が流れている状態で逆電圧が印加される
ため、この時D1にはリカバリ−電流が流れ、多大な損
失および雑音を発生する問題がある。
As is generally well known, a loss occurs when the main switching element SW1 is turned on and turned off. For example, when the main switching element is turned on, but just before the turn-on, the parasitic capacitance Cs is charged with a voltage substantially equal to the output voltage as shown in FIG. 6 (a). The charge of the parasitic capacitance Cs is shown in FIGS. 6 (b) and 6 (c).
As shown in, the main switching element SW1
Be discharged through. At this time, the energy stored in the parasitic capacitance Cs is consumed by the main switching element SW1 to reduce the conversion efficiency. In addition, the main switching element S
Immediately before the turn-on of W1, as shown in FIGS. 6 (d) and 6 (e), the load current is flowing in the diode D1,
In this state, SW1 turns on and a reverse voltage is applied to D1. Since the reverse voltage is applied while the forward current is flowing, the recovery current flows through D1 at this time, and there is a problem that a large amount of loss and noise are generated.

【0004】[0004]

【発明の目的】本発明の目的とするところは、上記従来
技術の問題点を解決したスイッチング電源装置の提供に
ある。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a switching power supply device which solves the above-mentioned problems of the prior art.

【0005】(3)(3)

【課題を解決するための本発明の手段】図1は本発明の
原理説明用の回路図であって、図5と同一符号部分は同
等部分を示す。図5により前記した従来のスイッチング
電源装置において、主スイッチSW1に直列にトランス
T1を追加し、トランスの二次側n2に補助電源の役割を
するコンデンサC2と、補助スイッチング素子SW2を接
続する。本回路は、これらの追加回路とFETトランジ
スタなどによる主スイッチング素子SW1のもつ寄生静
電容量Cs及び寄生整流素子Dsの利用により低損失化と
低ノイズ化を達成しようとするもので、寄生整流素子D
s等を持たないスイッチング素子が用いられる場合には
Ds、Csに相当する素子が接続される。また寄生整流素
子Dsのリカバリ−電流が問題となる場合は、図2に示
すように補助スイッチング素子SW2に直列に整流素子
D2を接続し、さらに補助スイッチング素子SW2と前記
整流素子D2の直列回路に並列に高速の整流素子Ds2を
接続して使用する。
FIG. 1 is a circuit diagram for explaining the principle of the present invention, and the same reference numerals as those in FIG. 5 indicate the same parts. In the conventional switching power supply device described above with reference to FIG. 5, a transformer T1 is added in series to the main switch SW1, and a capacitor C2 serving as an auxiliary power supply and an auxiliary switching element SW2 are connected to the secondary side n2 of the transformer. This circuit is intended to achieve low loss and low noise by using the parasitic capacitance Cs and the parasitic rectifying element Ds of the main switching element SW1 formed by these additional circuits and FET transistors. D
When a switching element having no s or the like is used, elements corresponding to Ds and Cs are connected. When the recovery current of the parasitic rectifying element Ds becomes a problem, the rectifying element D2 is connected in series to the auxiliary switching element SW2 as shown in FIG. A high-speed rectifying element Ds2 is connected in parallel for use.

【0006】[0006]

【作用】図1、図2の回路動作について、図3を参照し
て説明する。先ず図3の時刻t0において主スイッチン
グ素子SW1がタ−ンオンすかると、チョ−クL1とトラ
ンスT1の直列回路に入力電圧が印加される。このとき
補助スイッチング素子SW2はオフしているため、トラン
スT1の二次側に電流は流れない。従ってトランスT1は
その励磁インダクタンスと等価となり、図5の昇圧チョ
ッパと同じ動作となる。時刻t1において主スイッチン
グ素子SW1がタ−ンオフすると、トランスT1にはフラ
イバック電圧が発生し、ダイオ−ドDs2を通してコンデ
ンサC2を充電する。トランスT1の電圧はコンデンサC
2の電圧でクランプされ、その電流は直線的に減少す
る。またこのときチョ−クL1の電流はダイオ−ドD1を
通して負荷に供給されるが、この動作は従来の昇圧チョ
ッパの動作と同様である。トランスT1の電流がゼロに
達する時刻をt2とする。この時SW2はオフ状態なので
トランスの二次側には電流は流れない。従って、再びト
ラ (4) ンスT1はその励磁インダクタンスと等価となり、コン
デンサCs、Cs2と共振を始める。このとき共振電流は
Cs、T1、D1、C1のル−トとCs2、T1、C2のル−ト
を流れる。
The operation of the circuits shown in FIGS. 1 and 2 will be described with reference to FIG. First, when the main switching element SW1 is turned on at time t0 in FIG. 3, an input voltage is applied to the series circuit of the choke L1 and the transformer T1. At this time, since the auxiliary switching element SW2 is off, no current flows in the secondary side of the transformer T1. Therefore, the transformer T1 is equivalent to its exciting inductance and operates in the same manner as the boost chopper of FIG. When the main switching element SW1 is turned off at time t1, a flyback voltage is generated in the transformer T1 and the capacitor C2 is charged through the diode Ds2. The voltage of transformer T1 is capacitor C
It is clamped at a voltage of 2 and its current decreases linearly. At this time, the current of the choke L1 is supplied to the load through the diode D1. This operation is similar to that of the conventional boost chopper. The time when the current of the transformer T1 reaches zero is t2. At this time, since SW2 is in the off state, no current flows in the secondary side of the transformer. Therefore, the transformer (4) T1 becomes equivalent to its exciting inductance again, and starts to resonate with the capacitors Cs and Cs2. At this time, the resonance current flows through the routes of Cs, T1, D1 and C1 and the routes of Cs2, T1 and C2.

【0007】補助スイッチング素子SW2がタ−ンオン
する時刻をT3とする。トランスT1にはコンデンサC2の
電圧が印加され、その電流は直線的に増加する。時刻t
4で補助スイッチング素子SW2がタ−ンオンすると、ト
ランス二次側には電流が流れなくなり、トランスT1は
その励磁インダクタンスと等価になって、Csと共振を
始める。このとき共振電流はCs、T1、D1、C1のル−
トで流れ、Csを放電する。Csの電圧がゼロに達したと
き、あるいは最小点に達したときに主スイッチング素子
SW1をタ−ンオンさせる事により、SW1はゼロ電圧ス
イッチング、あるいはソフトスイッチングとなり、その
スイッチング損失を大幅に減らす事が可能となる。ま
た、この時ダイオ−ドD1の電流は図3(f)に示すよ
うにゼロに近付いており、次に時刻t0でSW1がタ−ン
オンしたときに発生するリカバリ−ノイズを減らすこと
が可能である。なおダイオ−ド電流については、補助ス
イッチング素子のオン期間を調整する事により、ゼロ電
流スイッチングとする事も可能である。次に本発明の実
施例について説明する。
The time when the auxiliary switching element SW2 turns on is T3. The voltage of the capacitor C2 is applied to the transformer T1 and its current increases linearly. Time t
When the auxiliary switching element SW2 is turned on at 4, the current stops flowing to the secondary side of the transformer, the transformer T1 becomes equivalent to its exciting inductance, and starts to resonate with Cs. At this time, the resonance current is a rule of Cs, T1, D1, and C1.
To discharge Cs. By turning on the main switching element SW1 when the voltage of Cs reaches zero or reaches the minimum point, SW1 becomes zero voltage switching or soft switching, and the switching loss can be greatly reduced. It will be possible. At this time, the current of the diode D1 is close to zero as shown in FIG. 3 (f), and it is possible to reduce the recovery noise generated when the SW1 is turned on at the next time t0. is there. Regarding the diode current, zero current switching can be performed by adjusting the ON period of the auxiliary switching element. Next, examples of the present invention will be described.

【0008】[0008]

【実施例】図4は定電圧制御機能を持たせた本発明の一
実施例の回路図であって、図においてPS1は交流電
源、D1〜D5はダイオ−ド、L1はチョ−ク、C1、C2
はコンデンサ、T1はトランスである。DVは出力電圧
検出回路であって、このうちR2、R3は出力電圧の分圧
抵抗、A4は誤差増幅器、VRは出力電圧設定用基準電圧
源であって、誤差増幅器A4の出力には基準電圧と出力
電圧との誤差電圧が送出される。PCは光カップラ、R
4は電流制限抵抗、A3はスイッチング素子の駆動信号発
生回路であって、光カップラPCにより伝送される誤差
信号を受け、主スイッチング素子及び補助スイッチング
素子の駆 (5) 動信号を送出する。A1、A2は駆動回路で、Q1、Q2を
駆動する役割を果たす。Q1は主スイッチング素子であ
るFETトランジスタであって、CSはその寄生静電容
量、DSは寄生整流素子である。Q2は補助スイッチング
素子であるFETトランジスタであって、CS2はその
寄生静電容量、DS2は寄生整流素子である。
FIG. 4 is a circuit diagram of an embodiment of the present invention having a constant voltage control function. In the figure, PS1 is an AC power source, D1 to D5 are diodes, L1 is a choke, C1. , C2
Is a capacitor and T1 is a transformer. DV is an output voltage detection circuit, of which R2 and R3 are output voltage dividing resistors, A4 is an error amplifier, VR is an output voltage setting reference voltage source, and the output of the error amplifier A4 is a reference voltage. The error voltage between the output voltage and the output voltage is transmitted. PC is an optical coupler, R
Reference numeral 4 is a current limiting resistor, and A3 is a drive signal generation circuit for the switching element, which receives the error signal transmitted by the optical coupler PC and sends the drive signal (5) for the main switching element and the auxiliary switching element. A1 and A2 are driving circuits which play a role of driving Q1 and Q2. Q1 is an FET transistor which is a main switching element, CS is its parasitic capacitance, and DS is a parasitic rectifying element. Q2 is an FET transistor which is an auxiliary switching element, CS2 is its parasitic capacitance, and DS2 is a parasitic rectifying element.

【0009】[0009]

【発明の効果】以上から明らかなように、本発明によれ
ばスイッチング素子のゼロ電圧スイッチング、ダイオ−
ドのゼロ電流スイッチングが達成されて、低スイッチン
グ損失、低ノイズのスイッチング電源装置を得ることが
でき、通信回路、コンピュ−タなどの分野に好適する高
効率、低ノイズの電源を提供することが出来る。
As is apparent from the above, according to the present invention, the zero voltage switching of the switching element, the diode.
It is possible to obtain a switching power supply device with low switching loss and low noise by achieving zero current switching of the battery, and to provide a highly efficient and low noise power supply suitable for fields such as communication circuits and computers. I can.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例回路図である。FIG. 1 is a circuit diagram of an embodiment of the present invention.

【図2】本発明の一実施例回路図である。FIG. 2 is a circuit diagram of an embodiment of the present invention.

【図3】本発明の動作波形図である。FIG. 3 is an operation waveform diagram of the present invention.

【図4】本発明の一実施例図である。FIG. 4 is a diagram showing an embodiment of the present invention.

【図5】従来回路の回路図である。FIG. 5 is a circuit diagram of a conventional circuit.

【図6】従来回路の動作波形図である。FIG. 6 is an operation waveform diagram of a conventional circuit.

【符号の説明】[Explanation of symbols]

A1 駆動回路 A2 駆動回路 (6) A3 駆動信号発生回路 A4 誤差増幅器 PS1 主電源 V1 制御回路電源 Vr1 基準電圧源 T トランス SW1 スイッチング素子 SW2 スイッチング素子 C1 コンデンサ C2 コンデンサ CS コンデンサ CS2 コンデンサ D1 ダイオ−ド D2 ダイオ−ド D3 ダイオ−ド D4 ダイオ−ド D5 ダイオ−ド DS ダイオ−ド DS2 ダイオ−ド L1 チョ−ク PC 光カップラ Q1 FETトランジスタ Q2 FETトランジスタ R1 抵抗 R2 抵抗 R3 抵抗 A1 drive circuit A2 drive circuit (6) A3 drive signal generation circuit A4 error amplifier PS1 main power supply V1 control circuit power supply Vr1 reference voltage source T transformer SW1 switching element SW2 switching element C1 capacitor C2 capacitor CS capacitor CS2 capacitor D1 diode D2 diode -D D3 diode D4 diode D5 diode DS diode DS2 diode L1 choke PC optical coupler Q1 FET transistor Q2 FET transistor R1 resistor R2 resistor R3 resistor

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 主電源に整流回路を接続し、整流回路の
出力と第一のインダクタンス、第一のトランスの一次コ
イルの直列回路を第一のスイッチング素子によりオンオ
フし、第一のトランスの一次コイルと第一のスイッチン
グ素子の直列回路に並列に、第一の整流素子と第一のコ
ンデンサの直列回路を接続し、前記第一のトランスの二
次コイルには第二のコンデンサと第二のスイッチング素
子の直列回路を接続し、前記第一のコンデンサの両端に
接続した負荷に電力を供給するスイッチング電源装置に
おいて、前記第一のスイッチング素子および第二のスイ
ッチング素子として、寄生整流素子と寄生静電容量を備
えるか、またはこれに代わる整流素子と静電容量を接続
した素子を使用すると共に、前記第一のスイッチング素
子のタ−ンオン以前における第二のスイッチング素子の
タ−ンオフ時、前記第一のスイッチング素子の寄生静電
容量またはこれに代えて接続された静電容量の充電電荷
を放電することを特徴とするスイッチング電源装置。
1. A rectifier circuit is connected to a main power source, and a series circuit of an output of the rectifier circuit, a first inductance, and a primary coil of a first transformer is turned on and off by a first switching element, and a primary circuit of the first transformer is connected. A series circuit of a first rectifying element and a first capacitor is connected in parallel to a series circuit of a coil and a first switching element, and a second capacitor and a second capacitor are connected to a secondary coil of the first transformer. In a switching power supply device that connects a series circuit of switching elements and supplies electric power to a load connected to both ends of the first capacitor, a parasitic rectifying element and a parasitic static element are used as the first switching element and the second switching element. Before the turn-on of the first switching element, using an element having an electric capacity or connecting an electric capacity with a rectifying element instead of the rectifying element. The switching power supply device is characterized in that when the second switching element is turned off, the charge of the parasitic capacitance of the first switching element or the capacitance connected in place of this is discharged.
【請求項2】 請求項1において、第二のスイッチング
素子に直列に第二の整流素子を接続し、前記第二の整流
素子と第二のスイッチング素子の直列回路に並列に第三
の整流素子を接続したことを特徴とするスイッチング電
源装置。
2. The third rectifying element according to claim 1, wherein the second rectifying element is connected in series to the second switching element, and the second rectifying element and the second switching element are connected in parallel to a series circuit. The switching power supply device is characterized in that.
【請求項3】 請求項1、請求項2において、主電源に
接続した整流回路を省略した事を特長とするスイッチン
グ電源装置。
3. A switching power supply device according to claim 1, wherein a rectifying circuit connected to a main power supply is omitted.
JP01315394A 1994-01-11 1994-01-11 Switching power supply Expired - Fee Related JP3339955B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP01315394A JP3339955B2 (en) 1994-01-11 1994-01-11 Switching power supply

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP01315394A JP3339955B2 (en) 1994-01-11 1994-01-11 Switching power supply

Publications (2)

Publication Number Publication Date
JPH07203673A true JPH07203673A (en) 1995-08-04
JP3339955B2 JP3339955B2 (en) 2002-10-28

Family

ID=11825229

Family Applications (1)

Application Number Title Priority Date Filing Date
JP01315394A Expired - Fee Related JP3339955B2 (en) 1994-01-11 1994-01-11 Switching power supply

Country Status (1)

Country Link
JP (1) JP3339955B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7002323B2 (en) 2003-05-07 2006-02-21 Nec Corporation Switching power supply circuit capable of reducing switching loss and control method used therein

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7002323B2 (en) 2003-05-07 2006-02-21 Nec Corporation Switching power supply circuit capable of reducing switching loss and control method used therein

Also Published As

Publication number Publication date
JP3339955B2 (en) 2002-10-28

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