JPH07212199A - Arbitrary pulse generator - Google Patents

Abstract

PURPOSE:To make it possible to drastically reduce memory capacity in the case of pulses long in cycle and slight in change. CONSTITUTION:When an information monitoring circuit 1 and a level information control circuit 2 are initial states, addresses 10 and 11 are stored as the first interval information of a memory 3. A gate on/off signal 7 is started from a high level state so that a high speed clock 6 may be connected with the control circuit 2. The first interval information I1 is outputted to a memory output signal 12 and the level information control circuit 2 outputs an interval information set signal 8 so that this information I1 may be set to the interval information monitoring circuit 1. When a count up is performed within the monitoring circuit 1, the address 11 changes and the stored addresses are shown. The control circuit 2 makes the signal 7 a low level, performs a waveform fairing for the data where L1 and L2 level information is outputted by using a reference clock 5 for a memory output signal 12 and outputs a timing waveform 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arbitrary pulse generator, and more particularly to a digital waveform generator using a memory.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing an example of a conventional arbitrary pulse generator. The number of reference clocks 5 is counted by the counter 21, and the counter output signal 23 is connected to the address section of the memory 3. Since each waveform information is already stored in the memory 3, the memory output signal 12 is output due to the address change.

Next, the memory output signal 12 is connected to the input portion of the flip-flop 22, and waveform shaping is performed by the reference clock 5 to generate a timing waveform.

The device disclosed in Japanese Patent Laid-Open No. 4-212516 has a pulse interval storage unit for storing pulse intervals, a pulse width storage unit for storing pulse widths, and a pulse amplitude storage unit for storing pulse amplitudes. And a pulse interval detection unit that outputs a pulse interval detection signal in response to the reference clock of the reference pulse generation unit, a pulse width comparator that outputs a pulse width detection signal, and the output data of the pulse width storage unit to an analog voltage. The A / D converter for conversion generates pulses having arbitrary pulse intervals, pulse widths, and pulse amplitudes.

Further, in the apparatus disclosed in Japanese Patent Laid-Open No. 61-127222, a memory circuit is used instead of a counter for determining a pulse width and a pulse interval, and each bit of the memory circuit is set so as to correspond to each output pulse. Then, several kinds of output pulses are obtained by scanning the address corresponding to the time axis of the memory circuit for a fixed time.

[0006]

In the conventional arbitrary pulse generator, the waveform capacity to be generated requires a memory capacity larger than the value obtained by the following equation.

A --- Number of signals of waveform to be generated b --- Longest signal cycle length among waveforms to be generated 1 cycle of the reference clock is 1 c --- Minimum required If the capacity of the memory (one unit is one bit), then c = a × b.

Even if the waveform to be generated does not change so much, the memory capacity cannot be reduced by the conventional arbitrary pulse generator if the conditions a and b in the above equation are the same. .

Further, in the devices described in Japanese Patent Laid-Open Nos. 4-212516 and 61-127222, the control circuit of the memory is complicated.

[0010]

An arbitrary pulse generator according to the present invention is a waveform generator comprising a memory and a digital circuit, and level information indicating whether the waveform is at a high level or a low level and A memory section for storing interval information indicating a time period during which the waveform is held at a high level or a low level; a circuit for extracting the level information and the interval information from the memory section; and a circuit for setting data according to the level information. And a circuit for stopping the access operation to the memory during the time when the waveform does not change according to the interval information.

[0011]

Embodiments of the present invention will now be described with reference to FIGS. In the present embodiment, the number of waveform signals to be generated is two. The waveforms of the two signals A and B generated are shown in FIG.

Data is created by setting the length of time during which the signals A and B do not change and one cycle of the reference clock as one set. When this data is used as interval information, I1, I2, I3, I
4, I5.

For each interval information, it is created as data whether the signals A and B at that time indicate a high level or a low level. When the level at this time is level information, in the signal A, L1, H1, H3, L4, H5
And in the signal B, L2, H2, L3, L5, H
It becomes 5.

FIG. 3 shows how to write the interval information and the level information thus created in the memory.

Start interval information I1 of 000
Write to H. At the next address, level information L1 and L2 at the time of interval information at the start are written. At the next address, the second interval information I2 is written, and then the level information H1 and H2 at the time of the second interval information is written. In this way, the interval information and the level information are written in the memory in order.

Next, the data is retrieved from the memory storing the waveform information of the signals A and B by any method,
Whether the signals A and B are generated will be described with reference to FIG.

It is necessary to use the high speed clock 6 in order to retrieve the "interval information" and the "level information" from the memory during one cycle of the reference clock 5. The frequency of the high-speed clock 6 is selected depending on how many times the memory is accessed during one cycle of the reference clock 5 to retrieve the interval information and the level information. In this embodiment, the frequency of the high-speed clock needs to be twice as high as that of the reference clock 5.

Next, the state in which the operation starts in this embodiment will be described. When the interval information monitoring circuit 1 and the level information control circuit 2 are in the initial state, the addresses 10 and 11 are stored as the first interval information in the memory 3, as shown by 0000H in FIG. The gate on / off signal 7 starts from a high level state so that the high speed clock 6 is connected to the level information control circuit 2.

First, as the memory output signal 12, the first interval information I1 is output. The level information control circuit 2 outputs the interval information set signal 8 so as to set this in the interval information monitoring circuit 1. When counting up in the interval information monitoring circuit 1, the address 11 changes and the level information L1 and L2 indicate the stored address.

After that, the level information control circuit 2 sets the gate on / off signal 7 to the low level, and the memory output signal 12 uses the data for which the L1 and L2 level information is output, using the reference clock 5. The retiming circuit 4 shapes the waveform and outputs the timing waveform 13.

Next, the interval information monitoring circuit 1 determines whether the time of the first interval information has passed to 0.
Detected by the detection signal 9, and when the time has passed, the interval information monitoring circuit 1 counts up by 1,
Further, the level information control circuit 2 operates so that the gate on / off signal 7 is turned on. At this time, the addresses 10 and 11 indicate the addresses storing the interval information of I2.

By repeating such an operation, the signals A and B can be generated in the timing waveform 13.

Although the case where the number of waveforms is two has been described above as an example, even when the number of waveforms increases, it is realized by the circuit of the embodiment only by changing the procedure of writing data to the memory. it can. As an example, a procedure when the number of output memories is increased will be described. When the number of waveforms is up to 8, level information is written as shown in FIG. 4 and can be realized in the same manner as this embodiment.

When the number of waveforms is 24, level information is written as shown in FIG. At this time, it can be realized by the circuit of the present embodiment only by changing the number of controlling the addresses 10 and 11 of the circuit of the present embodiment.

Even when the number of waveforms is 25 or more, it can be carried out by changing the number of control of the addresses 10 and 11 as in the case of up to 24 waveforms.

[0026]

As described above, according to the present invention,
When the cycle of the signal to be generated is long and the change of the signal is small, the memory capacity can be significantly reduced. For example,
When the number of waveform signals to be generated is 8, the cycle length of the signal is 1024 cycles at maximum, and the change of the signal is 4 points,
When the conditions are good, the memory capacity is 8192 in the conventional method.
The number of bits becomes 64 bits in this embodiment.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram for explaining extraction of waveform information in this embodiment.

FIG. 3 is a diagram for explaining writing of two pieces of data to a memory in this embodiment.

FIG. 4 is a diagram for explaining writing of eight pieces of data to a memory in this embodiment.

FIG. 5 is a diagram illustrating memory writing of 24 pieces of data in the present embodiment.

FIG. 6 is a block diagram of a conventional example.

[Explanation of symbols]

 1 Interval information monitoring circuit 2 Level information control circuit 3 Memory 4 Retiming circuit

Claims (1)

[Claims] 1. A waveform generator comprising a memory and a digital circuit, wherein level information indicating whether the waveform is at a high level or a low level and time when the waveform is held at a high level or a low level are provided. A memory unit for storing the interval information shown, a circuit for taking out the level information and the interval information from the memory unit, a circuit for setting data according to the level information, and a time for which the waveform does not change according to the interval information to the memory. And a circuit that stops the access operation of the arbitrary pulse generator.