JPH07214811A - Thermal head - Google Patents

Abstract

(57) [Summary] [Object] To provide a thermal head capable of simplifying a drive circuit and improving print quality. The drive circuit 10 transfers the print data DI composed of serial data in synchronization with an external clock signal CLK to convert it into parallel data for each predetermined number of bits and outputs the shift registers SR1 to SR6.
4, the integrating circuit 15, and the strobe signal STB output from the integrating circuit 15, the shift registers SR1 to S1.
Gate elements G1 to G64 for opening and closing the output from R64
And each of the gate elements G1 to G64, the terminals H1 to H
It is composed of a plurality of switching elements T1 to T64 for controlling the current flowing through a plurality of heat generating resistors connected to 64.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printing apparatus equipped with a thermal head for performing thermal recording on a recording medium such as thermal paper, and a driving method thereof.

[0002]

2. Description of the Related Art FIG. 4 is a circuit diagram showing an electrical configuration of a thermal head which is an example of a conventional thermal head. This thermal head has a large number of heating resistors R1 to R1728.
And a plurality of driving circuits 1 and the like, 64 heating resistors are connected to one driving circuit 1, and 57
The six heating resistors and the nine driving circuits 1 are divided into a total of three blocks B1 to B3 to perform a printing operation.

FIG. 5 is a circuit diagram of the drive circuit 1 shown in FIG. The drive circuit 1 transfers the DI to the print data composed of serial data in synchronization with the clock signal CLK from the outside, thereby converting the parallel data for each predetermined number of bits and outputting the shift registers SR1 to S.
Rn and a plurality of latch circuits L1 to Ln that store the outputs of the shift registers SR1 to SRn according to a latch signal LAT from the outside, and a strobe signal STBI from the outside.
And the print control signal BEO, each latch circuit L1
To a plurality of gate elements G1 to Gn for opening and closing the outputs of Ln
And a plurality of switching elements T1 to Tn for controlling the current flowing through the heating resistors R1 to Rn by the outputs of the respective gate elements G1 to Gn.

One end of each of the plurality of heating resistors R1 to Rn formed on the thermal head is connected to each of the switching elements T1 to Tn.
n drain elements, the other ends of the heating resistors R1 to Rn are commonly connected to the output side VH of the external power source 2, and the source sides of the switching elements T1 to Tn are commonly connected. External power supply 70 to the terminal GND2
The ground side of is connected.

The operation of this thermal head is shown in FIG.
It will be described with reference to the timing chart shown in FIG. Print data D for 1728 pixels formed as one scanning line
The ATA is provided in each drive circuit 1 in synchronization with the clock signal CLK.
Are input to and transferred to the shift registers SR1 to SRn, and the print signals DATA for 64 pixels are converted into parallel data in each drive circuit 1. Next, the latch signal LAT is inverted and the shift register SR1 of the drive circuit 1 is inverted.
Outputs of SRn are stored in the respective latch circuits L1 to Ln. Next, when the print control signal BEO is inverted to the low level and the strobe signal STBI is inverted to the low level, the gate elements G1 to Gn of the drive circuit 1 corresponding to the block B1 including the heating resistors R1 to R576 are opened. hand,
Print signal DATA stored in each latch circuit L1 to Ln
Based on the above, each of the switching elements T1 to Tn is selectively turned on. Then, an electric current selectively flows through the heating resistors R1 to R576 to generate heat, heat the thermal paper or the thermal transfer film, and perform the printing operation of a portion of 1/3 of one scanning line corresponding to the block B1.

Similarly, when the strobe signal STB2 is inverted to the low level, the heating resistors R577 to R11 are similarly generated.
When a current flows selectively to 52 to generate heat, the printing operation of 1/3 of one scanning line corresponding to the block B2 is performed, and the strobe signal STB3 is inverted to a low level,
A current selectively flows through the heating resistors R1153 to R1728 to generate heat, and ⅓ of one scanning line corresponding to the block B3.
The printing operation of the part is performed. In this way, a series of images are recorded by printing one scanning line and repeating the above-described operation while stepwise conveying the thermal paper or the thermal transfer film.

However, the thermal head shown in FIG. 5 needs to have the same number of shift registers SR1 to SRn, latch circuits L1 to Ln, switching elements T1 to Tn, etc. as the number of heating resistors R1 to Rn. Since the circuit configuration of the drive circuit 9 becomes complicated and a large number of drive circuits 1 are mounted on the thermal head, there is a problem that the manufacturing cost of the thermal head is increased. Further, when the number of drive circuits 1 increases, it is difficult to reduce the size of the thermal head.

In order to solve the above-mentioned problems, the latch circuits L1 to Ln are reduced, and further, the latch signal LAT, the strobe signal STBI, and the print control signal BEO are reduced as drive signals to greatly simplify the drive circuit 1. A thermal head that can be realized is disclosed in Japanese Utility Model Laid-Open No. 5-29753.

FIG. 7 is a circuit diagram showing the electrical construction of this thermal head. The thermal head is composed of a large number of heating resistors R1 to R1728 and a plurality of driving circuits 3, and 64 heating resistors are connected to one driving circuit 3. Print data DATA and a clock signal CLK are input to each drive circuit 3.

FIG. 8 is a circuit diagram of the drive circuit 3 shown in FIG. The drive circuit 3 shifts the print data DI composed of serial data in synchronization with an external clock signal CLK to convert the print data DI into parallel data for each predetermined number of bits, and outputs the parallel data.
4 and the clock signal CLK, the shift register S
Gate elements G1 to open and close outputs from R1 to SR64
By G64 and the outputs of the gate elements G1 to G64,
A plurality of switching elements T1 to T64 for controlling the current flowing through a large number of heating resistors connected to the terminals H1 to H64.
Etc.

The operation of this thermal head is shown in FIG.
A description will be given with reference to the timing chart shown by. The print data of 1728 pixels formed as one scanning line segment is synchronized with the clock signal CLK at time T1, and the shift registers SR1 to SR64 of each drive circuit 3 are synchronized.
Is input to and transferred to each drive circuit 3, and the print data for 64 pixels is converted into parallel data in each drive circuit 3.

Next, the clock signal CLK is fixed at a high level at time T2, and the gate elements G1 to G64 of each drive circuit 3 are respectively shifted to the shift registers SR1 to SR64.
The switching elements T1 to Tn are selectively brought into a conductive state by being driven based on the print data DI stored in.
Then, an electric current selectively flows through the heating resistor to generate heat, and printing for one scanning line is performed.

[0013]

However, in the thermal head, when the clock signal CLK is at the high level and the data stored in the shift register is at the high level at the time T1 shown in FIG. A current flows through the heating resistor via the switching element and the switching element. As a result, there is a problem that unnecessary printing is performed and unnecessary heat is stored in the thermal head even during data transfer.

SUMMARY OF THE INVENTION An object of the present invention is to provide a thermal head capable of simplifying a drive circuit and improving print quality in order to solve the above-mentioned problems.

[0015]

SUMMARY OF THE INVENTION According to the present invention, a plurality of heating resistors that form a printing pixel, a plurality of switching elements that control a current flowing through each heating resistor, and a plurality of gates that open and close each switching element. An element, a shift register for transferring print data composed of serial data and outputting the print data to the plurality of gate elements, a data input terminal for inputting print data to the shift register, and opening / closing each gate element A strobe signal and a clock input terminal for inputting a clock signal for transferring print data input to the shift register, the level of the clock signal is attenuated between the clock input terminal and each gate element. It is a thermal head characterized by interposing a pulse attenuation circuit for

Further, the present invention is characterized in that the pulse attenuating circuit is an integrating circuit composed of a resistor and a capacitor.

[0017]

According to the present invention, the pulse attenuating circuit for attenuating the level of the clock signal is interposed between the clock input terminal and each gate element. Therefore, while the clock signal for transferring the print data input to the shift register from the clock input terminal is being input, the level of the clock signal is attenuated in the pulse attenuator circuit and output to the gate element as a low-level strobe signal. Therefore, each gate element does not become active. Next, by fixing the clock signal input from the clock input terminal to a high level, the level of the clock signal is not attenuated in the pulse attenuator circuit and is output to the gate element as a high level strobe signal. The element is selectively activated based on the print data stored in the shift register. With this, printing is performed.

According to the invention, the pulse attenuating circuit is an integrating circuit composed of a resistor and a capacitor. Therefore, when the width of the clock signal input to the integrating circuit is smaller than the time constant of the integrating circuit, the level of the clock signal is attenuated.

[0019]

1 is a circuit diagram showing the electrical construction of a thermal head according to an embodiment of the present invention. This thermal head is composed of a large number of heating resistors R1 to R1728 and a plurality of drive circuits 10, and 64 heating resistors are connected to one drive circuit 10. Print data DATA and a clock signal CLK are input to the drive circuit 10.

FIG. 2 is a circuit diagram of the drive circuit 10 shown in FIG. The drive circuit 10 shifts the print data DI composed of serial data in synchronization with an external clock signal CLK to convert the print data DI into parallel data for each predetermined number of bits and output the shift registers SR1 to SR1.
The shift register S is provided by the SR 64, the integrating circuit 15, and the strobe signal STB output from the integrating circuit 15.
Gate elements G1 to open and close outputs from R1 to SR64
G64 and the gate elements G1 to G64 form a terminal H1.
To H64, it is composed of a plurality of switching elements T1 to T64 for controlling the current flowing through the plurality of heating resistors.

The integrator circuit 15, as shown in FIG.
It is composed of a buffer gate element 16 for stabilizing the input, a resistor R1 and a capacitor C1.
One end of 1 is connected to the resistor R1 and the other end is the ground terminal G
The resistor R1 is connected to ND2 and is connected to the buffer gate element 1
It is connected to the clock terminal CLK via 6. The time constant τ of the integrating circuit 15 is represented by τ = R1 · C1. When the pulse width of the clock signal CLK input to the integrating circuit 15 is TP, when TP <τ, the integrating circuit 15
Clock signal C of strobe signal STB output from
The value of the voltage level for LK decreases according to the ratio of the pulse width TP and the time constant τ. If TP >> τ,
The voltage levels of the strobe signal STB and the clock signal CLK are the same, with the rise time and fall time of the strobe signal STB being slightly longer.

An actual circuit example will be described below. Resistance R1
Is 1 KΩ and the value of the capacitor C1 is 250 pF, the value of the time constant τ of the integrating circuit 15 is 0.25 μsec.
Becomes When the frequency of clock signal CLK is 4 MHz and the duty ratio is 50%, the ratio of the voltage level of strobe signal STB to the voltage level of clock signal CLK is 0.39. Therefore, when the voltage level of the clock signal is 5V, the peak value of the voltage level of strobe signal STB is 1.95V. Gate elements G1 to G6
In the case where 4 is a circuit composed of CMOS, the internal transistor stably operates at 2.5 to 3 V or higher and becomes a high level. Therefore, the clock signal CLK
, The strobe signal STB becomes low level, and the gate elements G1 to G64 are not driven.

FIG. 3 is a time chart when the thermal head shown in FIG. 1 is driven under the above-mentioned circuit conditions. The operation of the thermal head will be described with reference to this time chart. 1 formed as one scan line
The print data for 728 pixels is input and transferred to the shift registers SR1 to SR64 of each drive circuit 10 in synchronization with the clock signal CLK having a frequency of 4 MHz at time T1, and the print data for 64 pixels is provided in each drive circuit 10. Are each converted into parallel data. At this time, since the voltage level of the strobe signal STB is attenuated and becomes low level as described above, the gate elements G1 to G64 are not driven.

Next, the clock signal CLK is fixed to the high level at the time T2. This time T2 is, for example, 2 msec, which is extremely large with respect to the time constant τ, so that the strobe signal is fixed to the high level substantially in synchronization with the clock signal CLK as described above. Therefore, the gate elements G1 to G64 of the drive circuits 10 are driven based on the print data DI stored in the shift registers SR1 to SR64, and the switching elements T1 to T64 are driven.
64 is selectively turned on. Then, an electric current selectively flows through the heating resistor to generate heat, and printing for one scanning line is performed.

[0025]

As described above, according to the present invention, while the transfer clock signal of the shift register is being input from the clock input terminal, the level of the clock signal is attenuated in the pulse attenuator circuit and the strobe signal of a low level is attenuated. Is output to each gate element, the gate element is not activated. Further, by fixing the clock signal input from the clock input terminal to a high level, the level of the clock signal is not attenuated in the pulse attenuator circuit, and the clock signal is output as a high level strobe signal to each gate element. . Therefore, based on the print data stored in the shift register, each gate element is activated and printing is performed. Further, the pulse attenuating circuit can be easily realized by an integrating circuit composed of a resistor and a capacitor. As a result, the drive circuit can be simplified and the printing quality can be improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an electrical configuration of a thermal head that is an embodiment of the present invention.

FIG. 2 is a circuit diagram of a drive circuit 10 shown in FIG.

FIG. 3 is a time chart when the thermal head shown in FIG. 1 is driven.

FIG. 4 is a circuit diagram showing an electrical configuration of a conventional thermal head.

5 is a circuit diagram of the drive circuit 1 shown in FIG.

FIG. 6 is a time chart when the thermal head shown in FIG. 4 is driven.

FIG. 7 is a circuit diagram showing an electrical configuration of a conventional thermal head 3.

8 is a circuit diagram showing an electrical configuration of a drive circuit 3 shown in FIG.

9 is a time chart when the thermal head shown in FIG. 7 is driven.

[Explanation of symbols]

 1, 3, 10 drive circuit 15 integration circuit 16 buffer gate element G1 to G64 gate element SR1 to SR64 shift register R1 resistor C1 capacitor DATA printing data CLK clock signal STB strobe signal

Claims (2)

[Claims] 1. A plurality of heating resistors constituting a print pixel, a plurality of switching elements for controlling a current flowing through each heating resistor, a plurality of gate elements for opening and closing each switching element, and a print consisting of serial data. A shift register for transferring data and outputting print data to the plurality of gate elements, a data input terminal for inputting print data to the shift register, and a strobe signal for opening and closing each gate element and input to the shift register In a thermal head having a clock input terminal for inputting a clock signal for transferring the printed image data, a pulse attenuating circuit for attenuating the level of the clock signal is interposed between the clock input terminal and each gate element. A thermal head characterized by 2. The thermal head according to claim 1, wherein the pulse attenuating circuit is an integrating circuit including a resistor and a capacitor.