JPH07218450A - Lcd testing device - Google Patents

Abstract

PURPOSE:To increase the extracting speed of the end point of a linear defect by binarizing a gradation defect appears on an LCD panel module into a picture at the slice level of an adjustable gradation and constituting a (3X3)-logical filter of hardware. CONSTITUTION:A circuit means which can adjust the slice of N gradation is provided and a binarized image is obtained at a set slice level. The end point of the binarized image is found by passing the obtained binarized image through a (3X3)-logical filter constituted of hardware. The logical filter is constituted of a original binarized image memory 10, (3X3)-window circuit 15, multiplexer 14 which selects the writing address of a memory 12 for data conversion or output address of the window circuit 15, offset register 13 which selects a plurality of conversion data tables, and the memory 12 which stores logic '1' at the addresses indicating the end point, and resulted binarized picture memory 11 which indicates the position of the end point.

Description

Detailed Description of the Invention

[0001]

This invention relates to an LCD (Liquid Cri
The present invention relates to an LCD test device that extracts the end points of line defects, which are important in failure analysis of stal displays, at high speed.

[0002]

2. Description of the Related Art Conventionally, as a method for extracting end points in image processing, a method is known in which an original image of a binary image is input and a 3 × 3 logical filter is used. This 3 × 3 logical filter is subjected to weighting interpretation as shown in FIG. 5, and can represent 512 patterns of processing. This logical filter is superimposed on the original image data of the binary image as shown in FIG.
The result according to the logical filter table for distinguishing 12 patterns is displayed in the result image data. The 3 × 3 logical filter patterns indicating the end points of the vertical and horizontal lines are the four types of patterns shown in FIG. 7, and the logical 1 is set to the addresses 48, 18, 24, 144 of the logical filter table of FIG. By setting all other values to logical 0, the end points of vertical and horizontal lines can be displayed in the resulting image data.

In a conventional LCD test apparatus, an image of an LCD panel module is captured at a slice level of one brightness that has been set, and the image is processed by software in the above-described 3 × 3 logical filter system to extract end points. Therefore, the difference in brightness of the end points cannot be separated, and a long processing time is required for the end point extraction.

[0004]

As described above, in the conventional LCD device, the adjustment of the slice level of the brightness when binarizing the image is required to speed up the process of the 3 × 3 logical filter. It was The present invention speeds up the extraction of end points of line defects by converting a defect having light and shade appearing in an LCD panel module into a binary image with an adjustable light and dark slice level and realizing a 3 × 3 logical filter by hardware. It is an object.

[0005]

In extracting end points of a line defect of an LCD, image data obtained from the LCD includes a dark line defect, a thin line defect, a dark point defect, a thin point defect, and the like.
Mixed at various levels. In order to extract defects having a darkness of a certain level or more from this, a circuit means capable of adjusting the dark and light slice levels is provided to obtain a binary image at the set slice level. A 3 × 3 logical filter configured by hardware for extracting end points is an original image binary image memory 10 that stores a binarized original image, and an original image binary image memory 10 in the horizontal direction one pixel at a time from the upper row. And a 3 × 3 window circuit 15 which uses a horizontal pixel delay circuit and a flip-flop to match the columns of three consecutive rows so that the 3 × 3 matrix data is output in the same cycle. And a B input for inputting a write address when setting the memory 12 for data conversion, or an A input for inputting an output address for inputting an output address in which columns of three consecutive rows of the 3 × 3 window circuit 15 match. An offset register 13 for selecting a table # of the data conversion memory 12 including a plurality of conversion data tables, and a conversion data table The output data of the data conversion memory 12 and the data conversion memory 12 configured by a plurality of conversion data tables that store logical 1s at addresses indicating end points and logical 0s at all other addresses are 3 × 3. The result is a binary image memory 11 which stores F / F4, which is the central address of the window circuit 15, at the output address.

[0006]

In this 3 × 3 logical filter, by setting logical 1 or logical 0 in correspondence with 512 kinds of matrices, image contraction, image expansion, image contour extraction, intersection points other than end point extraction Extraction, isolated point extraction, line smoothing,
It can be applied to density detection and the like.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 4 shows a flow of extracting dark line defects from light and dark line defects of an LCD panel module and obtaining addresses of end points of the dark line defects. FIG. 4A shows image data obtained from the LCD panel module, in which dark line defects, thin line defects and thin point defects are mixed. In FIG. 4B, since only the dark line defect is binarized, the slice level for binarizing the light and shade is increased. By adjusting the slice level, it is possible to obtain binary images with various shades. In FIG. 4C, the end points of the vertical line and the horizontal line are obtained by the 3 × 3 logical filter. The end point obtained here is LC
This is one of the important points in pursuing the cause in the failure analysis of D.

FIG. 1 shows a block diagram of a circuit for finding the end point of a line defect from an original binary image memory including a 3 × 3 logic filter. The 3 × 3 logical filter reads the original image binary image memory 10 before inputting to the filter and the original image binary image memory 10 one pixel at a time in the horizontal direction in order from the upper row, and the horizontal pixel delay circuit and the flip-flop circuit are read. Pull 1 (F / F1)
From F / F7 to match the columns in three consecutive rows,
A 3 × 3 window circuit 15 that performs cycle adjustment so that 3 × 3 matrix data is output in the same cycle.
And a B input for inputting a write address when setting the memory 12 for data conversion, or an A input for inputting an output address for inputting an output address in which columns of three consecutive rows of the 3 × 3 window circuit 15 match. And an offset register 13 for selecting a table # of the data conversion memory 12 composed of a plurality of conversion data tables, a logical 1 at an address indicating an end point of the conversion data table, and a logical 0 at all other addresses. Data conversion memory 12 configured by a plurality of conversion data tables for storing data and output data of the data conversion memory 12 is 3 × 3.
It is composed of the binary image memory 11 which stores the result at the address output from the F / F 4, which is the central address of the window circuit 15.

In order to operate the 3 × 3 logic filter, it is first necessary to write logic 1 to the address indicating the end point of the data conversion memory 12. Input B of multiplexer 14
Is selected, an address indicating the end point of the data conversion memory 12 is designated, and a logical 1 is written to the address. Here, since the addresses indicating the end points of the vertical and horizontal lines are 48, 18, 24 and 144 shown in FIG. 7, a logical 1 is written in that address and a logical 0 is written in the other addresses. The offset register 13 is used to switch and specify a plurality of conversion data tables, and in this example, 128 conversion data tables can be specified.
When the writing of the conversion data to the data conversion memory 12 is completed, the 3 × 3 logic filter can be operated.

FIG. 2 shows a timing chart when the 3 × 3 logic filter is operated. The original binary image memory 10 is
The horizontal pixels in the top row are moved from left to right 1.1 → 2.
The output is 1 → 3.1 → 4.1 → 5.1 → 6.1, and when the right end is output, the pixels in the row immediately below in the vertical direction are changed to 1.2.
→ 2.2 → 3.2 → 4.2 → 5.2 → 6.2
In the same manner, the vertically downward continuous rows are output until there are no more pixels in the vertical direction.

This output is input to F / F1 and F / F1
Is output to the F / F2 and the horizontal pixel delay circuit DL1. The output of F / F2 is input to F / F3, and F / F3
The outputs of F1, F / F2 and F / F3 are input to the addresses A0, A1 and A2 of the data conversion memory 12 through the multiplexer 14, respectively. The output of the horizontal pixel delay circuit DL1 is started in synchronization with the output of the F / F1 outputting the data 1.2 of the second row, and is simultaneously input to the F / F4 and the horizontal pixel delay circuit DL2. .
The output of F / F4 is input to F / F5, and DL1, F / F
4 and F / F5 are output to the addresses A3, A4, A5 of the data conversion memory 12 and the multiplexer 1 respectively.
Input through 4. The output of the horizontal pixel delay circuit DL2 starts in synchronization with the output of the F / F1 outputs the data 1.3 of the third row and the output of DL1 outputs the data 1.2 of the second row. And simultaneously input to F / F6. The output of F / F6 is input to F / F7, and DL2, F
The outputs of / F6 and F / F7 are input to the addresses A6, A7, and A8 of the data conversion memory 12 through the multiplexer 14, respectively. F / F7 output is 3 × 3 in the cycle of timing A at which the data 1.1 of the first row is output.
The first cycle of the nine matrix data of the window coincides with each other, the data is input as an address to the data conversion memory 12 through the multiplexer 14, and the resulting output of the data conversion memory 12 is a 3 × 3 window circuit. F / F4, which is the central address of 15, is used as an address, and the resultant binary image memory 11 is written. After that, nine matrix data of 3 × 3 windows obtained in each cycle of the subsequent timing are used as addresses and are input to the data conversion memory 12 through the multiplexer 14, and the resulting output of the data conversion memory 12 is output. F / F4, which is the central address of the 3 × 3 window circuit 15, is written as an address in the result binary image memory 11, and the same operation is executed up to the last column of the last row.

FIG. 3 shows the relationship between the data conversion memory 12 and the offset register 13. 9 in 3x3 matrix
As shown in FIG. 3, the individual pieces of data are input to addresses A0 to A8 of the data conversion memory 12. This makes 2
Logical filters can be set corresponding to ⁹ = 512 matrixes. Also, the offset register 1
The output of 3 is input to addresses A9 to A15 of the data conversion memory 12, and a total of 2 ⁷ = 128 conversion data tables can be designated. For example, as an example of the end point extraction logical filter shown in FIG.
48 is logical 1 and all other logical 0s, offset register # 1 address # 18 is logical 1 all other logical 0s, offset register # 2 address # 24 is logical 1 and all other logical 0,
By setting the address # 144 of the offset register # 3 to be logical 1 and the other addresses to be logical 0, the end point of the horizontal line extending from the left when passing through the offset register # 0 logical filter is the offset register # 1 logical filter. The end point of the vertical line extending from the bottom when passing through the register, the end point of the horizontal line extending from the right when passing through the offset register # 2 logical filter, and the end point when passing through the offset register # 3 logical filter. The end points of the vertical line extending from can be detected. As a result, the four types of end points are detected by being distinguished by different conversion data tables, and as a result, the binary image memory 1
By separately handling with 1, it is possible to perform failure analysis by distinguishing each end point.

[0013]

Since the present invention is constructed as described above, a line image having a light and shade appearing in an LCD panel module is converted into a binary image at an adjustable slice level and a 3 × 3 logical filter circuit is used. Thus, the end points can be extracted at high speed, and the cause of the defect can be efficiently investigated by analyzing the end points. Further, since there are a plurality of conversion data tables of this logical filter and the pattern of the logical filter can be changed in real time by changing the contents of the offset register, there is an effect that the types of end points can be immediately classified.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a 3 × 3 logical filter of the present invention.

FIG. 2 is a timing diagram of the 3 × 3 logic filter of the present invention.

FIG. 3 is an explanatory diagram showing a relationship between a data conversion memory and an offset register of the present invention.

FIG. 4 is an explanatory diagram showing a flow of obtaining an end point of the present invention.

FIG. 5 is an explanatory diagram of interpretation of weighting in a 3 × 3 logical filter.

FIG. 6 is an explanatory diagram of a method of using a 3 × 3 logical filter.

FIG. 7 is a 3 × 3 logical filter pattern showing end points of vertical and horizontal lines.

[Explanation of symbols]

 10 original image binary image memory 11 result binary image memory 12 data conversion memory 13 offset register 14 multiplexer 15 3 × 3 window circuit

Claims (1)

[Claims] 1. A method for obtaining a binary image by controlling a slice level for binarizing a gray scale of a defect in extracting an end point of a line defect of an LCD, and an original binary image memory for storing the binarized original image ( 10)
Then, the original image binary image memory (10) is sequentially read from the upper row one pixel at a time in the horizontal direction, and the horizontal pixel delay circuit and the flip-flop are used to match the columns of three consecutive rows,
A 3 × 3 window circuit (1 that performs cycle adjustment so that 3 × 3 matrix data is output in the same cycle)
5) and one input for inputting the write address when setting the data conversion memory (12), or the output address where the columns of three consecutive rows of the 3 × 3 window circuit (15) match. A multiplexer (14) for selecting the other input, an offset register (13) for selecting the table number of a data conversion memory (12) composed of a plurality of conversion data tables, and an address indicating the end point of the conversion data table. The data conversion memory (12), which is composed of a plurality of conversion data tables that store logical 1s in the memory, and logical 0s in all other addresses, and output data from the data conversion memory (12) are 3 × 3. Result binary image memory (11) to be stored in the center address of the window circuit (15), and an LCD test comprising the above Location.