JPH07219480A - Counter circuit - Google Patents

Abstract

PURPOSE:To simplify the peripheral circuit of a counter by adding a reset function to the counter circuit. CONSTITUTION:A counter 11 is integrated with a comparator 15 on the same semiconductor substrate 10. The counter 11 counts the clocks inputted from a clock input terminal 12, and it is reset by the comparison output of the comparator 15. The carry signal of the counter 11 is outputted from an output terminal 13 as the start pulse and the comparison output of the comparator 15 is outputted from an output terminal 18 as the reset pulse.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a counter circuit having a reset function.

[0002]

2. Description of the Related Art In a liquid crystal display panel (LCD panel) mounted on a portable computer or the like, a drive circuit having a shift register structure which operates by a clock having a constant cycle is used. This driving circuit includes a horizontal driver that horizontally scans the display pixels of the LCD panel and a vertical driver that vertically scans the display pixels. The display pixel scanned by the vertical driver for each row is equivalent to one row provided from the horizontal driver. Is configured to display the display data of the.

FIG. 6 is a block diagram showing the configuration of an LCD panel and its drive circuit, and FIG. 7 is a timing diagram for explaining its operation. The LCD panel 1 is arranged such that m scanning electrodes and n signal electrodes are orthogonal to each other and face each other with a liquid crystal interposed therebetween, and these electrodes form display pixels of m rows × n columns. It is defined. The X driver 2 is composed of an n-bit shift register corresponding to n signal electrodes, takes in display data that is continuously input in units of one row in accordance with a drive clock having a constant cycle, and takes in the displayed data at the same timing. Supply to each signal electrode. The Y driver 3 is composed of an m-bit shift register corresponding to m scan electrodes, and sequentially shifts the scan electrodes one by one by sequentially shifting a start pulse having a pulse width of one clock in accordance with the drive clock. .
The driver control circuit 4 is composed of a counter that operates according to a reference clock, and divides the reference clock into a predetermined cycle to generate a drive clock for the drivers 2 and 3 and a start pulse for the Y driver 3. For example, the reference clock is output as the drive clock of the X driver 2 in the same cycle, and this clock is divided into 1 / n and output as the drive clock of the Y driver 3. Further, the drive clock of the Y driver 3 is further divided into 1 / m to generate a start pulse and output to the Y driver 3. Therefore, each time the X driver 2 receives a drive clock of n clocks, Y
The drive clock of 1 clock is given to the driver 3,
In addition, the next start pulse is input every time the Y driver 3 is supplied with m driving clocks.

The display data corresponding to the LCD panel 1 is
For example, white / black information is represented by 1/0, and one pixel information is associated with one clock period of the reference clock. Then, 1 is set by consecutive n-bit data.
Information for one line is represented, and information for one screen is represented by m lines of this information. The display data is sequentially input to the X driver 2 from the first row to the m-th row in n-bit units (one-row unit), and sequentially scanned by the Y driver 3 from the first row to the m-th row. Are displayed on the display pixels of the LCD panel 1. That is, since the n-bit display data is repeatedly captured by the X driver 2 and the scanning electrodes driven by the Y driver 3 are advanced by one row each time the display of the captured display data is completed, the first row of the LCD panel 1 is driven. Information corresponding to the display data is continuously displayed from the first line to the m-th line. Note that this display data is continuous on a screen-by-screen basis, and after the display of one screen is completed, the display data on the first line of the next screen is X.
It is input to the driver 2.

Incidentally, in the LCD panel 1, in order to prevent deterioration of the liquid crystal due to a DC electric field, an AC voltage is usually applied to the scanning electrodes and the signal electrodes. That is, an alternating electric field is generated between the scanning electrode and the signal electrode, and the electric field applied to the liquid crystal is constantly inverted to prevent the generation of an ion current, thereby preventing the liquid crystal from being deteriorated. There is. When driving is performed with such an AC voltage, the drive circuit may not operate normally due to fluctuations in the power supply voltage, and a DC voltage may be applied to the LCD panel 1 to deteriorate the liquid crystal. A protection circuit is provided for detecting the above and stopping the operation of each driver 2, 3. In particular, in a portable computer using a built-in battery as a power source, the power supply voltage is likely to drop, so a protection circuit is indispensable. This protection circuit is composed of, for example, a comparison circuit that compares the power supply voltage with a constant reference voltage. When the output of the comparison circuit is inverted, the operation of each driver 2, 3 is stopped and the voltage to the LCD panel 1 is reduced. I am trying to cut off the supply of.

[0006]

In the protection circuit as described above, when the abnormality of the power supply voltage is detected, the drivers 2 and 3 are stopped regardless of the operation of the driver control circuit 4. The driver control circuit 4 does not enter the initial state after activating, and an initial setting operation is required when the drive circuit is activated again. For example, a counter that divides the reference clock by 1 / n to create a drive clock for the Y driver 3 and a counter that further divides the drive clock by 1 / m and creates a start pulse are restarted unless reset. I can't let you do it.

However, in order to add the reset function to the driver control circuit 4, it is necessary to provide a voltage comparison circuit together with the counter, which increases the number of parts when configuring the driver control circuit 4, and further, The wiring for connecting the drivers 2 and 3 and the driver control circuit 4 is complicated. Normally, the drivers 2 and 3 of the LCD panel 1 and the driver control circuit 4 are integrally configured as a module together with the LCD panel 1, so that if the number of components increases or the wiring becomes complicated, the cost of the module increases. .

Therefore, an object of the present invention is to add a reset function to the counter itself to minimize the increase in the number of components and the complication of wiring.

[0009]

The present invention has been made to solve the above-mentioned problems, and is characterized in that it responds to the rising or falling timing of a given clock pulse and is constant. The counting means repeats the counting operation in a cycle of, and the comparing means which compares the taken-in voltage with a predetermined reference voltage and resets the counting means according to the comparison result.

[0010]

According to the present invention, by providing the comparing means together with the counting means, when the power supply voltage is lowered and the output of the comparing means is inverted, the counting means is initialized at the same time as its reset signal. Is output. If the reset signal is used as a control signal for a circuit which operates by receiving the count output of the counting means, the circuit operation can be matched with the operation of the counting means.

[0011]

1 is a block diagram of a counter circuit of the present invention. The counter 11 performs a counting operation with a clock input from the clock input terminal 12, and generates a carry signal when counting a predetermined number of clocks.
The carry signal is output as a start pulse from the output terminal 13 and at the same time used as a load signal for controlling the loading of the preset data supplied to the preset data input terminal 14 into the counter 11. Thereby, the counter 11 is configured to start the counting operation with the preset data as the initial value, output the carry signal when the count value overflows, and fetch the preset data again. Therefore, it is possible to obtain a start pulse in which the clock applied to the clock input terminal is divided at a rate corresponding to the number of counting operations of the counter 11.

The comparator 15 has two input terminals 1
The monitor voltage and the reference voltage given to 6 and 17 are taken in, and the comparison result is output from the output terminal 18 as a reset pulse. Also, this reset pulse
It is used as a reset signal for the counter 11, and the counter 11 is reset when the comparison result of the comparator 15 is inverted. Here, if the start pulse output from the counter 11 is taken out as the logical sum of the reset pulse and the reset pulse, the output of the start pulse can be prohibited at the timing when the counter 11 is reset.

The monitor voltage applied to the input terminal 16 is
For example, as shown in FIG.
It is taken out after being divided by 1, 22. Here, the capacitor 23 is connected to the connection point of the pair of resistors 21 and 22 to prevent spike noise and the like from being taken into the comparator 15. Also, the input terminal 17
The reference voltage applied to the power supply maintains a constant level without being affected by the fluctuation of the power supply voltage. Similarly, as shown in FIG. 2, the connection of the resistor 24 and the diode 25 connected in series between the power supply grounds. Taken out from a point. Therefore, this reference voltage is always maintained at a level higher than the ground voltage by the threshold voltage of the diode 25. The reference voltage is set lower than the monitor voltage in a normal state, and the output of the comparator 15 is inverted when the power supply voltage drops to a predetermined level and the monitor voltage becomes lower than the reference voltage. There is.

The counter 11 and the comparator 15 described above
Are integrated on the same semiconductor substrate 10 and configured as a single integrated circuit element. At this time, the resistor 21 for extracting the monitor voltage and the reference voltage,
The elements 22 and 24 and the diode 26 may be externally attached to the substrate 10, but may be integrated and formed on the substrate 10.

In the case of the master slice type integrated circuit device, the counter 11 and the comparator 15 are integrated into one functional cell, and various circuits are added to the functional cell to form a control circuit having a one-chip configuration. Since such a master slice type integrated circuit element can be applied to various systems by combining functional cells, it can be applied in a wide range.

FIG. 3 is a circuit diagram of a comparator 15 having a MOS transistor configuration so that it can be formed on the same substrate as the counter 11. The two P-channel type MOS transistors 31 and 32 are connected to a power source, and the gates and drains of these MOS transistors 31 and 32 are connected to each other. MOS transistors 31, 3
N-channel type MOS transistors 33 and 34 are connected to the drains of the two, respectively, and a reference voltage and a monitor voltage are applied to the gates of these MOS transistors 33 and 34, respectively. The sources of the MOS transistors 33 and 34 are grounded via the N-channel MOS transistor 35 for controlling ON / OFF of circuit operation. The first determination circuit 30 is formed by the two P-channel type MOS transistors 31 and 32 and the three N-channel type MOS transistors 33, 34 and 35.
And two outputs a1 and a2 are obtained from the drain sides of the MOS transistors 31 and 32.

The two MOS transistors 41 and 42 are P-channel type MOS transistors 43 for controlling operation.
Connected to the power source through the gates of the MOS transistors 41 and 42, and the output a1 of the first determination circuit 30
a2 is applied. The drains of the MOS transistors 41 and 42 are respectively connected to N-channel type MOS transistors 44 and 45 whose sources are grounded, and their gates are both connected to the drain side of the MOS transistor 44. These three P-channel type MOS transistors 41, 42 and 43 and the two N-channel type MOS transistors 44 and 45 constitute the second determination circuit 40, and the output b is obtained from the drain side of the MOS transistor 42. And a pair of MOS transistors 5
1, 52 are connected in series between the power supply grounds, and the output b of the second determination circuit 40 is applied to the gates of the MOS transistors 51, 52. This pair of MOS transistors 5
1, 52 constitute an output buffer circuit 50,
Comparative output c from the connection point of the MOS transistors 51 and 52
Is obtained.

Next, the comparison operation of this comparator will be described. First, when the monitor voltage is higher than the reference voltage, the resistance value of the MOS transistor 34 is M
It becomes lower than the resistance value of the OS transistor 33, and at the same time,
The resistance value of the MOS transistor 32 becomes higher than the resistance value of the MOS transistor 31. Therefore, the first output a1
The second output a2 becomes a lower voltage than the second output a2
The resistance value of the MOS transistor 42 receiving the first output a1 becomes lower than the resistance value of the MOS transistor 41 receiving the first output a1. The second determination circuit 40, which is a current mirror circuit, is M
Since the currents flowing through the OS transistors 42 and 45 act in proportion to the currents flowing through the MOS transistors 41 and 44, when the resistance value of the MOS transistor 42 becomes lower than the resistance value of the MOS transistor 41, the potential on the drain side of the MOS transistor is increased. That is, the output b approaches the power supply voltage. Then, in the buffer circuit 50 receiving this output b, the MOS transistor 51 is turned off and the MOS transistor 52 is turned on, so that the output c becomes the ground potential.

On the other hand, when the monitor voltage drops and becomes lower than the reference voltage, conversely, the resistance value of the MOS transistor 34 becomes higher than the resistance value of the MOS transistor 33, and the resistance value of the MOS transistor 32 becomes the resistance value of the MOS transistor 31. Will be lower. As a result, the second output a2 has a higher voltage than the first output a1, and the resistance value of the MOS transistor 42 becomes higher than the resistance value of the MOS transistor 41, so that the output b approaches the ground voltage. Then, the MOS transistor 51 receiving this output b is turned on, the MOS transistor 52 is turned off, and the output c becomes the power supply potential.

Such a comparator having a MOS transistor structure undergoes a special manufacturing process in which a MOS type element and a bipolar type element are mixedly mounted on the same semiconductor substrate as the counter which is entirely composed of MOS transistor circuits. Can be easily integrated. FIG. 4 is a block diagram showing another embodiment. In this figure, the counter 11 and the comparator 15 are the same as those in FIG. 1, and are configured to reset the counter 11 according to the comparison output of the comparator 15.

The counter 11 counts according to the clock input from the clock input terminal 12 after being initialized to a predetermined value, and inputs the count output to the decoder 19. The decoder 19 decodes the count output of the counter 11 and generates a timing pulse at the timing when the count and the output match the preset decode value. Since the decode value of the decoder 19 is input from the preset data input terminal 20 and set in the decoder 19 in advance, it is not necessary to externally supply the preset data during the subsequent operation. When the decoder 19 is provided in this way, the peripheral circuit can be simplified as compared with the case of FIG. It is also possible to take out the count output of the counter 11 as it is and use it without using the decoder 19.

FIG. 5 is a block diagram showing a configuration in the case where the counter circuit of the present invention is used as the drive circuit of the LCD panel. The reference clock is supplied to the X driver 2 as a drive clock while counting the counter 5. The counter 5 counts the reference clock after preset data is set, and generates a carry signal when a predetermined number of counts are completed, thereby dividing the reference clock into 1 / n. The frequency-divided output obtained here, that is, the clock obtained by frequency-dividing the reference clock by 1 / n, is supplied to the Y driver 3 as a drive clock while counting the counter 11. The counter 11 receives the divided clock, further divides it into 1 / m to create a start pulse, and supplies it to the Y driver 3. The frequency dividing operation by these two counters 5 and 11 is the same as the frequency dividing operation of the counter 11 shown in FIG. The comparator 15 formed integrally with the counter 11 on the substrate 10 is
Upon receiving the monitor voltage obtained by dividing the power supply voltage and the reference voltage maintained at a constant level, the output is inverted and the counter 11 is reset when the monitor voltage becomes lower than the reference voltage. At the same time, the reset pulse is applied to the drivers 2 and 3 to stop the power supply of the LCD from the drivers 2 and 3. Therefore, when the power supply voltage drops and the output of the comparator 15 is inverted,
The power supply from the drivers 2 and 3 to the LCD panel 1 is cut off, the LCD panel 1 is turned off, and the counter 11 is reset to the initial state.

In this way, if the comparator 15 and the counter 11 are integrated into one chip to form the drive circuit of the LCD panel 1, the number of parts does not increase due to the addition of the protection circuit (comparator 15), and the wiring becomes complicated. Can also be prevented. In addition to the drive circuit of the LCD panel 1 as described above, the counter circuit of the present invention can be adopted in a system in which a count function and a reset function are required at the same time. For example, the CPU (Central Process) of a microcomputer
ing unit), which is used when a predetermined instruction is generated in accordance with the reset operation of the

[0024]

According to the present invention, by adding the reset function to the counter circuit, the peripheral circuit of the counter can be simplified and the cost of the device using this counter circuit can be reduced. Further, in the master slice type semiconductor device, by configuring the counter circuit including the comparator as one reference cell, it is possible to easily cope with various systems.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a counter circuit of the present invention.

FIG. 2 is a configuration diagram of a circuit that generates a monitor voltage and a reference voltage.

FIG. 3 is a circuit diagram of a comparator having a MOS transistor configuration.

FIG. 4 is a block diagram showing another embodiment of the present invention.

FIG. 5 is a block diagram when the counter circuit of the present invention is used as a drive circuit for an LCD panel.

FIG. 6 is a block diagram showing a configuration of a drive circuit of an LCD panel.

FIG. 7 is a timing diagram illustrating the operation of the drive circuit of the LCD panel.

[Explanation of symbols]

 1 LCD Panel 2 X Driver 3 Y Driver 4 Driver Control Circuit 10 Semiconductor Substrate 11 Counter 15 Comparator 19 Decoder 30 First Judgment Circuit 40 Second Judgment Circuit 50 Buffer Circuit

Claims (2)

[Claims] 1. A counting means that repeats a counting operation in a constant cycle in response to a rising or falling timing of a given clock pulse, and the captured voltage is compared with a predetermined reference voltage, and the count is performed according to the comparison result. A counter circuit for resetting the means. 2. A counting unit that repeats a counting operation at a constant cycle in response to a rising or falling timing of a given clock pulse, and a setting unit that sets preset data in the counting unit each time the counting operation is repeated. , A comparing means for comparing the power supply voltage with a predetermined reference voltage and resetting the counting means when the power supply voltage becomes equal to or lower than the reference voltage, integrated on a common semiconductor substrate, and the counting result of the counting means And obtain a timing pulse with a constant period from
A counter circuit, wherein a reset pulse is obtained from a comparison result of the comparison means.