JPH07219670A - CPU power saving method - Google Patents

Abstract

(57) [Abstract] [Purpose] To keep the CPU clock frequency down while executing key input processing. A key input processing state determining means for determining whether or not a key input processing is being executed in an information processing apparatus having a CPU clock switching means, and the key input processing state determining means. An information holding circuit for storing the determination result and a control means for sending a switching signal to the clock switching means based on the contents stored in the information holding circuit are provided. [Effect] Since the state of key input processing can be accurately determined and the clock frequency of the CPU can be kept low during execution of the key input processing, the power consumption of the CPU can be reduced without impairing the usability for the user.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power saving system for information processing equipment, and more particularly to a power saving system suitable for reducing power consumption of a CPU during execution of key input processing.

[0002]

2. Description of the Related Art Some small-sized information processing devices that are portable have power supplied by a battery. In order to extend the driving time on the battery and improve the usability, it is necessary to reduce the power consumption of each component of the small information processing device.

To reduce the clock frequency of the CPU is
It is generally known as one of the methods for reducing power consumption. However, since the clock frequency of the CPU affects the performance of the information processing device, it cannot be simply lowered. Therefore, many power saving methods have been developed and disclosed. Here, the power saving system of the CPU will be described by taking the system disclosed in Japanese Patent Laid-Open No. 4-130510 as an example.

In the method disclosed in the publication, the key input waiting determination means detects that the information processing device is in a key input waiting state. The key input waiting discriminating means discriminates the key input waiting state from the calling state of the key sense routine, and outputs a signal indicating the key input waiting state to the control means. The control means measures the elapsed time from when the signal is received. When this elapsed time exceeds a predetermined time, the control means outputs a signal for lowering the clock frequency of the CPU to the clock switching means. This reduces the clock frequency supplied to the CPU. On the other hand, when a key input occurs, the key input waiting determination means outputs a signal indicating that the key input waiting state is not in the key input waiting state to the control means. Receiving this, the control means outputs a signal for increasing the CPU clock frequency to the clock switching means, and the clock switching means restores the frequency of the clock supplied to the CPU to the original.

According to the above method, when the user interrupts the work of the information processing device and leaves the information processing device, the power consumption of the CPU can be reduced and the driving time by the battery can be extended. Further, since the key input state is determined by using the key sense routine which does not depend on the application program, there is an advantage that the clock frequency of the CPU can be lowered without changing the application program to reduce the power consumption.

[0006]

In the case of the above-mentioned method, if the user does not hit the key for a certain period of time, the low-speed clock is supplied to the CPU. Conversely, the key input occurs continuously. The case is that a high clock is always supplied to the CPU. In other words, during key input processing, the CPU
Power consumption cannot be reduced. However, the key input process is considered to be one of the processes that does not require the performance of the information processing device. This is because the key touch speed of the user is considered to be much slower than the key input speed of the CPU. Even if the clock frequency of the CPU is lowered while executing the key input process, it is possible to reduce the power consumption without making the user feel a reduction in usability. The method shown in the prior art does not consider this point.

An object of the present invention is to keep the clock frequency of the CPU lowered during the key input processing in the information processing apparatus having the CPU clock frequency switching means. As a result, the power consumption of the CPU is reduced and the battery drive time of the information processing device is extended without impairing the usability.

[0008]

Generally, when an application program performs key input processing, it calls a key sense routine in the BIOS routine. Key sense
A BIOS routine such as a routine is provided as standard in the information processing device and can be commonly used by each application program. When the application program is performing key input processing, the key sense routine is continuously called. Therefore, the key
The execution of the sense routine can be considered when the application program is executing the key input processing.

In order to achieve the above object, a key input processing state determining means for determining whether or not the information processing apparatus is executing the key input processing from a key sense routine is provided. Further, information holding means for holding the judgment result of the key input state judging means is provided. Further, there is provided control means for sending a switching signal to the clock switching means based on the contents stored in the information holding means.

[0010]

According to the present invention, when the application program calls the key sense routine, the key input processing state determining means determines that the application program is in the key input processing state,
The judgment result is stored in the information holding means. Then, based on the contents stored in the information holding means, the control means sends a signal for lowering the CPU clock to the clock switching means. On the other hand, when the key sense routine is completed, the key input state determination means determines that the application program is not in the key input processing state. When this determination result is stored in the information holding means, the control means sends a signal for raising the CPU clock to the clock switching means.

As described above, according to the present invention, since the clock frequency of the CPU can be kept low in the key input processing state, it is possible to reduce the power consumption of the CPU, and
There is no reduction in usability due to lowering the clock frequency.

[0012]

EXAMPLES Examples of the present invention will be described below.

FIG. 1 shows the overall structure of the present invention. The CPU 101 includes a ROM 102 for storing a BIOS routine such as a key sense routine, a RAM 103 for storing an application program, an input / output device 104 for inputting / outputting data, and a keyboard 10 for data input.
5 are connected via the system bus 109. The information holding circuit 106 is also connected to the system bus 109, and the determination result of the key input processing state determination means is CP.
It is stored in the information holding circuit 106 by U101. A control circuit 107 is connected to the information holding circuit 106, and a clock switching circuit 108 is further connected to the control circuit 107. The control circuit 107 includes the information holding circuit 10
A clock switching signal is sent to the clock switching means 108 according to the data held by 6. On the other hand, the CPU 10
One of the high clock 110 and the low clock 111 is supplied to 1 by the clock switching circuit 108. The high clock 110 has a higher frequency than the low clock 111 and is for operating the CPU 101 at high speed. The low clock 111 operates the CPU 101 at a low speed to reduce the power consumption of the CPU 101.

FIG. 2 shows the flow of a series of processes for switching the CPU clock.

The key sense routine is modified in advance as follows. That is, in addition to the processing that should be originally performed by the key sense routine, the processing of writing data indicating that the key sense routine has been called into the information holding circuit 106 and the processing of the key sense routine are completed. The process of writing the data indicating the above into the information holding circuit 106 is added. In this embodiment, these key sense
The processing program added to the routine serves as the key input processing state determination means.

When the application program requests a key input process, the key sense routine is called (process 201). Then, since the key sense routine has been changed as described above, data indicating that the key sense routine has been called is written in the information holding circuit 106 (process 202). As a result, the control circuit 1
07 sends a signal to the clock switching circuit 108 to lower the clock frequency. Upon receiving this signal, the clock switching circuit 108 sets the low clock 111 to the CPU 101.
Supply to.

When the writing to the information holding circuit 106 is completed, the original key sense routine is executed (process 203). During this period, the CPU 101 continues to be supplied with the low clock 111. Then, when the processing of the key sense routine is completed, data indicating that the key sense routine is completed is written in the information holding circuit 106 this time (processing 204). As a result, the control circuit 1
07 sends a signal for increasing the clock frequency to the clock switching circuit 108. Upon receiving this signal, the clock switching circuit 108 sends the high clock 110 to the CPU 101.
Supply to.

As described above, the CPU clock frequency can be kept low while the application program executes the key input process, that is, the key sense routine.

By the way, in the above-described embodiment, the key sense routine is changed by adding a program serving as a key input processing state determining means, but the key sense routine is not changed and the key input processing state determining means is not changed. It is also feasible to store the above program in the RAM 103. The flow of processing in this case will be described below with reference to FIG.

When the application program calls the key sense routine, the RAM 103 in which the address where the key sense routine is stored is written is referred to.
This causes the process to jump to the key sense routine. In the processing shown in FIG. 2, the processing shifts from the application program to the key sense routine to which the program of the key input processing state determining means is added in this way. On the other hand, in the processing shown in FIG. 3, the address written in the RAM 103 is not the address of the key sense routine, but the RA of the program of the key input processing state determination means is stored.
Rewrite to the address of M103. Then, when the application program calls the key sense routine (process 301), the process moves to the program of the key input process state determination means. Then, the program of the key input processing state determination means is executed, and the information holding circuit 106 receives the key sense.
Data indicating that the routine has been called is written (process 302). Then, the key sense routine is called from the program of the key input processing state discrimination means and executed (process 303). At this time, the CPU 101 is supplied with the low clock 111 during execution of the key sense routine as in the case of the processing shown in FIG. When the key sense routine is completed, the process returns to the program of the key input processing state determining means, and the data indicating that the key sense routine is completed is written in the information holding circuit 106 (process 304). As a result, the CPU 101 is supplied with the high clock 110.
Then, the processing shifts to the application program.

Even in the above-described manner, the CPU clock can be kept lowered during the key input processing as in the processing shown in FIG.

On the other hand, in the embodiment shown in FIG. 1, the information holding circuit 106, the control means 107 and the clock switching circuit 10 are provided.
Although 8 are individually provided, they can be realized by integrating them in one LSI. Further, as the clock to be supplied to the CPU 101, either one of the high clock 110 and the low clock 111 is supplied by the clock switching circuit 108. However, if a clock generation circuit is added to the clock switching circuit 108, one clock oscillator is provided. Thus, a high clock and a low clock can be supplied from a single clock. As a result, the number of parts required to realize the present invention can be reduced.

Further, the power consumption of the CPU is further reduced by combining the present invention with the power-saving method as shown in the above-mentioned publication, that is, the method of lowering the clock frequency of the CPU when the key is not hit for a certain time. It is also possible to reduce.

[0024]

According to the present invention, the CP is processed during key input processing.
Since the clock frequency of U can be lowered, it is possible to reduce the power consumption of the CPU without deteriorating the apparent processing performance of the information processing apparatus seen by the user.
As a result, the power consumed by the information processing device can be reduced, so that the time during which the information processing device can be driven by the battery is extended and the usability can be improved.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of the present invention.

FIG. 2 is a diagram showing a flow of processing when a key input processing state determination means is provided in a key sense routine.

FIG. 3 is a diagram showing a flow of processing when a key input processing state determination means is provided in the RAM.

[Explanation of symbols]

 101 ... CPU, 102 ... ROM, 106 ... Information holding circuit, 107 ... Control circuit, 108 ... Clock switching circuit.

Claims (2)

[Claims] 1. An information processing apparatus having a CPU clock switching means, a key input processing state determining means for determining whether or not a key sense routine called by an application program is being executed, and the key input. A control means is provided for sending a switching signal to the clock switching means of the CPU according to the judgment of the processing state judging means, and the clock frequency of the CPU is kept low during execution of the key sense routine, except for the key sense routine. A power saving method for the CPU, which is characterized in that the frequency of the CPU is increased when executing the processing of. 2. An information processing apparatus according to claim 1, further comprising: an information holding circuit which is connected to a bus for address, data and command signals of the CPU and holds a discrimination result of the key input state discrimination means; An information processing apparatus, comprising: a control circuit that sends a switching signal to the clock switching means according to the contents of the circuit.