JPH07219771A - Instruction processor - Google Patents

Abstract

(57) [Summary] [Purpose] When the execution result of a certain instruction is determined by the execution result of the previous instruction, the instruction is executed assuming the execution result of the previous instruction for the sake of speedup. If there is an error in the execution result of the instruction, the penalty of the process of correcting the error of the subsequent instruction due to the error is reduced. [Structure] The instruction 1a determined by the execution result of the previous instruction 0b is determined, the copy instruction 1a 'of the instruction is created, the instruction 1a is executed based on the operation result of the previous instruction 0b, and the previous data in the register is used. Executes the operation of copy instruction 1a '. afterwards,
When the instruction 0b is not invalidated, the writing of the operation result of the copy instruction 1a 'is suppressed, and when the instruction 0b is invalidated, the operation result of the copy instruction 1a' is validated, and the operation result of the instruction 1a is enabled. Invalidate. As a result, in an instruction whose execution is determined by the execution result of the previous instruction, even if an error occurs in the execution result of the previous instruction, it can be processed with a small penalty and the performance of the processor can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor for executing a next instruction by assuming the execution result of the previous instruction without waiting for the execution result when parallel processing a plurality of pipelined instructions. , An instruction processor suitable for reducing the time until the re-execution of the next instruction is executed when the assumed value differs from the execution result of the previous instruction.

[0002]

2. Description of the Related Art As a means for improving the performance of a high-performance information processing apparatus such as a RISC processor, a pipeline technology for executing instruction processing stepwise and a superscalar technology for processing a plurality of instructions in parallel in one processor It has been known.

The pipeline technique requires a process of fetching an instruction from a memory, a process of decoding an instruction, a process of calculating data, a process of writing a register, etc. in order to execute one instruction. Therefore, this is a technique of dividing one instruction into a plurality of stages and executing each stage individually to execute the instruction stepwise. With this pipeline technique, the execution of the next instruction can be started during the execution of one instruction, and the efficient execution of the instruction becomes possible.

The superscalar technology is a technology that enables a plurality of instructions to be executed simultaneously. In order to realize this, it is necessary to have a plurality of arithmetic units, for example.

When using the pipeline technique, the execution result of a certain instruction may be determined by the execution result of the previous instruction. In order to perform the processing in such a case at high speed, a method of assuming the execution result of the previous instruction and executing the instruction is often used. However, if there is an error in the execution result of the assumed previous instruction, an error will also occur in the instruction using the result, and a penalty for processing the error will occur.

When the operation result of one instruction is required by the next instruction, in order to process the operation result without stopping the pipeline, the operation result of the first instruction can be sent to the next instruction before being written to the register. Often done. This is called short pass or forwarding.

If the first instruction becomes invalid due to the flow of the program after performing the short pass, it means that the next instruction also uses the invalidated data, and it is necessary to redo it. Here, the invalidation of an instruction is called “narify”, and the redoing of another instruction due to the nullify is called “retry”. In order to perform the retry, it is necessary to suspend all the instructions being executed by the pipeline and re-execute the short-passed instructions from the beginning. As a result, there is a penalty that no instruction can be executed for several clock cycles.

FIG. 8 is a block diagram of a conventional processor. 100 is a main memory, 102 is an instruction cache, 104
Is an instruction issuing unit, and 106 is an instruction processing unit. The instruction processing unit 106 uses the address signal 191 to cause the instruction cache 102 to read the corresponding instruction,
The read instruction is sent to the instruction issuing unit 104 through the buses 103a to 103d. Instruction issuing unit 104
Selects an instruction that can be processed in parallel from the received instructions and sends it to the instruction processing unit 106 through the buses 105a to 105d. The instruction processing unit 106 calculates the instruction, further determines the short pass and the nullify, and retries by the instruction address signal 191.

Incidentally, one related to the prior art is disclosed in Japanese Patent Laid-Open No. 61-107435. However, this conventional technique only processes the instruction that depends on the preceding instruction by prediction, writes the result to the memory only when the prediction is determined to be correct, and does not retry when the prediction is incorrect. .

[0010]

FIG. 9 is a diagram showing a penalty cycle resulting from a retry in the conventional processor shown in FIG. In the example of this figure, four instructions a, b, c, d are processed in parallel. In the example of FIG. 9, the number of pipeline stages is 6, and the operation is performed in the E stage. The operation result of the instruction b at this E stage is
A short pass 143 is given to the next command a. But next F
When the verify signal 153 which invalidates the instruction b is issued at the stage, the instruction b does not store the operation result in the register at the W stage and issues the signal 191 for retrying the next instruction a. As is clear from this figure, the short path signal 143, the nullify signal 153,
Each signal 191 for fetching the instruction address again requires one cycle, and if a retry occurs, a penalty of four cycles occurs.

An object of the present invention is to provide an instruction processor capable of reducing the above-mentioned penalty when the execution result of a certain instruction is determined by the execution result of the previous instruction.

[0012]

SUMMARY OF THE INVENTION In the instruction processor for repeatedly pipeline processing a plurality of instructions in parallel, a data holding means for holding an operation result of an instruction at the final stage of pipeline processing and an instruction An instruction copying means for receiving a short path as a result of execution of an instruction and executing the instruction, and copying the instruction in which the previous instruction may be nullified into two identical first and second instructions; Instruction processing means for executing the first instruction based on the data by the short path and executing the second instruction based on the data stored in the data holding means; and the second instruction if the previous instruction is nullified. The operation result of the instruction is held in the data holding means, and when the previous instruction is not nullified, the operation result of the first instruction is held in the data holding means. By providing a deterrent for data writing to be accomplished.

[0013]

[Operation] First executed by receiving a short path from the previous instruction
If the operation result of the instruction becomes invalid due to the narify of the previous instruction, the operation result of the second instruction executed in parallel with the first instruction or immediately after the first instruction is validated, and the penalty is increased. Decrease. That is, the operation result of the second instruction can be directly obtained, as compared with the case where the necessary data is passed to the second instruction and executed after it is determined that the execution result of the first instruction is invalid. Either the execution of the first instruction or the execution of the second instruction is a wasteful execution, but the penalty to be reduced is a much better benefit as an instruction processor than the disadvantage due to the waste.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 1 is a block diagram of an instruction processor according to a first embodiment of the present invention. 10 is a means for holding an instruction, 20 is a means for judging copying, 30 is a means for copying an instruction, 40
Is a means for processing instructions in parallel, 50 is means for suppressing writing of erroneous operations, and 60 is means for holding data.

Each instruction read from the instruction holding means 10 is copied 20 through the signal line 11 to determine copying.
Sent to. The means 20 for judging the copy has two functions: (a) whether or not the instruction requires the execution result of the preceding instruction, and (b) whether or not the preceding instruction is likely to be qualified by the flow of the program. Depending on the conditions, it is determined whether or not copying should be performed.
If the instruction requires the execution result of the previous instruction and there is a possibility that it will be nullified, it is determined that the instruction should be copied, and the instruction copying means 30 makes the instruction two identical instructions. The signals are sent to the means 40 for processing through the signal lines 31 and 32.

The means 40 for processing instructions executes the two copied instructions by receiving necessary data from the means 60 for holding data. That is, one instruction receives and processes the result of the previous instruction through the short path, and the other instruction does not receive data through the short path, but stores the data stored in the register that stores the execution result of the previous previous instruction. Use and process. The result of each processing is the signal line 43,
It is sent via 44 to the means 60 for holding the data. The means 50 for suppressing the writing of the erroneous calculation includes the signal lines 41, 4
The processing result is obtained from the means 40 for processing the instruction through 2. At this time, if a narify occurs, the processing result of the instruction processed by the data by the short path is invalidated (writing of the processing result to the means 60 is suppressed).
A control signal is issued which suppresses writing to the means 60 for holding data through the signal line 51. Further, when the narify is not performed, the processing result of the instruction processed by the data not based on the short path is invalidated.

If the means 20 for determining copying does not require copying of the instruction, no copying is performed and the instruction is sent through the signal line 31 to the means 40 for processing the instruction and the processed result is , Is written in the means 60 for holding data through the signal line 43.

FIG. 2 is a block diagram of an instruction processor according to the second embodiment of the present invention. Reference numeral 100 is a main memory, 110 is an instruction cache (corresponding to the means 10 for holding the instruction in FIG. 1), 115 is a prediction bit generating unit, 120 is an instruction issuing unit (corresponding to the means 20 for judging copying in FIG. 1), 125 Is a selector unit (corresponding to the means 30 for copying the instruction of FIG. 1), 130 is a decoding unit, 14
0 is an arithmetic unit including an integer, a floating point, etc. (corresponding to the means 40 for processing the instruction in FIG. 1), 150 is a nullify generating unit, 160 is a short path control unit, 17
Reference numeral 0 is an instruction invalidation unit (corresponding to the means 50 for suppressing erroneous operation writing in FIG. 1), 180 is a register (means 60 for holding data in FIG. 1), and 190 is an instruction address generation unit. The instruction cache 110 holds the miscalculation prediction bit 112. In this embodiment, it is possible to process up to four instructions in parallel.

The instruction cache 110 outputs the corresponding instruction to the instruction issuing unit 120 through the bus 111 based on the instruction address signal 191. At this time, if necessary, the corresponding instruction is read from the main memory 100 through the bus 101 and output to the instruction issuing unit 120. The instruction output to the instruction issuing unit 120 has a prediction bit 112.
(Indicating an instruction to be copied under the conditions (a) and (b) above) is added.

The instruction issuing unit 120 sends an instruction selection signal 122 to the selector unit 125, copies the instruction in which the miscalculation prediction bit 112 is set, and issues the two instructions to the decoding unit 130 at the same time. The decode unit 130 decodes the instruction and outputs the operation control signal 13
3 to the arithmetic unit 140, a control signal 131 indicating that copying has occurred to the instruction invalidating unit 170, and a control signal 132 indicating that there is a possibility that narify will occur.
Is sent to the Nalify generation unit 150 and a control signal 134 indicating that a short path is generated is sent to the short path control unit 160.

If the miscalculation prediction bit 112 is set, copying is performed, and if a short pass instruction is made due to prediction and the instruction is invalidated, the instruction invalidation unit 170 causes the short pass control unit 160 to perform the short pass. The instruction to be invalidated is determined from the three signals, the generation signal 161, the nullification generation signal 151 from the nullification generation unit 150, and the copy generation signal 131 from the decoding unit 130, and the instruction invalidation signal 171 executes the instruction. The writing of the result to the register 180 is suppressed. The Nalify generation signal 151 is generated by the Nalify generation unit 150 from the control signal 132 indicating that Nalify may occur and the calculation result 141 of the calculation unit 140.

If the miscalculation prediction bit 112 is not set, the instruction to be nullified is not copied, and if the short-passing instruction is nullified, the retry processing is performed as in the conventional example, and then the instruction is executed. "1" is written in the miscalculation prediction bit 112 so that the prediction can be performed when executing. In the retry operation, the retry address is generated by the instruction address generation unit 190 using the nullify generation signal 151 from the nullify generation unit 150 and the short path generation signal 161 from the short path control unit 160, and the instruction address signal 191 is stored in the instruction cache. It is realized by sending the retry address through. In order to write “1” to the miscalculation prediction bit 112, the short path control unit 160 and the nullify generation unit 150 send the short path and nullify generation signals 161 and 151 to the prediction bit generation unit 115, and the prediction bit generation unit 115 Create the predicted bit signal 116 and send it to the instruction cache 110.

If it is predicted that an instruction that short-passes will be nullified because the miscalculation prediction bit 112 is set, if the prediction is incorrect and the short-passed instruction is not nullified, the short-path control unit 160 is called. The Nalify generation unit 150 sends signals 161, 151 to the prediction bit generation unit 115, and the prediction bit generation unit 115 outputs the miscalculated prediction bit signal 1
16 is sent to the instruction cache 110, and the miscalculation prediction bit 112 of the instruction predicted to be miscalculated is set to "0".

FIG. 3 is a block diagram of the selector unit 125 of FIG. Reference numerals 121a to 121d are instructions issued by the instruction issuing unit 120, 122 is an instruction selection signal output from the instruction issuing unit 120, and 126 is an instruction copy selector. The instructions 121a to 121d include the miscalculation prediction bit 112. If instructions 121a-121d
If none of the miscalculation prediction bits 112 of
Normal processing occurs, no copying of instructions. If the miscalculation prediction bit 112 of any of the instructions 121b, 121c, 121d is set, the instruction issuing unit 120
Issues earlier instructions first and shifts later instructions. Therefore, in the next cycle, the miscalculation prediction bit 112 of the instruction 121a is set. If the miscalculation bit 112 of the instruction 121a is set, the instruction issuing unit 120 outputs the instruction selection signal 122 to the instruction copy selector 126.
Control the selector 126 by sending
Copy 1a. In this case, the instructions 121b, 121c,
121d is issued in the next cycle.

FIG. 4 is a pipeline explanatory diagram showing the operation of the embodiment described with reference to FIGS. At the IFA stage, the instruction goes to the instruction cache. In the IFB stage, copy determination is performed and the instruction is transferred from the instruction issue unit to the decode unit. The D stage decodes the instruction. At the E stage, data calculation and the like are performed. In the F stage, a nullify signal is created as needed. Register writing is performed in the W stage. Reference numeral 143 is a short path signal, and 153 is a timing of a nullify signal.

At the IFA stage, four instructions at consecutive addresses such as 0a, 0b, 0c, 0d are fetched to the instruction cache, and at the IFB stage, the four instructions are moved to the instruction issue unit, and the erroneous operation prediction bit is set. Judge whether there is
Control the issuing of instructions. In the example of FIG. 4, since the miscalculation prediction bit 112 of the instruction 1a is set, the instruction 1a is copied,
Make a copy command 1a '. In this example, E stage instruction 0b
Occurs the short path 143 of the D stage instruction 1a. And in the D stage, the short-passed instruction
1a and the copy instruction 1a 'which has not been short-passed are decoded. The instruction 1a performs an operation based on the short-passed data in the E stage, and the copy instruction 1a 'performs an operation in the E stage using the previous data stored in the register.

Here, the instruction 0b is the nullify signal 153.
When the N-stage is verified by the F stage, the operation result of the instruction 1a is prevented from being written in the register 180 in the W stage. If the prediction is wrong, the narify signal 15
If 3 does not occur, the operation result of the copy instruction 1a 'is prevented from being written in the register. Therefore, in this embodiment, the penalty is 0 cycle.

FIG. 5 is an explanatory diagram of the pipeline when the erroneous operation prediction bit 112 is set in the instruction 1c which is executed by using the operation result of the instruction 0b. Command 1c is command 121 in FIG.
Corresponds to c. The instruction issuing unit 120 has an issue position 1
Since the instruction with the miscalculation prediction bit set to 21a must be issued, the instruction 1a and the instruction 1b before the instruction 1c are issued.
Is issued first. In the next cycle, the prediction bit 112
The instruction 1c in which is set is copied, and the instruction 1c and the copy instruction 1c 'are simultaneously executed in parallel. Other operations are the same as in the case of FIG. 4, and in this example, the penalty is 0 cycle.

FIG. 6 is a block diagram of another embodiment of the selector unit 125 of FIG. In the configuration of FIG. 3, the selector 121a and the instruction 121b are input, whereas in the configuration of FIG. 6, the instruction 121a and the selector 127 are input.
The difference is that it uses its own output as input. In this embodiment, with such a configuration, the copy instruction is executed with a delay of one cycle from the original instruction, but the penalty is reduced as will be described with reference to FIG. .

FIG. 7 is an explanatory diagram of the pipeline in the embodiment using the configuration of FIG. In the D stage, the instruction 1a to be short-passed is first executed, and in the next cycle, the same instruction is executed as the state 1a 'which is not short-passed.
In the example shown in FIG. 7, the short-passed instruction is nullified, so that the writing of the instruction 1a into the register is suppressed. If no narify occurs, the next copy instruction 1
Suppress register writing of a '. Since the copy instruction 1a 'is executed in the next cycle, the penalty is 1 cycle when the register writing of the instruction 1a is suppressed, and the penalty is 0 cycle when the register writing of the instruction 1a' is suppressed.

The present invention is not limited to the above-described embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

[0032]

According to the present invention, the following effects can be obtained. (1) In an instruction whose execution result is determined by the execution result of the previous instruction, even if an error occurs in the execution result of the previous instruction, it can be processed with a small penalty. (2) The performance of the processor can be improved through the above processing.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an instruction processor according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of an instruction processor according to a second embodiment of the present invention.

FIG. 3 is a configuration diagram of a selector unit shown in FIG.

FIG. 4 is a diagram illustrating pipeline processing of the instruction processor shown in FIG.

FIG. 5 is a diagram illustrating another pipeline process of the instruction processor shown in FIG.

FIG. 6 is a configuration diagram of another embodiment of the selector unit shown in FIG.

7 is a diagram illustrating pipeline processing of an instruction processor using the selector unit of FIG.

FIG. 8 is a configuration diagram of a conventional instruction processor.

9 is a diagram illustrating pipeline processing of the instruction processor of FIG.

[Explanation of symbols]

10 ... Means for holding instruction, 20 ... Means for judging copy, 30 ... Means for copying instruction, 40 ... Means for processing instruction, 50 ... Means for suppressing writing of erroneous operation, 60 ...
Means for holding data, 100 ... Main memory, 110 ... Instruction cache including miscalculation prediction bits, 112 ... Miscalculation prediction bits, 115 ... Prediction bit generation unit, 120 ...
Instruction issuing unit 122 ... Instruction selection signal 125 ... Selector unit 126 ... Instruction copy selector 130 ...
Decoding unit, 140 ... Arithmetic unit, 143 ... Short path signal, 150 ... Nalify generation unit, 1
53 ... Nalify signal, 160 ... Short path control unit, 170 ... Instruction invalidation unit, 180 ... Register, 190 ... Instruction address generation unit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takashi Hotta 7-1, 1-1 Omika-cho, Hitachi-shi, Ibaraki Hitachi Ltd. Hitachi Research Laboratory

Claims (13)

[Claims] 1. An instruction processor including an instruction holding unit, an instruction processing unit, and a data holding unit, which is provided with a copy determining unit, an instruction copying unit, and an erroneous operation write inhibiting unit, and is taken out from the instruction holding unit. For each instruction, the copy determining means determines whether or not it should be copied. If it is determined that the instruction should be copied, the instruction copying means sets the corresponding instructions to the same two instructions, and the instruction processing means. According to the above, the same two instructions are processed in parallel by using different operation data, and the incorrect operation write inhibiting means prevents the incorrect operation result of the operation results of the two instructions from being written in the data holding means. An instruction processor characterized in that the other operation result is written in the data holding means. 2. An instruction processor comprising an instruction holding means, an instruction processing means, and a data holding means, which is provided with a copy judging means, an instruction copying means, and an erroneous operation write inhibiting means, and is taken out from the instruction holding means. For each instruction, the copy determining means determines whether or not it should be copied. If it is determined that the instruction should be copied, the instruction copying means sets the corresponding instructions to the same two instructions, and the instruction processing means. By the above, the same two instructions are sequentially processed by using different operation data, and the erroneous operation write inhibiting means prevents the erroneous operation result of the operation results of the two instructions from being written in the data holding means. An instruction processor characterized in that the other operation result is written in the data holding means. 3. The instruction holding means according to claim 1 or 2, wherein an erroneous operation prediction bit is provided, and the copy determining means determines whether or not copying should be performed based on the value of the erroneous operation prediction bit. An instruction processor characterized by being configured to perform. 4. The copy determination means according to claim 1 or 2, wherein the copy determination means copies the instruction when the instruction requires the execution result of the previous instruction and the previous instruction may be narrified by the flow of the program. An instruction processor characterized by being a thing. 5. The method according to claim 4, wherein the first instruction of one of the two duplicated instructions is executed by using the data short-passed from the previous instruction, and the second instruction of the other is executed by the previous instruction processing. Execution processing is performed using the data stored in the data holding means, and when the previous instruction is nullified, the execution processing result of the first instruction is invalidated and the execution processing result of the second instruction is stored in the data holding means. An instruction processor having a configuration. 6. The method according to claim 4, wherein one of the duplicated two instructions is executed by using the data short-passed from the previous instruction and the other second instruction is executed by the previous instruction processing. Execution processing is performed using the data stored in the data holding means, and when the previous instruction is not nullified, the execution processing result of the second instruction is invalidated and the execution processing result of the first instruction is stored in the data holding means. An instruction processor characterized by having a configuration. 7. The instruction according to claim 1, wherein when a plurality of instructions are pipeline processed in parallel, a certain instruction is copied to process two identical instructions in parallel. An instruction processor characterized in that, of the instructions to be copied, an instruction whose pipeline processing is in a preceding stage is executed first and the copying is performed in the next cycle. 8. An instruction processor for repeatedly pipeline processing a plurality of instructions in parallel, and data holding means for holding an operation result of an instruction at the final stage of pipeline processing,
An instruction copying means for copying an instruction that is executed by receiving a short path of an execution result of the previous instruction and that the previous instruction may be nullified into two identical first and second instructions And an instruction processing means for executing the first instruction based on the data by the short path and an instruction processing means for executing the second instruction based on the data stored in the data holding means, and when the previous instruction is nullified. Data write inhibiting means is provided for holding the operation result of the second instruction in the data holding means and holding the operation result of the first instruction in the data holding means when the previous instruction is not nullified. An instruction processor characterized in that. 9. The instruction processor according to claim 8, wherein the instruction processing means executes the first instruction and the second instruction in parallel. 10. The instruction processor according to claim 8, wherein the instruction processing means sequentially and sequentially executes the first instruction and the second instruction. 11. The structure according to claim 8, wherein among the plurality of instructions, an instruction whose pipeline processing is in a preceding stage of the copy target instruction is executed first, and then the copy target instruction is executed. An instruction processor characterized in that. 12. The method according to claim 8, wherein the instruction is executed by receiving a short path of an execution result of the previous instruction, and whether the previous instruction is likely to be nullified. An instruction processor characterized in that an erroneous operation prediction bit for determining is added to an instruction. 13. The erroneous operation prediction bit in each instruction is rewritten based on a short path and a narify state in the process of repeatedly pipeline processing a plurality of instructions in parallel according to claim 12, and the copy of the instruction in the next cycle is performed. An instruction processor characterized by being configured to make a determination.