JPH07221274A - Compound semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] [Object] To provide a highly reliable compound semiconductor device and a manufacturing method thereof. [Constitution] In this compound semiconductor device, HBT is provided in a first region RE1 and HE is provided in a second region RE2 on a semiconductor substrate 10.
MT is formed. The HBT includes a buffer layer 20, a collector layer 30 a, a base layer 40 on the semiconductor substrate 10.
1. Emitter layer 50a and emitter contact layer 60
It is configured by sequentially stacking c. A part of the collector layer 30a is slightly removed in the thickness direction to expose the inner surface of the collector layer 30a. And
A collector electrode 70 is formed on the exposed surface of the collector layer 30a.
However, the base electrode 90 is formed on the exposed surface of the base layer 401, and the emitter electrode 80 is formed on the emitter contact layer 60c while maintaining ohmic contact. HEMT is
The buffer layer 20 is formed as a common layer with the HBT, and the first electron supply layer 30b, the channel layer 40b, and the second electron supply layer 50b are sequentially stacked on the buffer layer 20.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a hetero bipolar transistor (HBT) and a high electron mobility transistor (HEM).
T) and a compound semiconductor device formed on the same substrate and a method for manufacturing the same.

[0002]

2. Description of the Related Art Hetero Bipolar Transistor (HB
T) is a device that consumes a large amount of power but has an excellent current driving capability, while a high electron mobility transistor (HEM)
It is known that T) is a device that has a small current driving capability but consumes less power. So, these HBT
Attempts have been made to realize a large-scale integrated circuit capable of operating at high speed with low power consumption by forming the HEMT and the HEMT on the same substrate. As a device that has been integrated in this way, "Keijiro Itakura et al., IEICE Journal E
D89-76 PP. 83 ”. This device is a GaAs / GaAlAs-based HB
By forming T and HEMT monolithically,
This is a logic gate with low power consumption, high speed, and high load driving force.

The basic structure of this logic gate is that an npnHBT is formed on a contact layer and a HEMT having an electron supply layer is formed under the same contact layer as the npnHBT.

[0004]

However, in the basic configuration of this logic gate, the step difference between the HBT and the HEMT is large, and the step coverage when forming a wiring or an insulating film (passivation film) between these devices is large. It may worsen and lead to wire breakage. Moreover, since the HBT is formed on the HEMT region containing GaAlAs in the structure of the logic gate of the same document, the GaA forming the HBT is formed.
There is a problem in that the crystallinity of the s layer and the like is poor, the recombination current in the base increases, and the operating characteristics deteriorate.

Further, in the manufacturing method in which the epitaxial layer on the HEMT region is removed by using selective etching as in the same document, AlInAs / InGaAs system etching cannot be performed well, and the HEMT characteristics are changed due to etching variations. There was a problem of variation.

The present invention has been made in view of such a problem, and there is no fear of disconnection during the formation of wiring, and the HEMT characteristics are not deteriorated even when the combination of selective etching is bad. And a method for manufacturing the same.

[0007]

In order to solve such a problem, the present invention provides an npn hetero bipolar transistor (HBT) and a second npn hetero bipolar transistor (HBT) formed in the first region on the same substrate.
Electron mobility transistor (HEM
(A) npn hetero-bipolar transistor, wherein the first n-type compound semiconductor layer formed in the first region on the substrate and the first n-type compound semiconductor layer. A p-type compound semiconductor layer formed on the p-type compound semiconductor layer and a second n-type compound semiconductor layer formed on the p-type compound semiconductor layer.
At least one of the type compound semiconductor layers has an energy bandgap wider than that of the p type compound semiconductor layer, and the high electron mobility transistor (B) has a thickness substantially equal to that of the first n type compound semiconductor layer. Then, a third n-type compound semiconductor layer formed in the second region on the substrate, a compound semiconductor channel layer formed on the third n-type compound semiconductor layer, and a compound semiconductor channel layer formed on the compound semiconductor channel layer. And a fourth n-type compound semiconductor layer that has been formed, and the third n-type compound semiconductor layer or the fourth n-type compound semiconductor layer has a wider energy band gap than the compound semiconductor channel layer and supplies electrons. It is characterized by forming a layer.

Then, such a compound semiconductor device is
It can be obtained by forming HBT and HEMT on the same substrate having low electric conductivity. That is, in the method for manufacturing a compound semiconductor device according to the present invention, when the HBT has an emitter-up structure, the first n-type compound semiconductor to be the collector layer of the hetero-bipolar transistor in the first region on the substrate. A first step of forming a common layer on a common region including first and second regions on the substrate;
A second step of forming an undoped compound semiconductor common layer to be a compound semiconductor channel layer of the high electron mobility transistor in the second region in the common region on the first n-type compound semiconductor common layer; and an undoped compound semiconductor A third step of forming a base layer of a hetero-bipolar transistor by implanting ions serving as p-type impurities into a predetermined region in the first region on the common layer, and an energy bandgap that is larger than that of the undoped compound semiconductor common layer. Wide and first
The second n-type compound semiconductor common layer, which is to be the emitter layer of the hetero-bipolar transistor in the region of 1) and the electron supply layer of the high electron mobility transistor in the second region, is formed in the common region on the undoped compound semiconductor common layer. A fourth step of forming and a fifth step of electrically separating the first region and the second region by performing mesa etching or ion implantation from the second n-type compound semiconductor common layer toward the substrate And a process.

Further, the HB of such a compound semiconductor device
When T has a collector-up structure, the method for manufacturing a compound semiconductor device according to the present invention provides an emitter layer of a hetero-bipolar transistor in the first region on the substrate,
A first step of forming a second n-type compound semiconductor common layer to be an electron supply layer of the high electron mobility transistor in the second region in a common region including the first and second regions on the substrate; , An energy bandgap narrower than that of the second n-type compound semiconductor common layer, and an undoped compound semiconductor common layer to be a compound semiconductor channel layer of the high electron mobility transistor in the second region, A second step of forming a common region on the type compound semiconductor common layer, and a base layer of the hetero-bipolar transistor by implanting ions as p-type impurities into a predetermined region in the first region on the undoped compound semiconductor layer. And a first n-type compound semiconductor common layer to be a collector layer of the hetero-bipolar transistor in the first region is undoped. The fourth step of forming the common region on the compound semiconductor common layer, and the mesa etching or ion implantation from the first n-type compound semiconductor common layer toward the substrate to perform the first region and the second region. And a fifth step of electrically isolating the region.

[0010]

The compound semiconductor device of the present invention has n
A pn hetero bipolar transistor (HBT) and a high electron mobility transistor (HEMT) are formed. Then, the first n-type compound semiconductor layer of this HBT,
The p-type compound semiconductor layer and the second n-type compound semiconductor layer respectively function as an emitter, a base and a collector of the HBT, or a collector, a base and an emitter. Since the HBT has an energy bandgap of the first n-type compound semiconductor layer or the second n-type compound semiconductor layer that is wider than that of the p-type compound semiconductor layer, the HBT has a potential barrier between the emitter and the base, so that the emitter injection efficiency is high. Can be increased to perform high-speed, high-gain operation.

The HEMT has a compound semiconductor channel layer and an electron supply layer composed of a third or fourth n-type compound semiconductor layer, and propagates a two-dimensional electron gas generated at the interface between them at high speed. It can be driven with low power consumption.

Since the third n-type compound semiconductor layer of the HEMT has substantially the same thickness as the first n-type compound semiconductor layer of the HBT, it serves as the compound semiconductor channel layer of the HEMT and the base of the HBT. What is a p-type compound semiconductor layer?
It is formed so as to be separated from the substrate by the same distance.
Therefore, when these HEMTs and HBTs are provided with wirings and electrically coupled to each other to realize a logic circuit, these steps have a small step and good step coverage can be maintained.

When the second n-type compound semiconductor layer is used as the collector layer of the hetero bipolar transistor, the emitter concentration can be reduced to reduce the emitter junction capacitance and the collector area. It is possible to reduce the collector junction capacitance and increase the cutoff frequency of the HBT.

If the substrate includes a compound semiconductor buffer layer formed on the compound substrate, the crystallinity of the layer formed on this layer can be maintained well. In addition, this substrate is allowed to include a collector buried layer used in a bipolar transistor,
In addition, the compound semiconductor layers composed of the above HBT and HEMT may each include a graded region in which the composition of the constituent material is changed for lattice matching.

Further, if both the third n-type compound semiconductor layer and the fourth n-type compound semiconductor layer have an energy band gap wider than that of the compound semiconductor channel layer, the electron supply layer is formed. , A two-dimensional electron gas is supplied between the compound semiconductor channel layer and the two n-type electron supply layers.
Since it can be generated at the interface, the current density of the HEMT can be increased.

According to such a method of manufacturing a compound semiconductor device, when the HBT has an emitter-up structure, first, a film forming technique such as MBE method or MOVPE method is applied in the first step. A first n-type compound semiconductor common layer to be used as a collector layer of the hetero-bipolar transistor in the first region on the substrate is formed in the common region including the first and second regions on the substrate, and subsequently, By the second step, an undoped compound semiconductor common layer to be the compound semiconductor channel layer of the high electron mobility transistor in the second region is formed in the common region on the first n-type compound semiconductor common layer.

Then, in the third step, ions serving as p-type impurities are implanted into a predetermined region in the first region on the undoped compound semiconductor common layer to form a base layer of the hetero-bipolar transistor. In the second step, the energy bandgap is wider than that of the undoped compound semiconductor common layer, and it becomes the emitter layer of the hetero-bipolar transistor in the first region and the electron supply layer of the high electron mobility transistor in the second region. The n-type compound semiconductor common layer is formed in the common region on the undoped compound semiconductor common layer.

Finally, in the fifth step, the first region and the second region are electrically separated by performing mesa etching or ion implantation from the second n-type compound semiconductor common layer toward the substrate. As a result, the compound semiconductor device can be manufactured.

Further, the HB of such a compound semiconductor device
When T has a collector-up structure, first, in the first step, it becomes the emitter layer of the hetero-bipolar transistor in the first region on the substrate, and the electron supply layer of the high electron mobility transistor in the second region. A second n-type compound semiconductor common layer to be formed is formed in the common region including the first and second regions on the substrate.

In the second step, the energy bandgap is narrower than that of the second n-type compound semiconductor common layer, and the undoped compound to be the compound semiconductor channel layer of the high electron mobility transistor in the second region. The semiconductor common layer is formed in the common region on the second n-type compound semiconductor common layer.

Next, in the third step, ions serving as p-type impurities are implanted into a predetermined region in the first region on the undoped compound semiconductor layer to form a base layer of the hetero-bipolar transistor. By the process, a first n-type compound semiconductor common layer to be a collector layer of the hetero bipolar transistor in the first region is formed in the common region on the undoped compound semiconductor common layer.

Finally, in the fifth step, mesa etching or ion implantation is performed from the first n-type compound semiconductor common layer toward the substrate to electrically separate the first region and the second region. As a result, the compound semiconductor device according to the present invention can be manufactured.

[0023]

The compound semiconductor device according to the present invention will be described below with reference to the accompanying drawings. The same elements will be denoted by the same reference symbols, without redundant description.

First, the structure of the compound semiconductor device according to the first embodiment of the present invention will be described. FIG. 1 is a sectional configuration diagram for explaining the structure of the compound semiconductor device according to the first example. This compound semiconductor device has HBT in the first region RE1 and H in the second region RE2 on the semiconductor substrate 10.
The EMT is formed. The HBT is a buffer layer 20 having a thickness of 5000 angstroms formed on the semiconductor substrate 10.
1000 Å thick carrier concentration 1 × 10
¹⁸ / cm ³ collector layer 30a, base layer 40 having a thickness of 150 Å and an impurity concentration of 1 × 10 ²¹ / cm ^3.
1. Thickness 1000 angstrom and carrier concentration 1x
The emitter layer 50a of 10 ¹⁸ / cm ³ and the high-concentration emitter contact layer 60c are sequentially laminated. A part of the collector layer 30a is slightly removed in the thickness direction to expose the inner surface of the collector layer 30a. A collector electrode 70 is formed on the exposed surface of the collector layer 30a while maintaining ohmic contact. Similarly, the base layer 401 is partially exposed in the same manner, and the base electrode 90 is exposed on this exposed surface.
However, the emitter electrode 8 is formed on the emitter contact layer 60c.
0 is formed while maintaining ohmic contact.

On the other hand, in HEMT, the buffer layer 20 is
As a common layer with BT, a first electron supply layer 30b having a thickness of 1000 angstroms and a carrier concentration of 1 × 10 ¹⁸ / cm ³ is formed thereon, and a channel layer having a thickness of 150 angstroms and an impurity concentration of 1 × 10 ¹⁵ / cm ³ or less. Carrier concentration of 1 × 10 ¹⁸ at 40 b and a thickness of 1000 Å.
/ Cm ³ of the second electron supply layer 50b is sequentially laminated. Then, a part of the second electron supply layer 50b is slightly removed (about 500 angstroms) in the thickness direction, and the gate electrode 110 is formed on the surface exposed by this removal while maintaining Schottky contact. . In addition, the gate electrode 1 is formed on the second electron supply layer 50b.
A source contact layer 60a and a drain contact layer 60b are formed so as to sandwich 10, and a source electrode 100 and a drain electrode 120 are formed on these, respectively, while maintaining ohmic contact.

Further, the collector electrode 70 and the source electrode 10
0 is a wiring (Ti / P) deposited through the insulating film 130.
t / Au) 140 for electrical connection. In this embodiment, for the sake of simplicity, only the collector electrode 70 and the source electrode 100 are connected, but when these are applied to a logic circuit for an integrated circuit,
It is desirable that they be appropriately connected so as to realize the logic circuit described in the above document.

Each layer is composed of the materials shown in FIG. That is, the semiconductor substrate 10 is semi-insulating GaAs, the buffer layer 20 is GaAs formed to maintain the crystallinity of the layer formed thereon, and the collector layer 30a and the channel layer 40b are n-type GaA.
s, the base layer 401 is InGaAs (In = 0.5),
The channel layer 40b is undoped (undoped: carrier concentration 1 × 10 ¹⁵ / cm ³ or less) InGaAs, and the emitter layer 50a and the second electron supply layer 50b are n-type AlG.
The aAs layer and the contact layers 60a to 60c are high-concentration n-type GaA.
s.

If it is made of such a material, the energy band gap of the emitter layer 50a becomes wider than that of the base, and an HBT can be formed. According to the structure of this embodiment, the energy band gap of the collector layer 30a is also set wider than that of the base. The electrodes 70, 80, 90, 10 holding the respective ohmic contacts
0 and 120 are made of AuGe / Ni, and the electrode 110 holding the Schottky contact is Ti / Pt.
/ Au. Moreover, since the energy band gap of the channel layer 40b is narrower than that of the second electron supply layer 50b, a HEMT can be formed. Here, in this HEMT, the energy band gap of the channel layer 40b is also set narrower than that of the first electron supply layer 30b, so that two-dimensional electrons are also generated at these interfaces to form the HEMT.

By thus forming the channel layer 40b and the base layer 401 at an equal distance from the semiconductor substrate 10, the step between HEMT and HBT (step between electrodes) can be reduced. Yes, wiring 14
The step coverage of 0 can be improved. Accordingly, it is possible to reduce the risk that the wiring 140 is disconnected due to an inconvenient factor such as the concentration of an electric field.

Next, the operation of the compound semiconductor device of this embodiment will be described. This HBT is obtained by applying a forward voltage between the emitter layer 50a and the base layer 401 and a reverse voltage between the base and the collector layer 30a.
To work as. Since the energy band gap of the emitter layer 50a is wider than that of the base layer 401, the potential barrier between them causes the base layer 40a.
The reverse injection current from 1 to the emitter layer 50a can be reduced, the emitter injection efficiency can be increased, and high-speed gain operation can be realized.

Further, this HEMT is designed to operate in the D mode, and a drive voltage is applied between the source electrode 100 and the drain electrode 120 and the gate electrode 1
By applying a negative voltage to the first electron supply layer 3,
0b and the channel layer 40b, and the two-dimensional electron gas concentration generated at the interface between the second electron supply layer 50b and the channel layer 40b is reduced to reduce the source electrode 100 and the drain electrode 120.
The amount of the two-dimensional electron gas flowing between them is controlled. In such a HEMT, since two-dimensional electrons travel without being affected by space charges, the HEMT can operate at high speed with low power consumption.

Next, a method of manufacturing this compound semiconductor device will be described with reference to FIGS. In addition, each layer contains M (Ga, As, In) as a constituent element.
It was formed by using it as a source of BE (molecular beam epitaxial) method. First, as shown in FIG. 1, the buffer layer 20, the first wide bandgap layer 30, and the narrow bandgap layer 40 are sequentially stacked on the semiconductor substrate 10 by the MBE method. The layer thickness of the narrow bandgap layer 40 is set to about 150 angstroms. This is because the crystallinity of the narrow bandgap layer 40 and the layer formed thereon is kept good. Narrow band gap layer 40
Since it functions as a layer for generating two-dimensional electron gas on the substrate side of the HEMT shown in FIG. 1, it is preferably 300 angstroms or less from the viewpoint of maintaining the electric field strength generated here.

Next, as shown in FIG. 2, a photoresist 100 is applied / exposed (patterned) on the first wide band gap layer 30 to expose the photoresist 100 in a predetermined region of the first region RE1 of FIG. Peel off. Thereafter, 1 × 10 ¹⁴ / cm ² injected into the impurity concentration of 1 × 10 ²¹ / c a Be ⁺ at 10keV by ion implantation into the predetermined area
An m ³ p-type base layer 401 is formed. C ⁺ was used as the p-type impurity and was implanted at 1 × 10 ¹⁴ / cm ^{2 at 15 to 20} keV to obtain an impurity concentration of 1 × 10 ²¹ / c.
The m ³ p-type base layer 401 may be formed. As a result, the diffusion coefficient of C in GaAs and InGaAs is extremely small, so that the base layer 401 having a shallow impurity concentration distribution can be formed.

Then, a second layer is formed on the narrow band gap layer 40.
The wide band gap layer 50 and the cap layer 60 are sequentially grown (see FIG. 4). At this time, heat treatment of the impurities in the base layer 401 is also performed at the same time to activate the impurities. Note that this activation may be performed by RTA (850 ° C., 2 seconds) before the growth of the second wide band gap layer 50. Next, a photoresist (not shown) is applied / exposed (patterned) on the second wide band gap layer 50, and the first region RE1 and the second region RE2 of FIG.
The region between and is etched to the buffer layer 20 having low electrical conductivity. Then, the photoresist is peeled off to separate the HBT and the HEMT from each other to form the collector layer 30a, the first electron supply layer 30b, the channel layer 40b, and the second electron supply layer 50b shown in FIG. (See Figure 5). It should be noted that this element isolation is performed by the first region RE in FIG.
It may be performed by ion-implanting O ⁺ or B ⁺ from the second wide band gap layer 50 to the buffer layer 20 in the depth direction of the region between the first and second regions RE2.

Then, as shown in FIG. 6, the same lithography process (patterning and etching) as in FIG. 3 is performed to expose a part of the region of the collector layer 30a, and then the collector electrode is formed on the collector layer 30a. A region for forming 70 is formed to expose a partial region of the base layer 401, and then a region for forming the base electrode 90 is formed on the base layer 401a. At this time, the second wide bandgap layer 50 is etched to the base layer 401a by the same lithography process, and the emitter layer 50 of FIG.
a is formed.

Next, the base electrode 90 is formed by vapor deposition / lift-off in a partial region on the base layer 401a (see FIG. 7). Further, as shown in FIG. 8, on the emitter layer 50a of the HEMT via the contact layer 60d (AuGe / N
The source electrode 100 and the drain electrode 120 (which are made of the material of i) are patterned, vapor-deposited / lifted off, and alloyed at 420 ° C. for 1 minute. Then, at this time, the base layer 401 and the channel layer 40b are separated from the semiconductor substrate 10 by an equal distance in the thickness direction, and the thickness of the emitter layer 50a and the second electron supply layer 50b formed on the base layer 401 and the channel layer 40b are equal to each other. Are the same, the emitter electrode 8 and the drain electrode 120 are formed at the same time.
The formation of 0 can also be performed by the same patterning and vapor deposition / lift-off process. Next, the collector layer 30a
A collector electrode 70 is formed thereon by vapor deposition / lift-off. It should be noted that this lithography process is performed in the base layer 40.
1. Self-alignment may be used when the emitter layer 50a and these electrodes (80, 90) are formed.

Thereafter, the HE defined in the region of the source electrode 100 and the drain electrode on the second electron supply layer 50b is defined.
The same patterning (photoresist coating / exposure / removal) is performed on the MT gate region to form the second electron supply layer 50b.
Etch to a depth of about 500 angstroms from the surface. Then, the gate electrode 110 (Ti / Pt / Au) is deposited / lifted off on the gate region by recess etching using the mask used for this patterning to set the thickness of the second electron supply layer 50b to a predetermined current. To form.

After passing through these steps, the insulating film (SiN) 130 is deposited on the electrodes other than the desired electrodes by the plasma CVD method, and the wiring 140 is vapor-deposited and lifted off, as shown in FIG. A compound semiconductor device is obtained.

As described above, according to the method of manufacturing the compound semiconductor device of the present embodiment, the narrow band gap layer 40 is formed in the HBT.
Since the base layer 401 and the HEMT channel layer 40b are formed as a common layer, they are separated from the semiconductor substrate 10 by an equal distance in the thickness direction, and the source electrode 100 and the drain electrode 120 are formed in the same process. At the same time, the emitter electrode 80 can be formed by the same patterning and vapor deposition / lift-off process. In addition, the source electrode 100 and the drain electrode 120
Since the heights from the semiconductor substrate 10 are the same, the focal positions of the irradiation light at the time of exposure are the same, and the electrodes having a precise pattern can be formed. Further, by adopting this step, the step difference between the HBT and the HEMT is remarkably reduced, and the step coverage of the insulating film 130 and the electrodes arranged thereon can be improved.

In the manufacturing method of this embodiment, each layer was formed by using the MBE method, but it may be formed by the MOVPE method. In this case, MOV
Epitaxial growth by PE method is trimethyl In,
Trimethyl Ga and arsine can be used as sources.

Next, a second embodiment of the compound semiconductor device according to the present invention will be described. This compound semiconductor device is also H
Although the BT and the HEMT are formed on the same substrate, in this embodiment, the HBT has a collector-up structure. The material, composition, layer thickness and impurity concentration of each layer are the same as in the first embodiment.

FIG. 9 is a cross sectional view for explaining the structure of the compound semiconductor device according to the second embodiment. In this compound semiconductor device, HBT is formed in the first region RE1 and HEMT is formed in the second region RE2 on the semiconductor substrate 10. The HBT includes a buffer layer 20 on the semiconductor substrate 10,
Emitter layer 50a, base layer 401, collector layer 50a
And the emitter contact layer 60c are sequentially laminated. A part of the emitter layer 50a is slightly removed in the thickness direction so that the inner surface of the emitter layer 50a is exposed. An emitter electrode 80 is formed on the exposed surface of the emitter layer 50a while maintaining ohmic contact. Also, similarly to this, the base layer 4
01 is also partially exposed, and the base electrode 90 is formed on this exposed surface and the emitter electrode 80 is formed on the emitter contact layer 60c while maintaining ohmic contact.

On the other hand, the HEMT has its second electron supply layer 5
0b and the first emitter supply layer 30b are the emitter layer 50a.
And the collector layer 30a are formed corresponding to the difference from FIG. That is, the HEMT of the present embodiment is formed by sequentially stacking the second electron supply layer 50b, the channel layer 40b, and the twelfth electron supply layer 30b on the buffer layer 20 as a common layer with the HBT. There is. Then, a part of the first electron supply layer 30b is slightly removed (about 500 angstroms) in the thickness direction, and the gate electrode 110 is formed on the surface exposed by this removal while maintaining Schottky contact. . A source contact layer 60a and a drain contact layer 60b are formed on the first electron supply layer 30b with the gate electrode 110 interposed therebetween, and the source electrode 100 and the drain electrode 120 maintain ohmic contact on them. Are formed respectively. In addition, the emitter electrode 80 and the source electrode 100 have a wiring (T
i / Pt / Au) 140 for electrical connection.

With such a collector-up configuration, the area of the collector layer 30a can be reduced, so that the collector junction capacitance of the HBT is reduced and H is reduced.
The cutoff frequency of the BT and the logic circuit using the BT together with the HEMT can be improved. Further, this compound semiconductor device is manufactured by the same manufacturing method as that of the first embodiment. Therefore, the collector layer 30a and the first electron supply layer 30b
And are manufactured in the same manufacturing process. This can be an effective factor for improving the operating characteristics of this compound semiconductor device. That is, since it is effective to reduce the collector resistance to improve the cutoff frequency, it is possible to increase the impurity concentration of the collector layer 30a to realize this reduction. Moreover, since the HBT reduces the area of the collector layer 30a to reduce the collector junction capacitance, the collector junction capacitance does not increase much even if the impurity concentration is increased to reduce the collector resistance, and a high cutoff frequency is obtained. The compound semiconductor device can be operated while maintaining it. At this time, the collector layer 30a and the first electron supply layer 3
Since 0b has the same impurity concentration,
Impurities (carriers) of the first electron supply layer 30b of HEMT
The HEMT gain can be increased by increasing the concentration. However, if it is necessary to reduce the junction capacitance of the collector layer 30a in designing the circuit, the concentration of the collector layer can be reduced to about 1 × 10 ¹⁷ / cm ³ .

The present invention is not limited to the above-mentioned embodiment, but various modifications can be made. That is, in the first and second embodiments, the composition of the base layer 401 of the HBT and the channel layer 40b of the HEMT is InGaAs (In = 0.15). This is because the energy band gap of the base layer 401 is the emitter layer. It may be within a range narrower than that of 50a and within a range in which the energy band gap of the channel layer 40b is narrower than that of the first or second electron supply layers 30b and 50b (a condition A). That is, the composition of the base layer 401 is InGaAs (In = 0 to 0.3)
May be in the range.

The constituent materials and compositions of the respective layers may be as follows, as long as the condition A is satisfied. That is, as shown in the sectional configuration diagram of the third embodiment of FIG. 10, when the emitter-up HBT is used, the constituent material of the emitter layer 50a / base layer 401 is InGa.
It may be P (In = 0 to 1.0) / InGaAa, and such a configuration is also possible when a collector-up HBT is used as shown in the sectional configuration diagram of the fourth embodiment in FIG. Is. However, the constituent materials of the emitter layer 50a and the second electron supply layer 50b, and the collector layer 30a and the first electron supply layer 30b are the same. Furthermore, in the first and second embodiments, the semi-insulating GaAs is used as the semiconductor substrate 10, but semi-insulating InP can also be used as long as it satisfies the condition A. is there.

That is, as shown in the sectional structure view of the fifth embodiment of FIG. 12, the semiconductor substrate 10 is made of semi-insulating InP, the buffer layer 20 formed thereon is made of InP, and the HBT is made of the collector layer 30a ( n-type InGaAs: I
n = 0.53), base layer 401 (p-type InGaAs:
In = 0.53), emitter layer 50a (n-type AlInA
s: Al = 0.48) is sequentially laminated, and the HEMT also has the first electron supply layer 30b (n-type I).
nGaAs: In = 0.53), a channel layer 40b (non-doped InGaAs: In = 0.53), and a second electron supply layer 50b (n-type AlInAs: Al = 0.48) are sequentially laminated. Good.

Further, as long as the above condition A is satisfied, the semiconductor substrate 10 is made of semi-insulating InP, and the buffer layer formed on the semiconductor substrate 10 is as shown in the sectional configuration diagram of the sixth embodiment of FIG. 20 is AlInAs, HBT is a collector layer 30a (n-type InP), a base layer 401 (p-type InP), an emitter layer 50a (n-type AlInAs: Al).
= 0.48) are sequentially laminated, and the HEMT has a first electron supply layer 30b (n-type InP),
The channel layer 40b (non-doped InP) and the second electron supply layer 50b (n-type AlInAs: Al = 0.48) may be sequentially stacked.

However, when the compound semiconductor device shown in FIGS. 12 and 13 is configured to have a collector-up structure, HEMT
It is difficult to form such a collector-up compound semiconductor device because a good Schottky contact cannot be obtained because the gate electrode 110 of 1. is formed on InP.

As described above, the first and second
According to the configuration of the compound semiconductor device of the embodiment, HBT and H
The step difference from the EMT can be reduced, and the step coverage when forming a wiring or an insulating film (passivation film) between these devices can be improved.
In particular, since the compound semiconductor device has a small step, the wiring 140 and the electrodes (70 to 120) of the HBT and the HEMT.
Since the focal lengths of the irradiation light at the time of exposure can be set to be substantially equal during patterning such as, high precision microfabrication is possible.
As a result, this compound semiconductor device eliminates the possibility of wiring breakage and can operate with high reliability.
Moreover, the semi-insulating G is used as a constituent material of the semiconductor substrate 10.
When aAs is adopted, GaAs is used for the collector layer 30a.
Since the crystallinity of the GaAs layer constituting the HBT and the layer grown on the HBT can be maintained well, the recombination current in the base can be reduced and the operating characteristics can be improved. .

According to the manufacturing method of the compound semiconductor device of the first and second embodiments, the HEMT channel layer 40b and the HBT base layer 401 are formed in the same step. Therefore, the compound semiconductor device is manufactured. Manufacturing time can be shortened. Further, since the base layer 401 is formed by selectively using ion implantation in a desired region of the narrow bandgap layer 40, AlInAs / I
It is not necessary to consider the nGaAs-based selective etching property, and it is possible to prevent the reliability of the HEMT from deteriorating due to variations in these etchings.

[0052]

As described above, according to the method of manufacturing the compound semiconductor device of the present invention, the step between the HBT and the HEMT can be reduced, so that the wiring and the insulating film are formed between these devices. In this case, it is possible to improve the step coverage and the patterning accuracy during exposure. As a result, the compound semiconductor device of the present invention can operate with high reliability because there is no possibility of wire breakage during the manufacturing process and during operation.

According to the method of manufacturing the compound semiconductor device of the present invention, the compound semiconductor channel layer of the HEMT and the base layer of the HBT are manufactured in the same step, which shortens the manufacturing time of the compound semiconductor device. can do. Further, since this base layer is formed by selectively implanting ions serving as p-type impurities into a predetermined region in the first region on the undoped compound semiconductor layer, AlI
Even when the nAs / InGaAs-based material having a poor selective etching property is used, it is possible to prevent the HEMT from being deteriorated and the reliability of the compound semiconductor device using the HEMT from being deteriorated.

[Brief description of drawings]

FIG. 1 is a sectional configuration diagram for explaining a structure of a compound semiconductor device according to a first example.

FIG. 2 is a cross-sectional configuration diagram for explaining the method for manufacturing the compound semiconductor device according to the first example.

FIG. 3 is a cross-sectional configuration diagram for describing the method for manufacturing the compound semiconductor device according to the first example.

FIG. 4 is a sectional configuration diagram for explaining the manufacturing method for the compound semiconductor device according to the first example.

FIG. 5 is a cross-sectional configuration diagram for explaining the method for manufacturing the compound semiconductor device according to the first example.

FIG. 6 is a cross-sectional configuration diagram for explaining the method for manufacturing the compound semiconductor device according to the first example.

FIG. 7 is a cross-sectional configuration diagram for explaining the method for manufacturing the compound semiconductor device according to the first example.

FIG. 8 is a sectional configuration diagram for explaining the manufacturing method for the compound semiconductor device according to the first example.

FIG. 9 is a cross-sectional configuration diagram for explaining the structure of the compound semiconductor device according to the second example.

FIG. 10 is a sectional configuration diagram for explaining the structure of a compound semiconductor device according to a third example.

FIG. 11 is a sectional configuration diagram for explaining the structure of a compound semiconductor device according to a fourth example.

FIG. 12 is a sectional configuration diagram for explaining the structure of a compound semiconductor device according to a fifth example.

FIG. 13 is a sectional configuration diagram for explaining the structure of a compound semiconductor device according to a sixth example.

[Explanation of symbols]

10 ... Semiconductor substrate, 20 ... Buffer layer, 30a ... Collector layer, 401 ... Base layer, 50a ... Emitter layer, 60
c ... Emitter contact layer, 60a ... Source contact layer, 60b ... Drain contact layer, contact layer 60
d, 70 ... collector electrode, 80 ... emitter electrode, 90 ...
Base electrode, 100 ... Source electrode, 110 ... Gate electrode, 120 ... Drain electrode, 130 ... Insulating film, 140 ...
Wiring, 30b ... First electron supply layer, 40b ... Channel layer,
50b ... 2nd electron supply layer, 30 ... 1st wide bandgap layer, 40 ... Narrow bandgap layer, 50 ... 2nd wide bandgap layer, 60 ... Cap layer, 100 ... Photoresist.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 29/73 29/778 21/338 29/812 H01L 29/72 9171-4M 29/80 H

Claims (6)

[Claims] 1. An n formed in a first region on the same substrate
A compound semiconductor device comprising a pn heterobipolar transistor and a high electron mobility transistor formed in a second region, wherein the npn heterobipolar transistor is a first n-type compound formed in a first region on a substrate. A semiconductor layer, a p-type compound semiconductor layer formed on the first n-type compound semiconductor layer, and a second n-type compound semiconductor layer formed on the p-type compound semiconductor layer, At least one of the first and second n-type compound semiconductor layers has an energy bandgap wider than that of the p-type compound semiconductor layer, and the high electron mobility transistor includes the first n-type compound semiconductor. A third n-type compound semiconductor layer having a thickness substantially equal to that of the layer and formed in the second region on the substrate, and formed on the third n-type compound semiconductor layer And a fourth n-type compound semiconductor layer formed on the compound semiconductor channel layer, the third n-type compound semiconductor layer or the fourth n-type compound semiconductor layer Is a compound semiconductor device having an energy supply band gap wider than that of the compound semiconductor channel layer. 2. The compound semiconductor device according to claim 1, wherein the substrate includes a compound semiconductor buffer layer formed on a compound substrate. 3. The compound semiconductor device according to claim 1, wherein the second n-type compound semiconductor layer is a collector layer of a hetero bipolar transistor. 4. The third n-type compound semiconductor layer and the fourth n-type compound semiconductor layer form an electron supply layer with an energy bandgap wider than that of the compound semiconductor channel layer. The compound semiconductor device according to claim 1. 5. A method of manufacturing a compound semiconductor device comprising an npn heterobipolar transistor formed in a first region and a high electron mobility transistor formed in a second region on the same substrate having low electric conductivity. Forming a first n-type compound semiconductor common layer to serve as a collector layer of the hetero-bipolar transistor in the first region on the substrate in a common region including the first and second regions on the substrate, And a step of forming an undoped compound semiconductor common layer to be a compound semiconductor channel layer of a high electron mobility transistor in the second region in the common region on the first n-type compound semiconductor common layer. 2 and the step of implanting a hetero-by-type compound into the predetermined region in the first region on the undoped compound semiconductor common layer by implanting ions serving as p-type impurities. A third step of forming a base layer of the polar transistor; an energy bandgap wider than that of the undoped compound semiconductor common layer, and an emitter layer of the heterobipolar transistor in the first region, and a second region in the second region; A fourth step of forming a second n-type compound semiconductor common layer to serve as an electron supply layer of the high electron mobility transistor in the common region on the undoped compound semiconductor common layer, and the second n-type compound By performing mesa etching or ion implantation from the semiconductor common layer toward the substrate,
And a fifth step of electrically separating the first region and the second region from each other. 6. A method of manufacturing a compound semiconductor device comprising an npn heterobipolar transistor formed in a first region and a high electron mobility transistor formed in a second region on the same substrate having low electric conductivity. A second region which becomes an emitter layer of the hetero-bipolar transistor in the first region on the substrate and an electron supply layer of the high electron mobility transistor in the second region,
A first step of forming the n-type compound semiconductor common layer in a common region including the first and second regions on the substrate, and having an energy bandgap larger than that of the second n-type compound semiconductor common layer. Narrow and in the second region,
A second step of forming an undoped compound semiconductor common layer to be a compound semiconductor channel layer of a high electron mobility transistor in the common region on the second n-type compound semiconductor common layer, and on the undoped compound semiconductor layer And a third step of forming a base layer of the hetero-bipolar transistor by implanting ions serving as p-type impurities into a predetermined region in the first region, and forming a collector layer of the hetero-bipolar transistor in the first region. A fourth step of forming a first n-type compound semiconductor common layer in the common region on the undoped compound semiconductor common layer, and mesa etching from the first n-type compound semiconductor common layer toward the substrate. Or by performing ion implantation,
And a fifth step of electrically separating the first region and the second region from each other.