JPH0722155B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for planarizing an insulating layer on a wiring layer by an etching method.

SUMMARY OF THE INVENTION The present invention is a method for planarizing an insulating layer on a wiring layer in a semiconductor device, which comprises forming a silicate glass layer so as to cover the wiring layer, and further forming a silicon nitride layer on the silicate glass layer. And a resist layer are formed, and then these resist layer, silicon nitride layer and silicate glass layer are etched to flatten the surface of the silicate glass layer on the wiring layer, thereby obtaining a good flattened state. It was done like this.

[Conventional technology]

When manufacturing a semiconductor device having a multilayer wiring structure, a technique for flattening the surface is required. Heretofore, various methods such as an anodic oxidation method, a resin coating method, a glass flow method, an etching method, a lift-off method, a bias pattern method, etc. have been proposed as a flattening technique for this multilayer wiring ("Semiconductor World" Press Journal Company). , See the October 1984 issue). The present invention particularly relates to the etching method. According to the conventional etching method, one kind of insulating layer is formed to a thickness equal to or larger than the stepped portion of the wiring, a resist is applied on the insulating layer, and then plasma etching is performed. Alternatively, the surface layer is uniformly scraped off by RIE (Reactive Ion Etching) to form a flat insulating layer. Examples of materials for the insulating layer include SiO ₂ , PSG (phosphorus silicate glass), and plasma S
iN is used.

[Problems to be solved by the invention]

When etching is performed by forming a resist layer on the insulating layer made of PSG (or SiO ₂ ) by the conventional etching method, the oxygen decomposed from the PSG layer accelerates the etching of the resist layer as the etching time elapses. Contrary to this, unevenness progresses and a flat surface cannot be obtained. Especially, since the etching speed is high near the step of the wiring,
A groove is formed in this portion due to abnormal etching. As a result, disconnection may occur, which may lead to disconnection of wiring or shortage.

Further, when a resist layer is formed on the insulating layer made of plasma SiN and is etched back, SiN has a larger dielectric constant than SiO ₂ or PSG, so that the parasitic capacitance increases and there is a problem in increasing the speed of the semiconductor device. Occurs.

The present invention provides a flattening method capable of solving the above problems.

[Means for solving problems]

In the method for manufacturing a semiconductor device, a step of sequentially forming a silicate glass layer (3), a silicon nitride layer (4) and a resist layer (5) on a substrate (1) to cover a step portion formed of a wiring (2). A step of etching the resist layer (5) and the silicon nitride layer (4) to flatten the surface of the silicon nitride layer (4), and a step of etching the silicon nitride layer (4) and the silicate glass layer (3) There is a step of flattening the surface of the glass layer (3).

In the first planarization step for planarizing the surface of the silicon nitride layer (4), the resist layer (5) and the silicon nitride layer (4) are used.
It is necessary to make the etching speeds of the same to be the same, but this can be realized by appropriately adjusting the etching conditions such as the composition of the etching gas and the reaction pressure. In addition, the surface of the silicate glass layer (3) is flattened 2
Also in the case of the second flattening step, the etching conditions are similarly appropriately adjusted so that the etching rates of the silicon nitride layer (4) and the silicate glass layer (3) are the same.

As the silicate glass, PSG, AsSG (arsenic silicate glass), SiO ₂ or the like can be used.

[Action]

According to the present invention, since the insulating layer formed under the resist layer (5) is the silicon nitride layer (4), it is possible to control the etching speed of both layers to be constant during etching. . That is, when the insulating layer (PSG layer, SiO ₂ layer, etc.) containing oxygen under the resist layer (5) as in the conventional case, oxygen in the layer changes the etching rate of the resist (5), Although a constant etching speed cannot be obtained, the present invention eliminates such a fear. Therefore, the same flat surface as the flat surface on the resist layer (5) can be obtained even after the flattening step without causing abnormal etching. Further, since the insulating layer on the wiring (2) is the silicate glass layer (3), there is no fear that the parasitic capacitance will increase.

〔Example〕

 Embodiments of the present invention will be described with reference to the drawings.

First, as shown in A, after forming an Al wiring (2) on a Si substrate (1), a PSG layer (3) thicker than the thickness of the Al wiring (2) is formed by CVD to cover the Al wiring (2). (Temperature is 420 ° C). Next, a plasma SiN layer (4) is formed on the PSG layer (3) with a thickness equal to or larger than the step of the PSG layer (3). During the formation, it is necessary to form the Al wiring (2) at a temperature of 450 ° C. or lower in order to prevent the Al wiring (2) from melting and breaking. Next, a resist layer (5) is formed on the SiN layer (4) so that the surface becomes flat.

Next, as shown in B, a resist layer (5) and a SiN layer (4)
Etching conditions are adjusted so that the etching speeds are the same, and etching is performed by RIE to flatten the surface of the SiN layer (4).

Next, as shown in C, the etching conditions are adjusted so that the etching rates of the SiN layer (4) and the PSG layer (3) are the same, and etching is performed by RIE, and the PSG layer (3) on the Al wiring (2) is ) Is finally flattened.

〔The invention's effect〕

According to the present invention, two insulating layers made of silicate glass and silicon nitride are formed on a stepped portion of a wiring, and a resist layer is further formed on the insulating layer, and then a resist layer, a silicon nitride layer and a silicon nitride layer are formed. Since the silicate glass layers are sequentially etched back to be flattened, the etching speed of each layer during etching can be controlled to be constant. Therefore, the insulating layer on the wiring can be flattened neatly without step breakage, so that disconnection and shorting of the wiring can be prevented. Further, since the insulating layer finally formed on the wiring is the silicate glass layer, the problem of the parasitic capacitance unlike the case of the silicon nitride layer does not occur. The present invention is particularly suitable as a wiring technology for MOS / LSI and bar polar LSIs.

[Brief description of drawings]

The drawings are process drawings showing an embodiment of the present invention. (1) is the Si substrate, (2) is the wiring, (3) is the PSG layer,
(4) is a SiN layer, and (5) is a resist layer.

Claims (1)

[Claims] 1. A step of forming a silicate glass layer so as to cover a step portion formed on a substrate, a step of forming a silicon nitride layer on the silicate glass layer, and a resist layer formed on the silicon nitride layer. And a step of etching the resist layer, the silicon nitride layer, and the silicate glass layer to flatten the surface of the silicate glass layer.