JPH07226356A - 多層レジストを利用したパターン形成方法 - Google Patents

多層レジストを利用したパターン形成方法

Info

Publication number
JPH07226356A
JPH07226356A JP5314066A JP31406693A JPH07226356A JP H07226356 A JPH07226356 A JP H07226356A JP 5314066 A JP5314066 A JP 5314066A JP 31406693 A JP31406693 A JP 31406693A JP H07226356 A JPH07226356 A JP H07226356A
Authority
JP
Japan
Prior art keywords
resist
layer
pattern
forming
layer resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5314066A
Other languages
English (en)
Japanese (ja)
Inventor
Jun Seok Lee
ズン・ソク・リ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
LG Semicon Co Ltd
Goldstar Electron Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to DE4339466A priority Critical patent/DE4339466C2/de
Application filed by LG Semicon Co Ltd, Goldstar Electron Co Ltd filed Critical LG Semicon Co Ltd
Priority to JP5314066A priority patent/JPH07226356A/ja
Publication of JPH07226356A publication Critical patent/JPH07226356A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/06—Planarisation of inorganic insulating materials
    • H10P95/062—Planarisation of inorganic insulating materials involving a dielectric removal step

Landscapes

  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
JP5314066A 1993-11-19 1993-11-22 多層レジストを利用したパターン形成方法 Pending JPH07226356A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE4339466A DE4339466C2 (de) 1993-11-19 1993-11-19 Verfahren zur Bildung von Mustern unter Verwendung eines Mehrschichtresists
JP5314066A JPH07226356A (ja) 1993-11-19 1993-11-22 多層レジストを利用したパターン形成方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE4339466A DE4339466C2 (de) 1993-11-19 1993-11-19 Verfahren zur Bildung von Mustern unter Verwendung eines Mehrschichtresists
JP5314066A JPH07226356A (ja) 1993-11-19 1993-11-22 多層レジストを利用したパターン形成方法

Publications (1)

Publication Number Publication Date
JPH07226356A true JPH07226356A (ja) 1995-08-22

Family

ID=25931345

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5314066A Pending JPH07226356A (ja) 1993-11-19 1993-11-22 多層レジストを利用したパターン形成方法

Country Status (2)

Country Link
JP (1) JPH07226356A (de)
DE (1) DE4339466C2 (de)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7435682B2 (en) 2004-05-31 2008-10-14 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
US10312074B2 (en) 2014-10-31 2019-06-04 Samsung Sdi Co., Ltd. Method of producing layer structure, layer structure, and method of forming patterns
US10663863B2 (en) 2015-10-23 2020-05-26 Samsung Sdi Co., Ltd. Method of producing layer structure, and method of forming patterns
US10770293B2 (en) 2017-08-29 2020-09-08 Taiwan Semiconductor Manufacturing Co., Ltd. Method for manufacturing a semiconductor device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7262070B2 (en) * 2003-09-29 2007-08-28 Intel Corporation Method to make a weight compensating/tuning layer on a substrate

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4891303A (en) * 1988-05-26 1990-01-02 Texas Instruments Incorporated Trilayer microlithographic process using a silicon-based resist as the middle layer

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7435682B2 (en) 2004-05-31 2008-10-14 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
US10312074B2 (en) 2014-10-31 2019-06-04 Samsung Sdi Co., Ltd. Method of producing layer structure, layer structure, and method of forming patterns
US10663863B2 (en) 2015-10-23 2020-05-26 Samsung Sdi Co., Ltd. Method of producing layer structure, and method of forming patterns
US10770293B2 (en) 2017-08-29 2020-09-08 Taiwan Semiconductor Manufacturing Co., Ltd. Method for manufacturing a semiconductor device

Also Published As

Publication number Publication date
DE4339466C2 (de) 2001-07-19
DE4339466A1 (de) 1995-05-24

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