JPH0722907A - Radio receiver - Google Patents

Abstract

PURPOSE:To make the interruption of a voice signal during the reception of an electronic tuner tolerable by letting a phase locked frequency synthesizer converge as quickly as possible when broadcasting electric field intensity is checked, in a frequency modulated ratio receiver. CONSTITUTION:When the reception state of a radio broadcast at a frequency f0 is continued for about 5 seconds, a mute circuit 10 is interrupted at time t1, a frequency division ratio setting signal responding to a frequency f1 to be received is supplied by changing the circuit to a frequency divider circuit 21 at the time t2 and thereafter, and at the same time, a common contact 35 of a changeover switch 32 is switched from an individual contact 33 to an individual contact 34. From the contact 35, a voltage is supplied to a voltage controlled oscillation circuit 24, and when the period from the time t2 to the time t3, for example, 0.5ms passes, the voltage imparted to a circuit 24 is changed to a voltage which is equal to the voltage responding to the frequency f1 to be received. Next, when the contact 35 is switched to the individual contact 33, whether the time W2 from the time t3 to t4 passed is judged. If the time is judged to have passed, the locking of a phase locked frequency synthesizer 6 is converged in short time W4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is applicable to, for example, RDS (Radi
The present invention relates to a radio receiver suitable for receiving a frequency modulation (abbreviated as FM) radio broadcast called Data System).

[0002]

2. Description of the Related Art Such RDS broadcasting is carried out, for example, in Europe, and the high frequency signal of this radio broadcasting is not limited to audio signals, and information concerning radio broadcasting is transmitted in a frequency band higher than the audio signals. In the radio broadcast including the data signal that represents and the data signal matches or approximates, the broadcast content of the audio signal matches or approximates. Therefore, when such a radio receiver is installed in an automobile, the electric field strength of each radio broadcast is checked based on the data signal, and even if the automobile moves, the radio broadcast having the necessary electric field intensity is automatically tracked. And can be received.

In such a radio receiver, when a single electronic tuner is used to receive one radio broadcast while checking the electric field strength of another broadcast station, the audio signal being received is interrupted. Therefore, such time needs to be as short as possible.

[0004]

SUMMARY OF THE INVENTION An object of the present invention is to provide a radio receiver capable of shortening the operation of an electronic tuner when changing the receiving operation state of one radio broadcast to another receiving frequency. Is to provide.

[0005]

According to the present invention, a voltage control type oscillator circuit is provided with a frequency divider circuit for dividing the output by a variable frequency division ratio.
The output of this frequency dividing circuit and the output of the reference frequency oscillating circuit are given to the phase comparing circuit to output a voltage corresponding to the phase difference, and the voltage output is given to the voltage controlling type oscillating circuit. , A phase-locked loop frequency synthesizer having a phase difference between the output of the reference frequency oscillator and the output of the reference frequency oscillator, and an electronic tuner for receiving a frequency corresponding to the output frequency of the voltage controlled oscillator, a voltage output means, and an electronic tuner. At the time of changing the reception frequency of, the voltage output means generates a voltage approximately equal to the voltage to be applied to the voltage-controlled oscillation circuit corresponding to the frequency to be changed by the electronic tuner and applied to the voltage-controlled oscillation circuit. , The frequency divider circuit is operated so that the frequency division ratio corresponds to the frequency to be changed and received, and then the output of the phase comparator circuit is changed. A radio receiver which comprises a control means for providing switched to pressure control forms an oscillation circuit.

Further, according to the present invention, the output of the first voltage control type oscillation circuit is applied to a first frequency dividing circuit which divides the frequency with a variable frequency division ratio, and the output of the first frequency dividing circuit and the first reference frequency oscillation circuit. And the output to the first phase comparison circuit to output a voltage corresponding to the phase difference, and the voltage output to the first voltage control type oscillation circuit,
Thus, the first phase-locked loop frequency synthesizer having the same phase difference between the output of the first voltage-controlled oscillator circuit and the output of the first reference-frequency oscillator circuit is provided, which corresponds to the output frequency of the first voltage-controlled oscillator circuit. The first electronic tuner for receiving the frequency and the output of the second voltage control type oscillation circuit are given to a second frequency dividing circuit which divides the frequency by a variable frequency division ratio, and the output of the second frequency dividing circuit and the second reference frequency oscillation. The output of the circuit and the second
The voltage corresponding to the phase difference is output to the phase comparison circuit,
The voltage output is provided to the second voltage control type oscillation circuit, so that a second phase lock loop frequency synthesizer is provided in which the phase difference between the output of the second voltage control type oscillation circuit and the output of the second reference frequency oscillation circuit matches. When changing the receiving frequency of the second electronic tuner and the first electronic tuner that receive the frequency corresponding to the output frequency of the second voltage control type oscillation circuit, the first electronic tuner is changed to correspond to the frequency to be received. The voltage which is almost equal to the voltage to be applied to the first voltage controlled oscillator circuit is set to the second frequency by setting the frequency division ratio of the second frequency divider circuit.
The output of the phase comparison circuit is generated and given to the first voltage control type oscillation circuit, and the first frequency division circuit is operated so that the frequency division ratio corresponds to the frequency to be changed and received. A radio receiver including a control means for switching the output of the one-phase comparison circuit to the first voltage control type oscillation circuit and giving it.

[0007]

According to the present invention, in a radio receiver provided with an electronic tuner having a phase-locked loop frequency synthesizer, a frequency output means is provided, and when changing the receiving frequency of the electronic tuner, first, the frequency to be changed and received is changed. A voltage substantially equal to the voltage to be applied to the voltage controlled oscillator circuit, that is, a matched voltage or an approximate voltage, is stably generated by the voltage output means,
In this state, next, the voltage from the voltage output means is applied to the voltage-controlled oscillation circuit of the electronic tuner, and the frequency division circuit is operated so that the frequency division ratio corresponds to the frequency to be changed and received, Therefore, after the voltage from the voltage output means is applied to the voltage-controlled oscillation circuit and the voltage-controlled oscillation circuit is in a state of being applied with a voltage substantially equal to the voltage corresponding to the frequency to be changed and received, The output from the operation of the frequency dividing circuit is given to the phase comparison circuit, and thus the convergence time of the phase lock loop frequency synthesizer can be shortened.

According to the present invention, a first electronic tuner for receiving, for example, an FM radio broadcast and a second electronic tuner for receiving, for example, an amplitude modulation (abbreviated as AM) radio broadcast are provided, and the first electronic tuner is provided. When changing from the current reception state of a radio broadcast to another frequency to be received by the electronic tuner of, the frequency division ratio of the second frequency dividing circuit in the second electronic tuner is set and the second phase is set. The output of the comparison circuit generates a voltage substantially equal to the voltage to be applied to the first voltage control type oscillation circuit corresponding to the frequency to be changed and received, that is, a matched voltage or an approximate voltage, and the second phase comparison is performed. While the output of the circuit is stable, the output of the second phase comparator circuit is applied to the first voltage controlled oscillator circuit and the first frequency divider circuit of the first electronic tuner is operated to change the frequency. The frequency division ratio corresponding to the frequency to be received is changed, and then the output of the first phase comparison circuit is switched to the first voltage control type oscillation circuit to be provided, whereby the first electronic tuner When changing the frequency, the second electronic tuner can be used to shorten the convergence time of the first phase lock loop frequency synthesizer when changing the reception frequency of the radio broadcast in the first electronic tuner.

[0009]

1 is a block diagram showing the overall configuration of a radio receiver 1 for receiving an RDS radio broadcast according to an embodiment of the present invention. This radio receiver 1 is installed in an automobile and used, and can receive RDS frequency modulation radio broadcasting. The RDS radio broadcast is a frequency-modulated high-frequency signal including a voice signal and a data signal transmitted in a frequency band of 57 kHz higher than the voice signal, and is broadcast from a plurality of broadcasting stations.

The data signal includes a so-called PI code, and this PI code is composed of a plurality of digits, and each digit represents the nationality of the radio broadcasting station, the receiving service area, and whether it is a master station or a slave station. And a signal representing a group of radio broadcasting stations forming a common network. A radio broadcast in which all of the multiple digits of the PI code match has the same broadcast content of the audio signal, and in a radio broadcast in which most of the digits match, the content of the audio signal is almost the same. It will include programs that match but are slightly different.

A frequency modulated high frequency signal including a voice signal and a data signal from a radio broadcasting station is received by an antenna 2 of a radio receiver 1 and tuned by an electronic tuner 3. The electronic tuner 3 includes an amplifier circuit 4 for amplifying a high frequency signal from the antenna 2, a superheterodyne mixing circuit 5, a phase lock loop frequency synthesizer 6,
And an intermediate frequency amplifier circuit 7. The output of the intermediate frequency amplification circuit 7 is demodulated by the demodulation circuit 8, the audio signal is amplified from the line 9 through the mute circuit 10, the low frequency amplification circuit 11, and the speaker 12 sonicates.

The received electric field strength of the radio broadcast that has been tuned and received is given from the intermediate frequency amplifier circuit 7 to the analog / digital conversion circuit 15 included in the control circuit 14 via the line 13 and converted into a digital value. And is given to the processing circuit 16.

The output from the intermediate frequency amplifier circuit 7 is applied to a band pass filter 17 to extract a data signal in the band of 57 kHz, for example, and to a decoder 18 for decoding the data signal to be decoded.
To the memory M1. This memory M1 is connected to the processing circuit 16 together with another memory M2.

The phase lock loop frequency synthesizer 6 includes a reference frequency oscillator circuit 20 for generating a signal having a predetermined constant reference frequency, a frequency divider circuit 21 having a variable frequency division ratio, and an output of the reference frequency oscillator circuit 20. And the output of the frequency divider circuit 21 are compared with each other to output a voltage corresponding to the phase difference and outputting a voltage for making the phase difference zero. And the low-pass filter 2
And a voltage control type oscillation circuit 24 that changes the oscillation frequency so that the phase difference becomes zero. The output of 24 is given to the frequency dividing circuit 21 from the line 25 and is also given to the mixing circuit 5 to be used for tuning.

The processing circuit 16 gives a signal for setting the frequency division ratio of the frequency dividing circuit 21 to the frequency dividing circuit 21 via the line 26. The processing circuit 16 sets the frequency division ratio of the frequency dividing circuit 21 included in the phase-locked loop frequency synthesizer 6 so that the reception frequency of the radio broadcasting input by the key input means 27 is set, and the desired radio broadcasting is received. You can listen to it. In this way, the PI code and the frequency f forming a part of the data signal of the radio broadcast currently being received.
0, f1, f2, ... Are stored in the first memory M1.

A digital signal is applied from the processing circuit 16 to the digital / analog conversion circuit 28 constituting the voltage output means, and the voltage output generated by the digital signal is supplied to the line 2.
9 is derived. This voltage is applied from the line 29 to the analog / digital conversion circuit 31 via the voltage conversion circuit 30, and a negative field back loop is formed in this way, and the output voltage of the line 29 becomes the voltage set in the processing circuit 16. Controlled as. The output of the low pass filter 23 and the output of the line 29 are given to the individual contacts 33 and 34 of the changeover switch 32, respectively.
The output of the common contact 35 is applied to the voltage controlled oscillator circuit 24 as described above, and is also applied to the high frequency amplifier circuit 4 for tuning.

FIG. 2 is a diagram showing a memory map of the memory M1. A storage area for the received electric field strength corresponding to the frequencies f0, f1, f2, ... Of the radio broadcast is provided, and a signal representing the received electric field strength, which is a digital value obtained by conversion by the analog / digital conversion circuit 15, is processed. The circuit 16 causes the memory M1 to have reference marks S0, S1, S2.
Stored as indicated by.

FIG. 3 is a graph showing the relationship between the frequency of FM radio broadcasting of the electronic tuner 3 and the output voltage applied from the changeover switch 32 to the voltage controlled oscillator circuit 24. In this embodiment, for simplification of description, a voltage corresponding to the reception frequency by a linear function is set.

FIG. 4 is a diagram showing a memory map of the memory M2. For each predetermined range of the reception frequency f, the processing circuit 16 derives the output voltage set in the memory M2 from the line 29 by the digital / analog conversion circuit 28. Each output voltage is set to the voltage corresponding to the lowest frequency in the range of its reception frequency.

FIG. 5 is a diagram showing in simplified form the frequency of radio broadcasting and its electric field strength. The reception frequencies f0, f1, f2, ... Of the radio broadcast are selected and received by the electronic tuner 3, and the reception electric field strengths S0, S1, S2, S thereof are received.
, ... are stored in the memory M1 as described above, and such an operation is performed every 5 seconds while receiving the radio broadcast of the frequency f0.
To check the received electric field strength of f2, ...
2, for example, it is received every 15 msec.

FIG. 6 is a flow chart for explaining the operation of the processing circuit 16. Moving from step a1 to step a2, the common contact 35 of the changeover switch 32 is connected to the individual contact 33, and in this state, the reception frequency f0 is tuned at step a3, whereby analog / digital of the currently received radio broadcast is obtained. The received electric field strength detected by the conversion circuit 15 is stored in the memory M1 by the operation of the processing circuit 16 in a step a4 as indicated by reference numeral S0 in FIG.

When checking the reception electric field strength of the radio broadcast having the frequency f1 during the reception of this radio broadcast, first, in step a5, the digital / analog conversion circuit 28 should be changed to the line 29 and received. A signal preset in the memory M2 as shown in FIG. 4 is derived corresponding to the frequency f1. Step a6
Then, it is judged whether or not the reception state of the frequency f0 currently being received has passed the time T1 shown in FIG. 5, for example, 5 seconds, and during this time T1, it is led from the digital / analog conversion circuit 28 to the line 29. Voltage is stable enough.

FIG. 7 is a waveform diagram for explaining the operation of the radio receiver 1 shown in FIG. FIG. 7A shows the operation of the mute circuit 10. When it is determined in step a6 that the reception state of the radio broadcast of the frequency f0 has elapsed for 5 seconds, in the next step a7, the mute circuit 10 is cut off at time t1. Next, at step a8, after the time t2, the frequency dividing circuit 21 is set by giving the frequency dividing ratio setting signal representing the frequency dividing ratio corresponding to the frequency f1 to be changed and received. At the same time, at time t2, as shown in step a9, the common contact 35 of the changeover switch 32 is changed over from the individual contact 33 to the state of conduction. FIG. 7 (2) shows
The voltage applied from the common contact 35 of the changeover switch 32 to the voltage controlled oscillator circuit 24 is shown. In step a10, it is determined whether the time W1 from time t2 to time t3 has elapsed. The time W1 is, for example, 0.5 ms
Selected as ec. Thus, at time t3, the voltage applied to the voltage-controlled oscillator circuit 24 is changed as shown in FIG. 4 and is approximately equal to the voltage corresponding to the frequency f1 to be received, that is, an approximate voltage is derived in this embodiment. It This voltage may be selected to be exactly the voltage corresponding to the frequency f1.

At the next step a11, the common contact 35 of the changeover switch 32 is switched to the individual contact 33 again to be conductive, and at the next step a12, it is determined whether the time W2 from time t3 to time t4 has elapsed. To be judged.

FIG. 7 (3) shows the level of the received electric field strength of the received frequency f1 derived from the intermediate frequency amplifier circuit 7 to the line 13. As shown in this embodiment, at times t2 to t3, the voltage corresponding to the frequency f1 to be changed and received from the digital / analog conversion circuit 28 to the voltage control type oscillation circuit 24 via the line 29 and the changeover switch 32. Since a voltage substantially equal to is applied to the phase lock loop frequency synthesizer 6 after the time t3, the phase lock of the phase lock loop frequency synthesizer 6 is converged, and the convergence time is shortened and stabilized.

The time W2 in step a12 is equal to or more than the sum of the time taken for the phase lock loop frequency synthesizer 6 to lock to the new frequency f1 and the time until the level of the received electric field strength S1 at the frequency f1 is stably obtained. Set in time. This time W2 is 2-3 msec
Is. At step a13, the received electric field strength S1 of the frequency f1 is stored in the memory M1.

In this way, during reception of the radio broadcast of the frequency f0, after checking the reception electric field strength S1 of the other frequency f1, the radio broadcast of the original frequency f0 can be received again. In step a14,
At time t4, a signal representing the frequency division ratio corresponding to the frequency f0 is given to the frequency dividing circuit 21 from the line 26, and then, at step a15, it is determined whether or not the time W3 has elapsed. This time W3 may be 1 msec, for example, and is set to be longer than the time required for the phase-locked loop frequency synthesizer 6 to lock and converge at the frequency f0. At step a16, the mute circuit 10 is turned on at time t5, thus ending the series of operations.

As another embodiment, in order to further shorten the time W3 between the times t4 and t5, the voltage of the memory M2 corresponding to the original frequency f0 is set by the digital / analog conversion circuit 28 after the time t3. At t4, the voltage control type oscillation circuit 24 is switched from the contacts 34 and 35 of the changeover switch 32
Then, at the time t4, the frequency division ratio of the frequency division circuit 21 is set to the frequency division ratio corresponding to the frequency f0, and the changeover switch 32 is changed over from the contact 34 to the contact 33 to achieve the phase lock, that is, the above-mentioned. The same operation as at times t2 to t3 may be performed.

In this way, the frequencies f0 and f at which the PI code of the data signal of the RDS radio broadcast is similar to each other.
After the reception electric field strengths of 1, f2, ... Are stored in the memory M1, when the reception electric field strength of the currently received radio broadcast of the frequency f0 decreases, the operation shown in FIG. 8 is performed. The changeover switch 32 has contacts 33, 3
5 is conducting. When it is determined that the received electric field strength S0 of the frequency f0 of the radio broadcast becomes less than the predetermined discrimination level SL, the process proceeds from step b1 to b2.
Moving to step b3, the contents stored in the memory M1 are read, a radio broadcast having a received electric field strength larger than the received electric field strength S0 is searched, and a radio broadcast frequency having the maximum received electric field strength, for example, f1 is found.

Therefore, first, at step b4, the frequency f1
The digital / analog conversion circuit 28 is operated so as to obtain a voltage corresponding to. Thereafter, in step b5, the mute circuit 10 is cut off, and at the same time, in step b6, the frequency division ratio of the frequency divider circuit 21 is set to a value corresponding to the reception frequency f1. After that, in step b7, the common contact 35 of the changeover switch 32 is switched to the individual contact 34, and in step b8, it is determined whether or not the time W1 described above has elapsed. When the time W1 elapses, the common contact 35 of the changeover switch 32 is returned to the individual contact 33 in step b9, and the time W4 required for the phase lock loop frequency synthesizer 6 to lock and converge in step b10.
To determine if has passed. When the time W4 has elapsed, the mute circuit 10 is turned on in step b11, thus ending the series of operations. As a result, radio broadcasts having exactly the same or almost the same broadcast content are continuously received at the frequency f1.

FIG. 9 is a block diagram showing the overall construction of a radio receiver 37 for receiving RDS radio broadcasting according to another embodiment of the present invention. The radio receiver 37 has a configuration similar to that of the radio receiver 1 of the above-described embodiment, and the corresponding parts are designated by the same reference numerals and the same numerals are denoted by the subscript a. In addition to the electronic tuner 3 for receiving FM radio broadcasting, another electronic tuner 3a for receiving AM radio broadcasting is provided.

A change-over switch 38 is provided for switching between FM radio broadcasting and AM radio broadcasting. The common contact 39 is connected to the individual contact 40 when FM broadcasting is received, and the common contact 39 is individually arranged for listening to AM broadcasting. It is switched to the contact 41 to conduct electricity. In this embodiment, while receiving FM broadcast which is RDS radio broadcast, as in the above-mentioned embodiment,
The electronic tuner 3a is used to switch from the currently received frequency f0 to the frequency f1 and check the received electric field strength. As shown in FIG. 10, in the memory M2a, voltages TB1, TB2, ... Derived to the line 29 are determined over each frequency range of FM radio broadcasting, and the output voltage of AM broadcasting is as shown in FIG. Each corresponds to a reception frequency in which radio broadcasting can exist.

12 is used to check the received electric field strength of the radio broadcast of the FM frequency f1 as described above, while receiving the radio broadcast of the FM frequency f0 using the FM electronic tuner 3. Done. The operation by the processing circuit 16 of FIG. 12 is similar to the operation of FIG. 6 described above,
Therefore, the operation will be briefly described. Step c1
From step c2, the common contact 35 of the changeover switch 32 is connected to the individual contact 33 during reception of the frequency f0. In this state, the reception frequency f0 is tuned in step c3, and the radio broadcast currently being received is thereby received. The received electric field strength detected by the analog / digital conversion circuit 15 is stored in the memory M1 by the operation of the processing circuit 16 in the same manner as indicated by the reference symbol S0 in FIG. 2 in step c4.

When checking the reception electric field strength of the radio broadcast having the frequency f1 during the reception of this radio broadcast, first in step c5, the frequency of the AM radio broadcast corresponding to the frequency f1 to be changed and received is shown. The frequency division ratio to be given to the frequency dividing circuit 21a is determined so that the output voltage can be obtained by reading out from the 10 memories M2a. The frequency f1 to be changed and received is, for example, 77 to 7
When in the range of 8 MHz, the frequency 531 kHz of the AM radio broadcast corresponding thereto is determined, the frequency division ratio N1 for deriving the output voltage TB2 corresponding to the frequency 531 kHz of the AM radio broadcast is read from the memory M2a, and the electronic tuner is read. At 3a, the phase lock loop frequency synthesizer 6a is locked and converged in a state in which the frequency 531 kHz of the AM radio broadcast corresponding to the frequency division ratio N1 can be received.

At step c6, the frequency f currently being received is f.
It is determined whether the reception state of 0 has passed the above-mentioned time T1 shown in FIG. 5, for example, 5 seconds, and during this time T1, the voltage derived from the phase-locked loop frequency synthesizer 6a to the line 29 is sufficient. It is in a stable state.

When it is determined in step c6 that the reception state of the radio broadcast of the frequency f0 has elapsed for 5 seconds,
In the next step c7, the mute circuit 10 is cut off at time t1 in FIG. Next, at step c8, after the time t2, the frequency dividing circuit 21 is set by applying the frequency dividing ratio setting signal indicating the frequency dividing ratio corresponding to the frequency f1 to be changed and received.
At the same time, at time t2, the common contact 35 of the changeover switch 32 is changed to the individual contact 33 as shown in step c9.
From 34 to 34 for conduction, whereby the voltage TB2 corresponding to the frequency division ratio N1 derived from the phase lock loop frequency synthesizer 3a to the line 29 is applied from the changeover switch 32 to the voltage controlled oscillator circuit 24.
In step c10, it is determined whether or not the time W1 from time t2 to time t3 has elapsed. The time W1 is selected to be 0.5 msec, for example. Thus, at the time t3, the voltage applied to the voltage controlled oscillator circuit 24 is substantially equal to the voltage corresponding to the frequency f1 to be changed and received, that is, the operation by the approximate voltage TB2 in this embodiment is stabilized.

At the next step c11, the common contact 35 of the changeover switch 32 is switched to the individual contact 33 again to be conductive, and at the next step c12, it is determined whether the time W2 from time t3 to time t4 has elapsed. To be judged.

As shown in this embodiment, from time t2
At t3, a voltage TB2 that is substantially equal to the voltage corresponding to the frequency f1 to be changed and received is sent from the phase lock loop frequency synthesizer 6a for AM radio broadcasting to the voltage control type oscillation circuit 24 via the line 29 and the changeover switch 32. Since it is given, the convergence of the phase lock of the phase lock loop frequency synthesizer 6 is completed in a short time W4 after the subsequent time t3, and the convergence time is shortened and stabilized.

The time W2 in step c12 is
The time is set to be equal to or longer than the sum of the time required for the phase lock loop frequency synthesizer 6 to lock to the new frequency f1 and the time until the level of the received electric field strength S1 at the frequency f1 is stably obtained. This time W2 is 2-3 ms
ec. In step c13, the received electric field strength S1 of the frequency f1 is stored in the memory M1.

Thus, during reception of the radio broadcast of the frequency f0, after checking the reception electric field strength S1 of the other frequency f1, the radio broadcast of the original frequency f0 can be received again. In step c14,
At time t4, a signal representing the frequency division ratio corresponding to the frequency f0 is given to the frequency dividing circuit 21 from the line 26, and then, at step c15, it is determined whether or not the time W3 has elapsed. This time W3 may be, for example, 1 msec, and is set to be longer than the time required for the phase-locked loop frequency synthesizer 6 to lock and converge at the frequency f0. At step c16, the mute circuit 10 is turned on at time t5, thus ending the series of operations.

As another embodiment, in order to further shorten the time W3 from time t4 to time t5, after the time t3, the frequency divider circuit 21 of the phase-locked loop frequency synthesizer 6a.
A voltage TB1 corresponding to the frequency division ratio N0 corresponding to the frequency f0 is set in a via the line 26a, and the time t is set.
In step 4, the voltage control type oscillation circuit 24 is supplied from the contacts 34 and 35 of the changeover switch 32, and at the time t4, the frequency division ratio of the frequency divider circuit 21 is set to the frequency division ratio corresponding to the frequency f0. 33 so that the phase lock is achieved, that is, the time t2 to t3 described above.
An operation similar to the above may be performed.

In this embodiment of FIG. 9, operations similar to those shown in connection with FIG. 8 above are also achieved. That is, in this embodiment, the combination of the digital / analog conversion circuit 28, the voltage conversion circuit 30, and the analog / digital conversion circuit 31 in FIG. 1 described above achieves the same function by the electronic tuner 3a for receiving the AM radio broadcast. Thus, the electronic tuner 3a is also used for receiving and listening to AM radio broadcasts.

[0043]

As described above, according to the present invention, in a radio receiver using an electronic tuner, voltage output means is prepared, and this voltage output means is changed prior to changing the frequency of the electronic tuner. Generates a voltage approximately equal to the voltage to be applied to the voltage control type oscillation circuit corresponding to the frequency to be received, supplies the output of the voltage output means to the voltage control type oscillation circuit, and operates the frequency divider circuit of the electronic tuner. The frequency division ratio corresponding to the frequency to be received is changed, and then the output of the phase comparison circuit is switched to the voltage control type oscillation circuit to be given, so that the phase lock loop frequency synthesizer converges. The time can be shortened, and for checking the electric field strength of other radio broadcasting while receiving the electronic tuner, for example, for a very short time, for example, about 5msec is only just the audio signal is interrupted, it is possible to the extent that there is no hindrance.

Further, according to the present invention, in the radio receiver including the first and second electronic tuners in total, the second electronic tuner is used to change the reception frequency of the first electronic tuner. The convergence time of the first phase lock loop frequency synthesizer in the first electronic tuner can be shortened, and such a configuration also has an advantage that the configuration can be simplified.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a radio receiver 1 according to an embodiment of the present invention.

FIG. 2 is a diagram showing a memory map of a memory M1.

FIG. 3 is a graph showing the relationship between the reception frequency of radio broadcasting and the voltage applied to the voltage controlled oscillator circuit 24.

FIG. 4 is a diagram showing a memory map of a memory M2.

FIG. 5 is a diagram for explaining an operation for checking the reception electric field strength of radio broadcasts of other frequencies f1, f2, ... While receiving a radio broadcast of frequency f0.

FIG. 6 is a flowchart for explaining the operation of the processing circuit 16 for checking the received electric field strength.

FIG. 7 is a waveform diagram for explaining an operation for checking the received electric field strength.

FIG. 8 is a flowchart for explaining an operation for switching to another radio broadcast having the same or similar broadcast content when the reception electric field strength S0 decreases during reception of the radio broadcast of the frequency f0. .

FIG. 9 is a block diagram showing the overall configuration of a radio receiver 37 according to another embodiment of the present invention.

10 is a memory M of the radio receiver 37 shown in FIG.
It is a figure which shows the memory map of 2a.

11 shows two electronic tuners 3, 3a shown in FIG.
3 is a graph showing the relationship between the voltage and the voltage applied to the voltage controlled oscillation circuits 24 and 24a.

FIG. 12 is a flow chart for explaining the operation of the processing circuit 16 of the embodiment shown in FIGS. 9 and 10.

[Explanation of symbols]

 1,37 Radio receiver 2 Antenna 3,3a Electronic tuner 4,4a High frequency amplification circuit 5,5a Mixing circuit 6,6a Phase lock frequency synthesizer 7,7a Intermediate frequency amplification circuit 8,8a Demodulation circuit 10 Mute circuit 11 Low frequency amplification Circuit 12 Speaker 14 Control circuit 16 Processing circuit 20, 20a Reference frequency oscillation circuit 21, 21a Frequency divider circuit 22, 22a Phase comparison circuit 23, 23a Low pass filter 24, 24a Voltage control type oscillation circuit 28 Digital / analog conversion circuit 32 Changeover switch M1, M2, M2a memory

Claims (2)

[Claims] 1. An output of a voltage control type oscillation circuit is applied to a frequency dividing circuit which divides a frequency by a variable frequency division ratio, and an output of this frequency dividing circuit and an output of a reference frequency oscillation circuit are applied to a phase comparison circuit to obtain a phase difference. It is equipped with a phase-locked loop frequency synthesizer that matches the phase difference between the output of the voltage controlled oscillator and the output of the reference frequency oscillator. , An electronic tuner for receiving the frequency corresponding to the output frequency of the voltage controlled oscillator circuit, a voltage output means, and a voltage controlled type corresponding to the frequency to be received by changing the electronic tuner when changing the receiving frequency of the electronic tuner. A voltage which is approximately equal to the voltage to be applied to the oscillator circuit is generated by the voltage output means and applied to the voltage controlled oscillator circuit, and the frequency to be changed and received is the same. Operating the corresponding division ratio so as to divider circuit, then the radio receiver, characterized in that it comprises a control means for providing switching the output of the phase comparator to a voltage control type oscillator circuit. 2. The output of the first voltage control type oscillation circuit is applied to a first frequency dividing circuit which divides the frequency with a variable frequency division ratio, and the output of the first frequency dividing circuit and the output of the first reference frequency oscillation circuit are provided. The voltage corresponding to the phase difference is output to the first phase comparison circuit, and the voltage output is applied to the first voltage control type oscillation circuit, whereby the output of the first voltage control type oscillation circuit and the first reference frequency oscillation circuit. Of the first voltage-controlled oscillation circuit, which includes a first phase-locked loop frequency synthesizer having a phase difference with the output of the first voltage-controlled oscillation circuit, and a first electronic tuner for receiving a frequency corresponding to the output frequency of the first voltage-controlled oscillation circuit. The output is given to a second frequency dividing circuit which divides the frequency by a variable frequency dividing ratio, and the output of the second frequency dividing circuit and the output of the second reference frequency oscillating circuit are given to the second phase comparing circuit to cope with the phase difference. Voltage is output, and the voltage output is the second voltage control type A second phase-locked loop frequency synthesizer in which the phase difference between the output of the second voltage-controlled oscillator circuit and the output of the second reference-frequency oscillator circuit is equalized. When changing the reception frequency of the second electronic tuner that receives the frequency corresponding to the output frequency and the first electronic tuner, the first electronic tuner changes the first frequency that corresponds to the frequency to be received.
A voltage substantially equal to the voltage to be applied to the voltage controlled oscillator circuit is set to the frequency division ratio of the second frequency divider circuit to generate the output of the second phase comparator circuit, which is applied to the first voltage controlled oscillator circuit. Control means for operating the first frequency dividing circuit so that the frequency dividing ratio is changed to correspond to the frequency to be received, and then switching the output of the first phase comparison circuit to the first voltage controlled oscillator circuit; Radio receiver characterized by including.