JPH0722941A - Clock regenerating device - Google Patents
Clock regenerating deviceInfo
- Publication number
- JPH0722941A JPH0722941A JP5068001A JP6800193A JPH0722941A JP H0722941 A JPH0722941 A JP H0722941A JP 5068001 A JP5068001 A JP 5068001A JP 6800193 A JP6800193 A JP 6800193A JP H0722941 A JPH0722941 A JP H0722941A
- Authority
- JP
- Japan
- Prior art keywords
- clock
- output
- edge
- input data
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000001172 regenerating effect Effects 0.000 title 1
- 238000011084 recovery Methods 0.000 claims description 15
- 230000008929 regeneration Effects 0.000 claims 1
- 238000011069 regeneration method Methods 0.000 claims 1
- 230000000630 rising effect Effects 0.000 abstract description 12
- 102100040844 Dual specificity protein kinase CLK2 Human genes 0.000 abstract description 5
- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 abstract description 5
- 230000003111 delayed effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 9
- 230000002265 prevention Effects 0.000 description 9
- 101001122448 Rattus norvegicus Nociceptin receptor Proteins 0.000 description 6
- 238000001514 detection method Methods 0.000 description 5
- 230000007704 transition Effects 0.000 description 5
- 238000003708 edge detection Methods 0.000 description 3
- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 description 1
- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 description 1
- 239000011435 rock Substances 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/14—Preventing false-lock or pseudo-lock of the PLL
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Measuring Phase Differences (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はクロック再生装置に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock recovery device.
【０００２】[0002]
【従来の技術】クロック再生回路は、例えばＭＳＫデモ
ジュレータにおいて使用される。従来のクロック再生回
路を図６に示す。ＭＳＫデモジュレータの遅延検波回路
から出力された検波結果としての、例えば１．２ｋＨｚ
または１．８ｋＨｚの周波数情報をフレームごとにＨｉ
ｇｈ（“１”）またはＬｏｗ（“０”）で示す（１．２
ｋＨｚが“１”、１．８ｋＨｚが“０”）ＲＤＡＴＡ
は、エッジ検出回路１に入力され、その立上りと立下り
とが検出される。ＦＡＳＴ／ＳＬＯＷコントロール回路
２は、カウンタ３の出力ＲＣＬＫのエッジがＲＤＡＴＡ
のエッジに同期するようにカウンタ３のカウント数を制
御する。Clock recovery circuits are used, for example, in MSK demodulators. A conventional clock recovery circuit is shown in FIG. For example, 1.2 kHz as the detection result output from the differential detection circuit of the MSK demodulator.
Or frequency information of 1.8 kHz is set for Hi for each frame.
Shown by gh (“1”) or Low (“0”) (1.2
"1" for kHz and "0" for 1.8 kHz) RDATA
Is input to the edge detection circuit 1 and its rising and falling edges are detected. In the FAST / SLOW control circuit 2, the edge of the output RCLK of the counter 3 is RDATA.
The count number of the counter 3 is controlled so as to be synchronized with the edge of.
【０００３】[0003]
【発明が解決しようとする課題】上述のクロック再生回
路においては、入力データ、すなわち遅延検波回路から
のＲＤＡＴＡにおける“１”のフレーム幅と“０”のフ
レーム幅とが同等である限りは、ＲＣＬＫはＲＤＡＴＡ
に対してロック状態になり、全く問題は生じない。In the above clock recovery circuit, as long as the input data, that is, the frame width of "1" and the frame width of "0" in RDATA from the differential detection circuit are equal, Is RDATA
It will be locked and no problem will occur.
【０００４】しかしながら、遅延検波回路中で用いられ
ているアナログ回路の持つオフセット等の影響でＲＤＡ
ＴＡにおける“１”のフレーム幅と“０”のフレーム幅
とが異なることがある。このようなときは、ＦＡＳＴ／
ＳＬＯＷコントロール回路２が例えばカウンタ３のカウ
ント数をＦＡＳＴ→同期→ＳＬＯＷ→同期→ＦＡＳＴ…
というように制御するので、いわゆるフォールスロック
（ＦＡＬＳＥ ＬＯＣＫ）状態に陥ってしまい、ＲＣＬ
ＫはＲＤＡＴＡのエッジに追いつことができない（すな
わち、ＲＣＬＫのエッジはＲＤＡＴＡのエッジにロック
しない）。However, RDA is affected by the offset and the like of the analog circuit used in the differential detection circuit.
The frame width of "1" and the frame width of "0" in TA may be different. In such a case, FAST /
For example, the SLOW control circuit 2 changes the count number of the counter 3 to FAST → synchronization → SLOW → synchronization → FAST ...
Since it is controlled like this, it falls into the so-called false lock (FALSE LOCK) state, and RCL
K cannot catch the edge of RDATA (ie, the edge of RCLK does not lock to the edge of RDATA).
【０００５】そこで本発明は以上のような問題を解消
し、入力データの“１”と“０”のフレーム幅が異なっ
たとしてもＦＡＬＳＥ ＬＯＣＫしないクロック再生装
置を提供することを目的とする。SUMMARY OF THE INVENTION It is an object of the present invention to solve the above problems and to provide a clock reproducing apparatus which does not FALSE LOCK even when the frame widths of "1" and "0" of input data are different.
【０００６】[0006]
【課題を解決するための手段】本発明は、再生クロック
を発生する再生クロック発生手段と、該再生クロック発
生手段からの再生クロックのエッジが入力データのエッ
ジにロックするように前記再生クロック発生手段を制御
する制御手段とを有するクロック再生装置において、前
記再生クロックの２分周クロックを作成する２分周手段
と、前記再生クロックの前半周期の中心において前記２
分周クロックと前記入力データとの排他的論理和を出力
する第１手段と、前記再生クロックの後半周期の中心に
おいて前記２分周クロックと前記入力データとの排他的
論理和を出力する第２手段と、前記第１手段の出力およ
び第２手段の出力が所定の関係になるまで前記入力デー
タのエッジに対して前記再生クロック発生手段における
再生クロックのエッジ位置を一方的に進ませるかまたは
遅らせるように前記制御手段を制御する手段とを具えた
ことを特徴とする。According to the present invention, there is provided a regenerated clock generating means for generating a regenerated clock, and the regenerated clock generating means for locking the edge of the regenerated clock from the regenerated clock generating means to the edge of input data. In the clock recovery device having a control means for controlling the clock, the frequency division means for generating a frequency-divided clock of the reproduction clock and the center of the first half cycle of the reproduction clock are
First means for outputting an exclusive OR of the divided clock and the input data; and second means for outputting an exclusive OR of the divided clock by 2 and the input data at the center of the second half cycle of the reproduction clock. Means and the output of the first means and the output of the second means have a predetermined relationship with each other, the edge position of the reproduction clock in the reproduction clock generating means is unilaterally advanced or delayed with respect to the edge of the input data. And a means for controlling the control means.
【０００７】[0007]
【作用】本発明によれば、入力データの“１”と“０”
のフレーム幅が異なっても強制引込みによってＦＡＬＳ
Ｅ ＬＯＣＫせずに入力データに追随した再生クロック
が得られるようになる。According to the present invention, "1" and "0" of input data
FALS even if the frame width of the
A reproduced clock that follows input data can be obtained without E LOCK.
【０００８】[0008]
【実施例】以下、図面を参照して本発明の実施例を詳細
に説明する。Embodiments of the present invention will now be described in detail with reference to the drawings.
【０００９】図１は本発明の実施例にかかるクロック再
生回路のブロック図である。１はエッジ検出回路、２１
はＦＡＳＴ／ＳＬＯＷコントロール回路、３１はカウン
タ、４１はＦＡＬＳＥ ＬＯＣＫ防止回路である。図２
は本クロック再生回路の詳細を示す。図３はＦＡＬＳＥ
ＬＯＣＫ防止回路の動作を示す。FIG. 1 is a block diagram of a clock recovery circuit according to an embodiment of the present invention. 1 is an edge detection circuit, 21
Is a FAST / SLOW control circuit, 31 is a counter, and 41 is a FALSE LOCK prevention circuit. Figure 2
Shows the details of this clock recovery circuit. Figure 3 is FALSE
The operation of the LOCK prevention circuit is shown.
【００１０】図２に示すように、カウンタ３１の出力Ｉ
ＮＩＴＮは、ＲＣＬＫの１周期ごとに発生し、ＦＡＬＳ
Ｅ ＬＯＣＫ防止回路４１中のフリップフロップ（以下
“ＦＦ”ともいう）Ｆ１〜Ｆ４を初期化する。これによ
って、ＲＣＬＫの１周期ごとに初期化されて、Ｆ１の反
転Ｑ出力（反転Ｑ１），Ｆ２の反転Ｑ出力（反転Ｑ
２），Ｆ３のＱ出力（Ｑ３）は“１”（Ｈｉｇｈ）に、
Ｆ４のＱ出力（Ｑ４）は“０”（Ｌｏｗ）になる。ＦＡ
ＬＳＥ ＬＯＣＫ防止回路４１中のフリップフロップＦ
５のＱ出力としてのＣＫ６００は、反転ＲＣＬＫを２分
周したクロック（本例ではＲＣＬＫの立下りで変化す
る）であり、ＥＸ−ＯＲ１で示すＥＸＣＬＵＳＩＶＥ−
ＯＲゲートの出力ＸＯＲ１はＣＫ６００と遅延検波回路
からのＲＤＡＴＡＩとの排他的論理和出力である。ＥＸ
−ＯＲ２の出力としてのＣＬＫ１はＲＣＬＫの前半周期
の中心と後半周期の中心におけるＸＯＲ１の値をＦ１，
Ｆ２にサンプルするためのクロックであり、ＮＡＮＤゲ
ートＮＡＮＤ１の出力としてのクロックＣＬＫ２は、Ｃ
ＬＫ１によりＦ１，Ｆ２にサンプルされた２ビットデー
タ（ＸＯＲ１の値）をＦ３，Ｆ４にパラレルロードす
る。すなわち、ＣＬＫ２の立上りによって、Ｆ３のＱ出
力（Ｑ３）にはＲＯＣＫの後半周期の中心におけるＸＯ
Ｒ１の値が、Ｆ４のＱ出力（Ｑ４）にはＲＣＬＫの前半
周期の中心におけるＸＯＲ１の値が各々得られ、これら
の２つのＸＯＲ１の値が入力されたＥＸ−ＯＲ３の出力
ＦＬＯＣＫＮが“１”のときは本クロック再生回路が正
常ロック状態であることを示し、“０”のときは本クロ
ック再生回路がＦＡＩＬ ＬＯＣＫ状態であることを示
す。As shown in FIG. 2, the output I of the counter 31
NITN is generated in each cycle of RCLK, and FALS
Flip-flops (hereinafter also referred to as “FF”) F1 to F4 in the E LOCK prevention circuit 41 are initialized. As a result, it is initialized every one cycle of RCLK, and the inverted Q output of F1 (inverted Q1) and the inverted Q output of F2 (inverted Q output).
2), the Q output (Q3) of F3 becomes "1" (High),
The Q output (Q4) of F4 becomes "0" (Low). FA
Flip-flop F in LSE LOCK prevention circuit 41
CK600 as the Q output of 5 is a clock obtained by dividing the inverted RCLK by two (changes at the falling edge of RCLK in this example), and EXCLUSIVE-indicated by EX-OR1.
The output XOR1 of the OR gate is an exclusive OR output of CK600 and RDATAI from the differential detection circuit. EX
CLK1 as the output of OR2 has the value of XOR1 at the center of the first half cycle and the center of the second half cycle of RCLK as F1,
The clock CLK2, which is a clock for sampling to F2 and is an output of the NAND gate NAND1, is C
The 2-bit data (value of XOR1) sampled by F1 and F2 by LK1 is parallel loaded to F3 and F4. That is, due to the rising edge of CLK2, the Q output (Q3) of F3 has XO at the center of the latter half cycle of ROCK.
The value of R1 is the value of XOR1 at the center of the first half cycle of RCLK at the Q output of F4 (Q4), and the output FLOCKN of EX-OR3 to which these two values of XOR1 are input is "1". When this is "0", this clock recovery circuit is in the normal lock state, and when it is "0", this clock recovery circuit is in the FAIL LOCK state.
【００１１】図３の（ａ）は、以上の各タイミングを示
しており、同（ｂ）はＲＣＬＫとその２分周クロックで
あるＣＫ６００と、このＣＫ６００との間でＣＬＫ２の
立上りのタイミングで排他的論理和出力（ＸＯＲ１）を
得るためのＲＤＡＴＡＩのエッジの各位置〜との関
係を示しており、同（ｃ）はＲＤＡＴＡＩのエッジが各
位置〜にある場合におけるＱ３およびＱ４の値の排
他的論理和の真理値表を示す。すなわち、この排他的論
理和（ＥＸ−ＯＲ３の出力）が“０”のときはＦＡＬＳ
Ｅ ＬＯＣＫ状態（図３（ａ）のＣＬＫ２Ａのタイミン
グがこの状態を示しており、ＲＣＬＫの立上りエッジが
ＲＤＡＴＡＩの立上りエッジに一致していない。同様に
図４の（ｂ）もＦＡＬＳＥ ＬＯＣＫ状態を示す）であ
り、このとき、本クロック再生回路は強制引込み状態に
遷移する。また、“１”のときは正常クロック状態（図
４の（ａ））である。FIG. 3 (a) shows each of the above timings, and FIG. 3 (b) shows RCLK and its divided clock CK600, and the CLK600 rising edge exclusive between CLK600 and this CK600. Shows the relationship between each position of the edge of RDATAI to obtain the logical OR output (XOR1). The same (c) shows the exclusive values of Q3 and Q4 when the edge of RDATAI is at each position of. The truth table of the logical sum is shown. That is, when this exclusive OR (output of EX-OR3) is "0", FALS
The E LOCK state (the timing of CLK2A in FIG. 3A shows this state, and the rising edge of RCLK does not match the rising edge of RDATAI. Similarly, FIG. 4B also shows the FALSE LOCK state. ) At this time, the clock recovery circuit makes a transition to the forced pull-in state. Further, when it is "1", it is a normal clock state ((a) of FIG. 4).
【００１２】ＦＡＬＳＥ ＬＯＣＫ防止回路４１はＦ６
からＲＤＡＴＡとＲＣＬＫとの位相差を検出した信号Ｓ
Ｌ２，ＦＡ２を出力し、これらをＦＡＳＴ／ＳＬＯＷコ
ントロール回路２１に与える。The FALSE LOCK prevention circuit 41 is F6.
Signal S that detects the phase difference between RDATA and RCLK from
It outputs L2 and FA2 and supplies them to the FAST / SLOW control circuit 21.
【００１３】以上の構成によれば、ＦＡＬＳＥ ＬＯＣ
Ｋ防止回路４１は、ＲＣＬＫの立上りでＦ１〜Ｆ４が初
期化され、Ｑ３が“１”、Ｑ４が“０”になって、必ず
通常引込み状態に遷移し、ＣＬＫ２の立上りでＱ３／Ｑ
４が１／０または０／１ならば、ＦＬＯＣＫＮは１のま
まなので、強制引込み状態には遷移しない。ＣＬＫ２の
立上りでＱ３／Ｑ４が１／１または０／０ならば、ＦＬ
ＯＣＫＮは０となるので、強制引込み状態に遷移し、Ｆ
ＡＳＴ／ＳＬＯＷコントロール回路２１はＦＡＬＳＥ
ＬＯＣＫ防止回路４１からのＳＬ２，ＦＡ２の値に基づ
いて、次のＲＣＬＫの立上りまで、カウンタ３１を強制
的にＳＬＯＷ制御またはＦＡＳＴ制御し、Ｑ３／Ｑ４が
１／０または０／１になるまでこの強制引込み状態を継
続する。According to the above configuration, the FALSE LOC
In the K prevention circuit 41, F1 to F4 are initialized at the rising edge of RCLK, Q3 is set to "1", Q4 is set to "0", and a transition is always made to the normal pull-in state.
If 4 is 1/0 or 0/1, FLOCKN remains 1, so the state does not transition to the forced pull-in state. If Q3 / Q4 is 1/1 or 0/0 at the rising edge of CLK2, FL
Since OCKN becomes 0, it transits to the forced pull-in state and F
AST / SLOW control circuit 21 is FALSE
Based on the values of SL2 and FA2 from the LOCK prevention circuit 41, the counter 31 is forcibly SLOW-controlled or FAST-controlled until the next rise of RCLK, and this is maintained until Q3 / Q4 becomes 1/0 or 0/1. Continue the forced pull-in state.
【００１４】なお、以上の説明は、ＣＫ６００がＲＣＬ
Ｋの立下りで変化するように回路構成した場合における
ものであるが、ＣＫ６００がＲＣＬＫの立上りで変化す
るように回路構成することもできる。この場合は、図５
に示すように、ＣＫ６００とＲＤＡＴＡＩとの排他的論
理和であるＱ３とＱ４の値、すなわちＱ３／Ｑ４が１／
０または０／１のときにＦＡＬＳＥ ＬＯＣＫ状態であ
るので、ＦＬＯＣＫＮ＝１に基づいて強制引込みに遷移
させればよく、Ｑ３／Ｑ４が０／０または１／１のとき
は通常引込み状態に遷移させればよい。In the above description, CK600 is RCL.
Although the circuit configuration is such that it changes at the falling edge of K, it is also possible to configure the circuit so that CK600 changes at the rising edge of RCLK. In this case,
As shown in, the value of Q3 and Q4, which is the exclusive OR of CK600 and RDATAI, that is, Q3 / Q4 is 1 /
When it is 0 or 0/1, it is in the FALSE LOCK state, so it is sufficient to make a transition to forced pull-in based on FLOCKN = 1, and when Q3 / Q4 is 0/0 or 1/1, make a transition to the normal pull-in state. Just do it.
【００１５】[0015]
【発明の効果】以上説明したように本発明によれば入力
データの“１”と“０”のフレーム幅が異なってもＦＡ
ＬＳＥ ＬＯＣＫしないクロック再生装置を提供するこ
とができる。As described above, according to the present invention, even if the frame widths of "1" and "0" of input data are different, FA
It is possible to provide a clock recovery device that does not LSE LOCK.
【図１】本発明の実施例にかかるクロック再生回路のブ
ロック図である。FIG. 1 is a block diagram of a clock recovery circuit according to an embodiment of the present invention.
【図２】同クロック再生回路の詳細を示すブロック図で
ある。FIG. 2 is a block diagram showing details of the clock recovery circuit.
【図３】（ａ）はＦＡＬＳＥ ＬＯＣＫ防止回路の動作
タイミングを示す図であり、（ｂ）はＲＣＬＫ，ＣＫ６
００と各ＲＤＡＴＡＩとの関係を示す図であり、（ｃ）
はＱ３，Ｑ４の排他的論理和の真理値を示す図である。3A is a diagram showing an operation timing of a FALSE LOCK prevention circuit, and FIG. 3B is a diagram showing RCLK and CK6.
It is a figure which shows the relationship between 00 and each RDATAI, (c)
FIG. 6 is a diagram showing a truth value of an exclusive OR of Q3 and Q4.
【図４】（ａ）は通常クロック状態を示す図であり、
（ｂ）はＦＡＬＳＥ ＬＯＣＫ状態を示す図である。FIG. 4A is a diagram showing a normal clock state,
(B) is a diagram showing a FALSE LOCK state.
【図５】ＲＣＬＫとＣＫ６００との他の関係におけるＱ
３，Ｑ４の値とその結果に基づく制御態様を示す図であ
る。FIG. 5: Q in another relationship between RCLK and CK600
It is a figure which shows the control aspect based on the value of 3, Q4, and the result.
【図６】従来のクロック再生回路のブロック図である。FIG. 6 is a block diagram of a conventional clock recovery circuit.
Ｆ１〜Ｆ５ フリップフロップ ＥＸ−ＯＲ１〜ＥＸ−ＯＲ３ ＥＸＣＬＵＳＩＶＥ Ｏ
Ｒゲート １ エッジ検出回路 ２１ ＦＡＳＴ／ＳＬＯＷコントロール回路 ３１ カウンタ ４１ ＦＡＬＳＥ ＬＯＣＫ防止回路F1 to F5 flip-flops EX-OR1 to EX-OR3 EXCLUSIVE O
R gate 1 Edge detection circuit 21 FAST / SLOW control circuit 31 Counter 41 FALSE LOCK prevention circuit
Claims (1)
生手段と、該再生クロック発生手段からの再生クロック
のエッジが入力データのエッジにロックするように前記
再生クロック発生手段を制御する制御手段とを有するク
ロック再生装置において、 前記再生クロックの２分周クロックを作成する２分周手
段と、 前記再生クロックの前半周期の中心において前記２分周
クロックと前記入力データとの排他的論理和を出力する
第１手段と、 前記再生クロックの後半周期の中心において前記２分周
クロックと前記入力データとの排他的論理和を出力する
第２手段と、 前記第１手段の出力および第２手段の出力が所定の関係
になるまで前記入力データのエッジに対して前記再生ク
ロック発生手段における再生クロックのエッジ位置を一
方的に進ませるかまたは遅らせるように前記制御手段を
制御する手段とを具えたことを特徴とするクロック再生
装置。1. A reproduction clock generating means for generating a reproduction clock, and a control means for controlling the reproduction clock generating means so that an edge of the reproduction clock from the reproduction clock generating means is locked to an edge of input data. In a clock recovery device, a frequency division means for generating a frequency-divided clock of the reproduction clock, and an exclusive OR of the frequency-divided clock and the input data at the center of the first half cycle of the reproduction clock. 1 means, 2nd means for outputting the exclusive OR of the divided clock by 2 and the input data at the center of the latter half cycle of the reproduced clock, and the output of the 1st means and the output of the 2nd means are predetermined. Until the above relationship is satisfied, the edge position of the reproduced clock in the reproduced clock generating means is unidirectionally advanced with respect to the edge of the input data. Clock regeneration apparatus is characterized in that and means for controlling said control means so as Luke or delay.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5068001A JP2810288B2 (en) | 1993-03-26 | 1993-03-26 | Clock recovery device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5068001A JP2810288B2 (en) | 1993-03-26 | 1993-03-26 | Clock recovery device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0722941A true JPH0722941A (en) | 1995-01-24 |
| JP2810288B2 JP2810288B2 (en) | 1998-10-15 |
Family
ID=13361216
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5068001A Expired - Lifetime JP2810288B2 (en) | 1993-03-26 | 1993-03-26 | Clock recovery device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2810288B2 (en) |
-
1993
- 1993-03-26 JP JP5068001A patent/JP2810288B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP2810288B2 (en) | 1998-10-15 |
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