JPH07235594A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] Even when a contact hole is formed using the self-alignment method, the thin etching stopper film that protects the electrodes is not etched, so that the electrodes are not short-circuited via the aluminum wiring and the yield and A method of manufacturing a semiconductor device having improved reliability is obtained. [Structure] After forming an etching stopper film on the entire surface including a contact hole that is open to the middle, anisotropic etching is performed by leaving the side surface of the etching stopper film.
1a, 11b are formed, and the second sidewall 11a,
While 11b protects the protective oxide films 5a, 5b, the first sidewalls 6b, 6c, and the first etching stopper film 8, anisotropic etching is performed to expose the semiconductor substrate 1 and form a contact hole.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device such as an IC or LSI.

[0002]

2. Description of the Related Art A process for manufacturing a semiconductor device includes a number of processes such as a process for forming elements on a semiconductor substrate and a process for interconnecting these devices. A wiring layer for connecting the element is provided with a contact hole for connecting with the element, and then a layer of aluminum, polycrystalline silicon, or the like is formed, and the wiring layer and the element are connected through the contact hole. It is formed by connecting and patterning the wiring layer into predetermined wiring. Therefore, it is important to properly provide the contact hole at a predetermined position for proper wiring.

By the way, since the pattern size has been miniaturized with the high integration of semiconductor devices in recent years, the margin for misalignment in photolithography for forming contact holes has decreased. That is,
If the mask for forming the contact hole is displaced from the predetermined position due to a slight misalignment, the gate or wiring of the transistor may be cut during the formation of the contact hole, or the insulating layer may be removed even if it is not cut. The wires are exposed, shorting them out.

Therefore, a self-alignment method has been proposed as a method for obtaining a margin when forming a contact hole in a manufacturing process of a semiconductor device having an extremely high degree of integration. This self-alignment method is often used in combination with flattening by etching back.

FIG. 13 is a diagram for explaining a method of forming a contact hole by a conventional flattening self-alignment method. The figure shows a partial cross-sectional structure of the semiconductor device. In the figure, 1 is a semiconductor substrate, 2 is an element isolation region formed on the semiconductor substrate 1, 3 is a gate oxide film, 4a and 4b are gate electrodes formed on the gate oxide film 3, and 5a and 5b are gates. Protective films formed on the electrodes 4a and 4b, 6a to 6d are sidewalls provided on the side surfaces of the gate electrodes 4a and 4b and the protective films 5a and 5b, and 7
Is the semiconductor substrate 1, the element isolation region 2, the protective films 5a and 5
b, an oxide film 8 provided on the sidewalls 6a to 6d, 8 is an etching stopper film formed on the oxide film 7 for suppressing the progress of etching, and is made of a nitride film or polycrystalline silicon. Become. 9 is an interlayer film formed on the etching stopper film 8 and 16 is an interlayer film 9
Is a resist pattern which is applied on top of and is formed into a predetermined pattern.

Here, a material having a high selection ratio is used for the etching stopper film 8. That is, the nitride film or the polycrystalline silicon film, which is the etching stopper film 8, is dry-etched, compared to the interlayer film 9, which is an interlayer film.
In either case of wet etching, it is difficult to be etched.

Next, a method of forming a contact hole will be described with reference to FIG. First, the oxide film 7 and the etching stopper film 8 are formed on the element formed on the semiconductor substrate 1, and the interlayer film 9 is further stacked. After that, the interlayer film 9 is flattened by etching back by reactive ion etching (hereinafter referred to as RIE).

Further, RIE is anisotropic etching performed while applying a high frequency electric field to ions. Unlike etching by sputtering, it has a feature that side etching rarely occurs. RIE
Is different from isotropic so-called wet etching,
It is anisotropic etching.

Next, a photoresist is applied on the flattened interlayer film 9 and patterned to form a resist pattern 16. In the self-alignment method, the diameter d'of the opening of the resist pattern 16 is slightly larger than the diameter d of the contact hole to be formed. The reason for this will be described later. The state at this time is shown in FIG.

Next, etching is performed using the resist pattern 16 as a mask. The etching at this time is performed by RIE which is anisotropic etching. Over-etching is performed so that the semiconductor substrate 1 is exposed to form the contact holes. Here, the resist pattern 16
Since the diameter d'of the opening is larger than the diameter d of the contact hole, the inclined portions 14a and 14b of the etching stopper film 8 are exposed first when the etching is advanced.

Since RIE is reactive etching,
It has some selectivity based on the difference in the material of the portion to be etched. Therefore, the gate electrodes 4a, 4
The etching stopper film 8 of the inclined portions 14a and 14b for protecting b is not much etched, but the interlayer film 9 is etched. Then, the interlayer film 9 within the range of the diameter d'of the opening of the resist pattern is completely removed. Then, by further anisotropically etching by RIE, the etching stopper film 8 of the flat portion 15 is removed, and a contact hole having a diameter d is opened. On the other hand, since the etching stopper film 8 of the inclined portions 14a and 14b is inclined, it is not completely removed, and a part thereof remains (FIG. 13B). This is because when the etching stopper film 8 has a thickness of t and the etching stopper film 8 of the flat portion 15 is removed by anisotropic etching RIE, the inclined portions 14a and 14b are also anisotropically etched by t. Since the thickness of the etching stopper film 8 in the etching direction is larger than t,
This is because it is not completely removed (Fig. 1
5).

As described above, according to the self-alignment method, the etching stopper film 8 of the inclined portions 14a and 14b is formed.
In order to protect the gate electrodes 4a and 4b, even if the resist film 16 having an opening having a diameter d'which is larger than the diameter d of the contact hole is used, only the flat portion 15 is opened to form a contact hole having a diameter d. be able to. Therefore, even if the resist film 16 is slightly misaligned (x in the figure) as shown in FIG.
A contact hole having a predetermined diameter d is obtained, the margin for photolithography is improved, and the yield is improved.

[0013]

In the conventional method of manufacturing a semiconductor device, in order to form the contact hole having the diameter d, the interlayer film 9 is removed and only the flat portion 15 of the etching stopper film 8 is etched by etching. It is desirable to remove the topper film 8 while not completely removing the etching stopper film 8 of the inclined portions 14a and 14b in order to protect the gate electrodes 4a and 4b. Therefore, it is preferable that the etching rate in the inclined portions 14a and 14b be lower than the etching rate of the interlayer film 9 in accordance with the difference in material, and the higher the selection ratio between the etching stopper film 8 and the interlayer film 9 is. Good.

Here, a material having a high selection ratio is used for the etching stopper film 8, and the nitride film or the polycrystalline silicon film which is the etching stopper film 8 is dry-etched more than the interlayer film 9 which is the interlayer film. In both cases, wet etching has the property of being difficult to be etched. However, in the case of wet etching with hydrofluoric acid or the like, the ratio of etching of the oxide film to the silicon nitride film (selection ratio) is 100 or more, whereas in the case of dry etching using a gas such as CH ₂ F _2, Is 5 to 2
The dry etching selectivity is inferior to that of the wet etching. As described above, the RIE has some selectivity, but since the selection ratio is small, the sloped portion 1
4a, 14b etching stopper film 8, oxide film 5
Etching also progresses on a and 5b and the oxide film side walls 6b and 6c. When the etching stopper film 8 is thin, the resist film 16 and the gate electrodes 4a and 4b
The etching stopper film 8 is also removed by etching when the interlayer film 9 is etched depending on the positional relationship with the gate electrode 4 as shown in FIG. 14 (b).
A and 4b may be exposed. In this state, the flat portion 15
When the etching stopper film 8 is removed to form a contact hole, the gate electrodes 4a and 4b are short-circuited via the aluminum wiring and the normal operation is stopped.

In order to prevent such a problem, the etching stopper film 8 is thickened and the protective film 5 is formed.
It is conceivable to increase the film thicknesses of a, 5b and the oxide film side walls 6a to 6d. However, in this case, although the gate electrodes 4a and 4b can be prevented from being exposed, on the other hand, the step difference on the surface becomes so large that planarization becomes difficult and a process problem occurs.

As described above, since the etching stopper film 8, the protective films 5a and 5b and the oxide film sidewalls 6b and 6c of the inclined portions 14a and 14b are etched by the dry etching having a low selection ratio, the gate electrodes are etched. There is a problem that parts of 4a and 4b are exposed and short-circuited due to the wiring, which lowers the yield and reliability of the semiconductor device.

The present invention has been made in order to solve the above problems, and prevents the etching of the portion protecting the electrode from proceeding even when the contact hole is formed by the self-alignment method, An object of the present invention is to provide a method for manufacturing a semiconductor device, which can improve the yield and reliability of the semiconductor device.

[0018]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: a first step of forming a second etching stop layer on an insulating layer; and an anisotropic method based on a predetermined resist pattern. Anisotropic etching after removing the second etching stop layer by reactive etching and removing a part of the insulating layer to form an opening, and forming a third etching stop layer on the entire surface. A third step of removing the third etching stop layer on a portion other than the side surface of the opening by etching to form a side surface etching stop layer, and the remaining portion of the insulating layer in the opening and the first step. A fourth step of removing the etching stop layer and exposing the semiconductor substrate.

A method of manufacturing a semiconductor device according to claim 2 is
A first step of forming a second etching stop layer overlying the insulating layer, and removing the second etching stop layer by anisotropic etching based on a predetermined resist pattern, and part of the insulating layer. Is removed to form an opening, and a third etching stop layer is formed on the entire surface, and then the third etching stop layer is removed by anisotropic etching except the side surface of the opening. A third step of forming a side surface etching stop layer, and a fourth step of exposing the semiconductor substrate by removing the remaining portion of the insulating layer in the opening and the first etching stop layer by anisotropic etching. Be prepared.

A method of manufacturing a semiconductor device according to claim 3 is
A first step of forming a first side surface etching stop layer by removing a portion other than the side surface of the electrode by anisotropic etching after forming the first etching stop layer; A second step of forming an insulating layer, a third step of forming a second etching stopper layer on the insulating layer, and an anisotropic etching based on a predetermined resist pattern to prevent the second etching stopper. The fourth step of removing the layer and removing a part of the insulating layer to form an opening, and the third etching stop layer is formed on the entire surface, and then anisotropic etching is performed to remove parts other than the side surface of the opening. Removing a portion of the third etch stop layer from the second
And a sixth step of exposing the semiconductor substrate by removing the remaining portion of the insulating layer in the opening by isotropic etching for selectively removing the insulating layer. And a process.

A method of manufacturing a semiconductor device according to claim 4 is
The first step of etching back the insulating layer until the first etching stop layer on the electrode is exposed, and the second etching stop layer is formed on the entire surface, and then anisotropic etching is performed based on a predetermined resist pattern. A second step of removing the second etching stop layer to provide an opening, and a third step of exposing the semiconductor substrate by removing the remaining portion of the insulating layer in the opening and the first etching stop layer by etching. And the process of.

[0022]

In the first aspect of the invention, the side surface etching stop layer formed on the side surface of the insulating layer protects the first etching stop layer so that the electrode is not exposed during etching.

According to the second aspect of the present invention, the first etching stop layer is removed while the side surface etching stop layer formed on the side surface of the insulating layer protects the electrode from being exposed during anisotropic etching. To do.

According to the third aspect of the present invention, the first side surface etching stop layer protects the electrode and the second side surface etching stop layer protects the electrode during the isotropic etching for selectively removing the insulating layer. Protect layers.

In the invention of claim 4, the second etching stop layer protects the first etching stop layer so that the electrode is not exposed during etching.

[0026]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a partial cross section of a semiconductor device manufactured based on the method of manufacturing a semiconductor device according to this embodiment. In the figure, 1 is a semiconductor substrate, 2 is an element isolation region arranged on the semiconductor substrate 1, 3 is a gate oxide film, 4
a and 4b are gate electrodes formed on the gate oxide film 3,
Reference numerals 5a and 5b are protective films formed on the gate electrodes 4a and 4b, and 6a to 6d are gate electrodes 4a and 4b and the protective film 5.
The first sidewalls 7 made of an oxide film provided on the side surfaces of a and 5b are provided on the semiconductor substrate 1, the element isolation region 2, the protective films 5a and 5b, and the first sidewalls 6a to 6d. The oxide film 8 is formed of a nitride film or polycrystalline silicon on the oxide film 7, and is a first etching stopper film 9 for suppressing the progress of etching.
Is an interlayer film formed on the first etching stopper film 8, 10 is a second etching stopper film formed on the interlayer film 9, and 11a and 11b are side surfaces of an opening provided in the interlayer film 9. It is the formed second sidewall.

2 to 5 are views for explaining a method of manufacturing a semiconductor device according to this embodiment. Figure 2
5 to FIG. 5 show a series of manufacturing steps in four drawings for convenience, and show these continuous steps.

Next, referring to FIG. 2 for the following steps A to C, FIG. 3 for steps D to F, FIG. 4 for steps G to I, and FIG. 5 for step J, respectively. A method of manufacturing the semiconductor device of this embodiment will be described.

Step A: A device isolation region 2 is formed on a semiconductor substrate 1, an oxide film for forming a gate oxide film 3 is then deposited, and a polycrystalline film for forming gate electrodes 4a and 4b is formed thereon. A silicon layer is deposited, and an oxide film for forming protective films 5a and 5b is further stacked. Then, a resist pattern (not shown) is formed on them, and etching is performed using this resist pattern as a mask to form a predetermined pattern of the gate oxide film 3, the gate electrodes 4a and 4b, and the protective film 5.
a and 5b are formed (FIG. 2 (a)).

Step B In order to protect the gate electrodes 4a and 4b formed in Step A, first side walls 6a to 6d made of an oxide film are formed (FIG. 2 (b)). That is, after forming an oxide film (not shown) on the entire surface, RIE which is anisotropic etching
The gate electrodes 4a and 4b and the protective films 5a and 5b are removed by removing portions other than the side surfaces.

Step C: An oxide film 7 for insulation is deposited on the entire surface, and on top of that,
An etching stopper film 8 made of a nitride film is deposited to protect the lower layer from etching, and an interlayer film 9 is further deposited (FIG. 2 (c)).

Step D The surface of the interlayer film 9 formed in Step C is not flat due to the unevenness due to the pattern formed thereunder. Therefore, etching back is performed using RIE to flatten the surface of the interlayer film 9. This etch back is performed so that the interlayer film 9 remains on the first etching stopper film 8 in the portion above the gate electrode 4a (the portion 21 in FIG. 3D) (the first etching stopper film in the portion 21). 8) so that it is not exposed). Since the gate electrode 4a is formed on the element isolation region 2 as shown in FIG.
It is slightly higher than the gate electrode 4b.

Step E Polycrystalline silicon is deposited on the flattened interlayer film 9 in Step D to form a second etching stopper layer 10 (FIG. 3 (e)). This is to prevent the interlayer film 9 other than the contact holes from being etched in steps I and J described later.

Step F A predetermined resist pattern (not shown) for forming a contact hole is formed on the second etching stopper layer 10. Then, the interlayer film 9 is removed by etching by RIE using this pattern as a mask.
This etching is performed until part of the inclined portions 14a and 14b of the first etching stopper film 8 is exposed. Then, the resist pattern not shown is removed (FIG. 3 (f)).

Since RIE is anisotropic etching, etching is performed in the q direction in FIG.
No etching is done in the direction. Also, RIE
Has anisotropy and also has some selectivity, so that the first etching stopper film 8 of the inclined portions 14a and 14b is formed.
However, the etching does not proceed so much. This is because the exposure time is relatively short and is not affected by the sputtering of ions. Therefore, in this step, after the second etching stopper film 10 is etched, the interlayer film 9 is exclusively removed by etching, and an opening portion having a flat portion 12 (a contact hole that does not penetrate to the semiconductor substrate 1) is provided. .

Step G A third etching stopper film 22 made of polycrystalline silicon is deposited on the entire surface (FIG. 4 (g)).

Step H By etching the third etching stopper film 22 formed in Step G, the second sidewall 11 is etched.
a and 11b are formed on the side surface (including the inclined portions 14a and 14b) of the opening provided in the process F (FIG. 4 (h)).
That is, the third etching stopper film 22 formed on the entire surface is entirely etched by RIE, which is anisotropic etching, and the second sidewall 11a,
11b is formed. On the other hand, the third etching stopper film 22 of the flat portion 12 is removed. The second sidewalls 11a and 11b are formed by R in step I described later.
This is for preventing the first etching stopper film 8 of the inclined portions 14a and 14b from being side-etched by ion sputtering during etching by IE.

Step I Following step H, the interlayer film 9 in the flat portion 12 is etched by RIE so that the first stopper film 8 in the flat portion 15 is exposed (FIG. 4 (i)). .

Process J Following the process I, the flat portion 15 is further subjected to RIE.
By etching, the first stopper film 8 and the oxide film 7 of the flat portion 15 are removed, and the semiconductor substrate 1 is exposed,
A contact hole is formed (FIG. 5 (j)). At this time, the first etching stopper film 8 of the inclined portions 14a and 14b is also etched, but the second sidewall 1
1a and 11b protect the inclined portions 14a and 14b from etching, so that the first etching stopper film 8 in this portion is not completely removed, and the first sidewalls 6b and 6c are not exposed. . Therefore, the gate electrodes 4a and 4b are not exposed.

In this embodiment, in step H, the step of forming the second sidewalls 11a and 11b, and in steps I and J, the interlayer film 9, the first etching stopper film 8,
Since all the steps of etching the oxide film 7 are performed by RIE, these steps H, I, and J can be continuously performed.

As described above, according to the method of this embodiment, since the second sidewalls 11a and 11b are provided on the side surfaces of the opening when the self-alignment method is used, the interlayer film 9 is formed by dry etching. Is removed, a fine contact hole can be formed without completely removing the protective film of the gate electrodes 4a and 4b, the integration degree is improved, and the yield of the semiconductor device and the yield of the semiconductor device are prevented without short-circuiting the gate electrodes 4a and 4b. Improves reliability.

Example 2. In the above embodiment, the process is performed only by RIE which is anisotropic etching, but wet etching which is isotropic etching may be used as a part of the process. An example of this will be described below.

6 to 8 are views for explaining a method of manufacturing a semiconductor device according to the second embodiment. Figure 6
8 to 8 show a series of manufacturing steps in three drawings for the sake of convenience, and show these continuous steps.
In the figure, reference numerals 23a and 23b are first etching stopper films 24a-2, which are formed of a silicon nitride film on the gate electrodes 4a and 4b and suppress the progress of etching.
Reference numeral 4d denotes a first sidewall formed of a silicon nitride film on the side surfaces of the gate electrodes 4a and 4b to suppress the progress of etching, and 25 denotes a second etching stopper film formed of a silicon nitride film on the oxide 9. , 31 is an oxide film for forming the gate oxide film 3, 32 is polycrystalline silicon for forming a gate electrode, 33 is a silicon nitride film for forming the first etching stopper film 23, and 34 is a predetermined film. A resist pattern which is a mask for forming the gate electrodes 4a, 4b and the like of the pattern, 35 is a silicon nitride film for forming the first sidewalls 24a to 24d, and 36 is a mask for forming contact holes. A resist pattern 37 is a silicon nitride film for forming the second sidewalls 11a and 11b.

Since the semiconductor substrate 1, the gate oxide film 3, the gate electrodes 4a and 4b, the interlayer film 9 and the second sidewalls 11a and 11b are the same as those in the first embodiment, the description thereof will be omitted. .

Next, the process flow will be described in the following steps A to C.
Will be described in order with reference to FIG. 6, steps D to F with reference to FIG. 7, and steps G to I with reference to FIG.

Step A An oxide film 31 for insulating the gate is deposited on the entire surface of the semiconductor substrate 1, and a polycrystalline silicon film 32 for forming the gate electrodes 4a and 4b is deposited on the oxide film 31 and further stacked. As a result, a silicon nitride film 33 for forming the first protective films 5a and 5b is deposited. Then, a predetermined resist pattern 34 is formed on the silicon nitride film 33 (FIG. 6).
(a)).

Step B Etching is performed by RIE using the resist pattern 33 as a mask to form the gate electrodes 4a and 4b and the first etching stopper films 23a and 23b (FIG. 6).
(b)).

Step C A silicon nitride film 35 for forming the first sidewalls 24a to 24d is deposited thereon (FIG. 6 (c)).

Step D The silicon nitride film 35 formed in Step C is etched by RIE to form the first sidewalls 24a-24.
d is formed (FIG. 7D).

Step E On top of that, an interlayer film 9 is thickly deposited and flattened by etching back, and then a second etching stopper film 25 of a silicon nitride film is deposited thereon, and further overlaid with a contact hole. A resist pattern 36 corresponding to the above shape is formed (FIG. 7E).

Step F Using the resist pattern 36 formed in Step E as a mask, the first etching stopper 23a,
Etching is performed until a part of 23b (18a, 18b in FIG. 7 (f)) is exposed. Then, the resist pattern 36 is removed (FIG. 7 (f)).

Step G Next, a silicon nitride film 37 is deposited (FIG. 8G). The silicon nitride film 37 is used as the second etching stopper film 2
5 is deposited on the bottom surface 12 and the side surface of the opening provided in the interlayer film 9 in the step F.

Process H RIE etching is performed on the entire surface to form second sidewalls 11a and 11b as etching stopper films on the side walls of the opening (see FIG. 7 (h), process H of Example 1).

Step I Then, wet etching is performed with hydrofluoric acid (HF) or the like to remove the interlayer film 9 at the bottom surface 12 of the opening provided in the step F to expose the semiconductor substrate 1. This opens the contact hole (FIG. 7 (i)). The selection ratio in the case of wet etching with hydrofluoric acid or the like used here is 100 or more, which is higher than the selection ratio (5 to 20) in the case of dry etching using a gas such as CH ₂ F ₂ .

As described above, according to the method of this embodiment, when the self-alignment method is used, the second sidewalls 11a and 11b are provided on the side surfaces of the opening, while the semiconductor substrate 1 and the interlayer film 9 are provided. Since no etching stopper film is provided between and, the interlayer film 9 can be removed,
Fine contact holes can be formed without etching the protective films of the gate electrodes 4a and 4b, and the degree of integration can be improved, and the yield and reliability of the semiconductor device can be improved without short-circuiting the gate electrodes 4a and 4b.

Since wet etching is used, the protective films 23a, 23b, 24a for the gate electrodes 4a, 4b,
24b may be thin.

Example 3. 9 and 10 are views for explaining a method for manufacturing a semiconductor device according to the third embodiment. 9 and 10 show a series of manufacturing steps in two drawings for the sake of convenience, and these show continuous steps.

In the figure, reference numerals shown in FIG.
5), the same reference numerals indicate the same or corresponding portions, and the description thereof will be omitted.

Next, steps A to C will be described with reference to FIG. 9, and steps D and E will be described with reference to FIG.

Step A By the same steps as in Example 1, the element isolation region 2, the gate oxide film 3, and the gate electrode 4 are formed on the semiconductor substrate 1.
a, 4b, protective films 5a, 5b, first sidewall 6
a to 6d, the oxide film 7, the first etching stopper film 8 and the interlayer film 9 are formed (see steps A to C of Example 1).

Step B Next, the interlayer film 9 is flattened by etching back by RIE. As shown in FIG. 9B, this etch back is performed until the interlayer film 9 in the portion 22 above the gate electrode 4b is removed and the first etching stopper film 8 is exposed. At this time, the first etching stopper film 8 on the gate electrode 4a is also exposed.

Step C Polycrystalline silicon is deposited so as to overlap the interlayer film 9 and the first etching stopper film 8 exposed in the step B.
Then, the etching stopper film 10 is formed. That is,
A predetermined resist pattern (not shown) for forming a contact hole is formed thereon, and the polycrystalline silicon film is etched by RIE using this as a mask to expose the interlayer film 9 in the flat portion 12. After that, the resist mask is removed (FIG. 9C).

Step D The interlayer film 9 of the flat portion 12 is removed by wet etching with an HF solution or the like to expose the flat portion 15 (FIG. 10).
(d)). Since the silicon nitride film forming the first etching stopper film 8 and the polycrystalline silicon forming the second etching stopper film 10 are less likely to be etched than the interlayer film 9, only the interlayer film 9 is removed, and the gate electrode 4 is removed.
A and 4b are not exposed.

Step E Etching is performed by using RIE to remove the first etching stopper film 8 and the oxide film 7 on the flat portion 15 to expose the semiconductor substrate 1 (FIG. 10 (e)). In this way, the contact hole is formed. Since the etching in this step only removes the thin first etching stopper film 8, it takes only a short time, and the first etching stopper film 8 of the inclined portions 14a and 14b is hardly removed.

In the third embodiment, the first embodiment
As in the case of (FIGS. 1 to 5), the case where the oxide film 7 and the first etching stopper film 8 are formed on the semiconductor substrate 1 has been described as an example, but the present invention is not limited to this and the second embodiment (FIG. 6). 8 to 8), it can be applied to the case where the interlayer film 9 is directly formed on the semiconductor substrate 1. In this case, since the semiconductor substrate 1 is exposed, the RIE in the above step E is unnecessary.

As described above, according to the method of this embodiment, the first etching stopper film 8 on the gate electrodes 4a and 4b is used when the self-alignment method is used.
Is exposed, the second etching stopper film 10 is formed, and the flat portion 1 is formed by wet etching with good selectivity.
Since the second interlayer film 9 is removed and then the first etching stopper film 8 of the flat portion 15 is removed by dry etching, the etching time for the inclined portions 14a and 14b, which are easily etched by sputtering, is shortened, Fine contact holes can be formed without etching the protective films of the gate electrodes 4a and 4b, and the degree of integration can be improved, and the yield and reliability of the semiconductor device can be improved without short-circuiting the gate electrodes 4a and 4b.

Since wet etching is used, the protective films 5a, 5b, 6b, 6c for the gate electrodes 4a, 4b,
8 may be thin.

According to the semiconductor device manufacturing methods of the first to third embodiments, the second sidewalls 11a and 11 are formed.
b, the sloped portions 14a, 14b, etc., the contact hole has a forward taper shape (FIG. 11).
The filling property of the wiring material 41 such as polysilicon is improved.

For example, when burying polysilicon by the CVD method, thin films are sequentially formed and deposited on the bottom and side surfaces. Therefore, in the case of the vertical contact hole 52, FIG.
Although the gap 55 is likely to be formed as shown in (a2), in the case of the forward tapered contact hole 51, the process for forming the gap 55 without the gap as shown in FIG. 12 (a1) becomes unnecessary. Further, when aluminum is embedded by sputtering, it is difficult to form a film on the bottom. Therefore, in the case of the vertical contact hole 52, the thickness of the bottom may be thin as shown in FIG. In the case of the hole 51, this does not occur as shown in FIG. 12 (b1), and no contact failure occurs at the bottom.

[0070]

As described above, according to the invention of claim 1, after the side surface etching stop layer is provided on the side surface of the opening,
Since the contact holes are formed by exposing the semiconductor substrate by etching, the electrodes are not exposed and a short circuit between the electrodes can be prevented, which improves the yield and reliability of the semiconductor device.

According to the second aspect of the present invention, since the side surface etching stop layer is provided on the side surface of the opening, the semiconductor substrate is exposed by anisotropic etching to form the contact hole. The manufacturing process can be facilitated, the electrodes are not exposed, a short circuit between the electrodes can be prevented, and the yield and reliability of the semiconductor device are improved.

According to the third aspect of the invention, after the side surface etching stop layer is provided on the side surface of the opening, the semiconductor substrate is exposed by the isotropic etching having a high selection ratio to form the contact hole. The etching stop layer is hardly etched, the etching stop layer can be thinned, and even when a fine contact hole is formed,
The electrodes are not exposed, short circuits between the electrodes can be prevented, and the yield and reliability of the semiconductor device are improved.

Further, according to the invention of claim 4, since the second etching stop layer is formed after etching back until the first etching stop layer on the electrode is exposed, the second etching stop layer with respect to the first etching stop layer is formed. The etching time is short, the electrodes are not exposed, a short circuit between the electrodes can be prevented, and the yield and reliability of the semiconductor device are improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a cross section of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a sectional view showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a sectional view showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 7 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 8 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 9 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the third embodiment of the present invention.

FIG. 10 is a cross-sectional view showing the method of manufacturing the semiconductor device of Embodiment 3 of the invention.

FIG. 11 is a cross-sectional view showing a state of a wiring material deposited in a contact hole formed according to the present invention.

FIG. 12 is a diagram for explaining the relationship between the shape of a contact hole and the deposition state of a wiring material.

FIG. 13 is a cross-sectional view showing the conventional method of manufacturing a semiconductor device.

FIG. 14 is a cross-sectional view showing the conventional method of manufacturing a semiconductor device.

FIG. 15 is a diagram for explaining etching of the etching stopper film of the inclined portion.

[Explanation of symbols]

 1 semiconductor substrate 2 element isolation region 3 gate oxide film 4 gate electrode 5 protective film 6 first sidewall 7 oxide film 8 first etching stopper film 9 interlayer film 10 second etching stopper film 11 second sidewall

Claims (4)

[Claims] 1. A method of manufacturing a semiconductor device, wherein a first etching stop layer for protecting an electrode formed on a semiconductor substrate and an insulating layer are sequentially formed, and then an opening is formed by a self-alignment method. And a second step of forming a second etching stop layer, and removing the second etching stop layer by anisotropic etching based on a predetermined resist pattern and removing a part of the insulating layer. After the second step of forming the opening, and after forming the third etching stop layer on the entire surface, the third etching stop layer except for the side surface of the opening is removed by anisotropic etching to etch the side surface. The third step of forming a blocking layer, and the remaining portion of the insulating layer in the opening and the first etching blocking layer are removed by etching to expose the semiconductor substrate. 4th
The method of manufacturing a semiconductor device, comprising: 2. A method for manufacturing a semiconductor device, wherein a first etching stop layer for protecting an electrode formed on a semiconductor substrate and an insulating layer are sequentially formed, and then an opening is formed by a self-alignment method, wherein the insulating layer is formed. And a second step of forming a second etching stop layer, and removing the second etching stop layer by anisotropic etching based on a predetermined resist pattern and removing a part of the insulating layer. After the second step of forming the opening, and after forming the third etching stop layer on the entire surface, the third etching stop layer except for the side surface of the opening is removed by anisotropic etching to etch the side surface. The third step of forming a blocking layer, and the remaining portion of the insulating layer in the opening and the first etching blocking layer are removed by anisotropic etching to expose the semiconductor substrate. The method of manufacturing a semiconductor device, characterized in that it comprises a fourth step of. 3. A method for manufacturing a semiconductor device, wherein a first etching stop layer for protecting an electrode formed on a semiconductor substrate and an insulating layer are sequentially formed, and then an opening is formed by a self-alignment method. A first step of forming a first side surface etching stop layer by removing the first etching stop layer other than the side surface of the electrode by anisotropic etching, after forming the etching stop layer of A second step of forming the insulating layer, a third step of forming a second etching stopper layer on the insulating layer, and anisotropic etching based on a predetermined resist pattern to prevent the second etching stopper. A fourth step of removing the insulating layer and removing a part of the insulating layer to form an opening, and a third etching stop layer formed on the entire surface, and then anisotropic etching is performed. The fifth step of removing the third etching stopper layer on the portion other than the side surface of the opening to form the second side etching stopper layer, and the isotropic etching for selectively removing the insulating layer described above. A sixth step of removing the remaining portion of the insulating layer in the opening and exposing the semiconductor substrate. 4. A method of manufacturing a semiconductor device, wherein a first etching stop layer for protecting an electrode formed on a semiconductor substrate and an insulating layer are sequentially formed, and then an opening is formed by a self-alignment method. In a first step of etching back the insulating layer until the first etching stop layer is exposed, and after forming a second etching stop layer on the entire surface, anisotropic etching based on a predetermined resist pattern is performed. A second step of removing the second etching stop layer and providing an opening;
And a third step of removing the remaining portion of the insulating layer in the opening and the first etching stop layer by etching to expose the semiconductor substrate.