JPH07244623A - Transmission control device - Google Patents

Abstract

(57) [Summary] [Object] To provide a transmission control device capable of efficiently and efficiently transmitting data between data processing station devices having large differences in data transmission speed. [Structure] A storage means for temporarily storing received data of a transmission control device for converting parallel data and serial data by mutual conversion and transmitting and receiving the contents of each received word and after transfer processing of each word A control signal indicating the contents to be processed and a status flag indicating whether or not the received word is correctly stored, are stored in the same stage, and the same number of storage cells as the total number of bits of the data word, the control signal and the status flag. FI with multiple storage segments consisting of
It is configured as a FO type buffer 2, and when the data stored in the extended FIFO buffer 2 is extracted and transmitted, the data stored in the control signal storage cell and the status flag storage cell are read at the same time, and this information content is dealt with. The bus interface control unit 51 and the data conversion interface 52 that execute the above-described transfer processing constitute a transmission control device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention connects a process controller, a computer, etc. by a network,
The present invention relates to a transmission control device when performing communication.

[0002]

2. Description of the Related Art Communication between a controller and a computer connected by a network is performed by a serial data transmission system, but in a device such as a controller or a computer, data information is transmitted in parallel through an internal data bus. ing. For this reason, the transmission control device that connects the network transmission line and the individual controllers or computing devices connected to this transmission line has a conversion interface for converting parallel data and serial data mutually. In addition, since the parallel transmission rate of data through the parallel data bus and the serial transmission rate and transmission timing of data through the serial transmission path are usually different, the transmission control device does not immediately transfer the received data, The data is stored in the storage means, and the stored data is sequentially extracted and sent out to the transmission path of the transmission destination.

FIG. 7 shows the configuration of an example of a conventional transmission control device having the above-mentioned functions. In FIG. 7, a FIFO buffer 20 is a first-in-first-out (FIFO) type storage means in which parallel data is stored in the order of arrival of data and is read out in the order of arrival when it is sent out. Under the command from, the data transmitted from the external data memory C connected to the internal data bus A is sequentially stored in the above FIFO buffer, or conversely, the received data stored in the FIFO buffer is read in the order of reception. This is a bus interface for writing and storing in the external data memory C.

On the other hand, the data conversion interface 4 is
The parallel data stored in the FIFO buffer 20 is read out in the order in which it is stored and converted to serial data, and then sent out to the serial transmission line B constituting the network via the transmission line interface D, or vice versa. Alternatively, the serial data transmitted from the computer is received via the transmission line interface D, converted into parallel data, and the FIFO buffer 20
The data is written and stored in the order of arrival of data.

The operations of the bus interface 3 and the data conversion interface 4 described above are performed under the supervision and management of the transmission / reception control unit 70.
A FIFO buffer monitoring circuit that monitors whether or not there is room for writing data in the FO buffer 20 and, when there is no room for writing data, sends a signal for temporarily interrupting the input and reception of data until the data is transmitted and there is room for writing.
71 and the transfer of control signals such as start / stop of transmission / reception operation between the bus interface 3 and the data conversion interface 4, which are usually asynchronous in circuit, and the delivery of status flags indicating normal / abnormal of transmitted data. A timing control circuit 72 for confirmation is included.

In the transmission control device according to the prior art as described above, even if there is a large difference between the serial data transmission rate on the serial transmission line and the parallel data transmission rate via the bus interface on the internal bus, this difference is temporarily corrected by the FIFO. It is absorbed by being taken in the buffer, and it is possible to connect to a network such as a controller having a different transmission speed.

FIG. 8 shows an example of the structure of a message frame as an information data transmission / reception unit transmitted in the transmission control apparatus according to the prior art described with reference to FIG. The data information body to be transmitted is divided into block data 124 according to the character of the data information, and each divided block data is
At the beginning of the block 124, there is a block header 121 that describes information such as the number 122 of the data block and the number of bytes 123 as the amount of data, and at the end of the block data 124, the data was received correctly when it was received. A check sequence (hereinafter abbreviated as FCS) 125 that functions as a key for checking whether or not the block header 121 and the FCS 125 are attached to a plurality of block data of the same series are concatenated. A frame is composed of a start flag 111 and a frame header 110 consisting of a command for generating the address and storage area of the receiving station and the number of data blocks to be transmitted. , The end of the frame is attached with a termination flag sequence that notifies the end of the data receiving unit, and constitutes a message frame.

When a message frame is placed on the serial transmission line, the reception control unit of the transmission control device on the data receiving side reads the contents of the frame header, and if the self is designated as the receiving phase station, the contents of the command The received data is stored in the storage area of the external data memory of the receiving side device generated by, and when the FCS is received, it is checked whether or not the data is correctly received by the contents, and when the error is found, the error data is detected. It issues processing commands such as deletion and data resend.

[0009]

According to the above-mentioned transmission control device according to the prior art, it is possible to combine various controller calculation devices having different transmission / reception data transmission speeds into the same network to form a system. There are the following problems 1) and 2) in terms of data reliability and efficiency.

1) Even if an error is found in the data transmission,
Correct data may not be extracted correctly. That is, the transmission timing of the transmission data via the FIFO during transmission and the transmission of the status flag relating to the data for each unit are different, so that there is a time lag between the data and the status flag which is the information indicating the status. As a result of this time lag, it is transmitted that normal data remains inside the FIFO without being transferred to the bus interface, or conversely after the data has been transferred, that data was erroneous. The one-to-one correspondence between the status flag indicating an abnormal condition and the data corresponding to this flag may not be correctly transmitted.

2) The transmission efficiency is low between devices having greatly different transmission speeds. For example, at the time of transmission / reception operation, for the bus interface side and the data conversion interface side, the switching of the operation sequence on the side where the sequence ends early,
The operation of extracting the data accumulated in the FIFO is affected, and a waiting time occurs on the side that has completed the operation first, and the overall processing efficiency decreases.

The present invention solves the above problems of the transmission control device according to the prior art, and the transmission control device is capable of efficiently and reliably transmitting data between devices such as controllers having a large difference in data processing speed. The purpose is to provide.

[0013]

[Means for Solving the Problems] In order to achieve the above purpose,
In the first invention of the present application, the storage device for temporarily storing the transmission data of the transmission control device that couples the device and the device having the internal data bus for transferring the parallel data to the serial transmission line is provided from the same number of storage cells as the data word. When the data stored in the storage segment are extracted, the control signal indicating the content to be processed after each data word is extracted from the FIFO buffer and the FIFO buffer are extracted in the FIFO buffer which is extracted in the order of storage.
A status flag indicating the result of examining each data word stored in the O buffer;
Bit expansion memory cells are added to form an extended FIFO buffer in which the number of memory cells in each stage of the FIFO buffer is the same as the total number of bits of the data word, control signal, and status flag.

Then, the internal data bus and the extended FI are
The data passing through the bus interface that transfers data between the FO buffers is monitored, and when the data is written to the extended FIFO buffer, the passing data inspection result is written to the control signal storage cell and the status flag storage cell of the extended FIFO buffer. A bus interface control unit for reading the contents of the control signal storage cell and the status flag storage cell when extracting the data stored in the extended FIFO buffer, the transmission line interface connected to the serial transmission line, the transmission line interface connected to the serial transmission line, and the expansion F
By monitoring the data passing through the data conversion interface for converting the data serially to parallel between the IFO buffers and transferring the data, an operation equivalent to that of the bus interface control unit regarding the bus interface and the expansion FIFO buffer is performed. A data conversion interface control unit that acts on and,
A bus interface control unit and a transmission / reception control unit that controls transmission / reception of frame message data based on the contents of the storage cells read by the data conversion interface.

In the second invention of the present application, the extended F
The control signal storage cell and the status flag storage cell of the IFO buffer have a storage capacity of 1 bit or more, the control signal indicates the structural information of the message frame, the status flag indicates the error state of the stored information, and the transmission / reception control unit Performs a transmission process according to the structure information and a data error recovery process according to the status flag.

[0016]

An expanded FIF in which a status flag storage cell and a control signal storage cell are provided in the same stage as a storage segment of a data word.
When storing received data, the O buffer stores information designating a process to be performed after storing each received data word in the control signal storage cell, and stores information on normal / abnormal of stored data in the status flag storage cell. Then, the bus interface or the data conversion interface is extended FI.
When the data stored in the FO buffer is extracted and transmitted, the data stored in the control signal storage cell and the status flag storage cell are read at the same time, and the transfer process corresponding to this information content is executed.

When the control signal of the extended FIFO buffer and the storage cell of the status flag are expanded to 1 bit or more, it becomes possible to transmit various kinds of information as compared with the binary information in the case of 1 bit, and the control signal allows the transmission target. The structure information of the message frame is sent, and a simpler data transfer means suitable for the data structure is selectively executed for each data structure of each stage of the message frame. Further, a check code for precise check of the corresponding transfer data is transmitted by the status flag of a plurality of bits, and even if a transfer error occurs, the receiving side uses the check code to restore the data.

[0018]

FIG. 1 shows the configuration of an embodiment of a transmission control device according to the present invention. In FIG. 1, the extended FIFO buffer 2
Is a control signal of at least 1 bit for designating the next operation of the transmission / reception control unit 5 after the transmission / reception of the word data for each word data, and a status flag signal of at least 1 bit indicating whether the transmission / reception is correctly performed. Is a storage means having an internal structure shown in FIG. 2 in which a plurality of storage segments to which storage cells for storing the same are stored in the same stage as the data word are arrayed, which is different from the FIFO buffer 20 in the conventional device. The bit width of the storage segment is expanded by the bit width for storing the control signal and the status flag signal.

Reference numeral 3 in FIG. 1 indicates an internal data bus A and an extended FI.
Reference numeral 4 denotes a bus interface that executes data exchange between the FO buffers 2 under the control of a bus interface controller 51 that constitutes the transmission / reception controller 5, and 4 is a transmission path interface D that is coupled to a serial transmission path B of an external network. It is a data conversion interface that executes data exchange between the serial transmission line and the expansion FIFO buffer 2 via the control of the data conversion interface control unit 52 constituting the reception control unit 5.

The bus interface control unit 51 of the reception control unit 5 is composed of a control signal processing unit 512 and a status flag processing unit 511 and functions as follows. First, the internal data bus A
Frame message consisting of parallel data words from 100
Is transmitted and stored in the extended FIFO buffer 2, the control signal processing unit 512 causes the bus interface 3
For detecting the presence or absence of a subsequent data word of each data word, and when the bus interface 3 writes the data word to the storage segment of the expansion FIFO buffer 2, the detection result, namely the following data word The presence / absence is written in the memory cell added for storing the control signal at the same stage of the memory segment storing the data word. Then, the status flag processing unit 511 inspects the written and stored data word and the contents at the time of reception of the data word by a vertical parity check or other preset means, and the two match and the received data word is correctly expanded. When it is confirmed that the data word has been written into the FIFO buffer, a flag indicating normality, for example, 0 is written in the memory cell added for the status flag signal at the same stage of the memory segment storing the data word, and the received data word of the received data word is written. When it is detected that the contents are not correctly written, a flag indicating an error, for example, 1 is written.

Contrary to the above, when the bus interface 3 performs an operation of reading data from the expansion FIFO buffer 2 and loading it on the internal data bus A, the status flag processing unit 511 of the bus interface control unit 51 causes the expansion FIFO to operate.
The status flag stored in the status flag storage cell of the storage segment storing the data word to be read from the O buffer 2 is read, and if the content of the flag is normal, the data word stored in the storage segment in the bus interface 3 is read. Is sent to the internal data bus A as it is, and the content of the flag means an error,
The bus interface 3 is instructed to suspend the transmission or transmit a dummy signal to the internal data bus A based on a predetermined rule.

On the other hand, the data conversion interface controller
52 comprises a control signal processing unit 521 and a state flag processing unit 522, and functions as follows. First, the data is transmitted from the internal data bus A, and the expansion FIFO is transmitted via the bus interface 3.
When the data once stored in the O buffer 2 is sent to the serial transmission line B via the data conversion interface 4 and the transmission line interface D, it is pulled out when the data conversion interface 4 pulls out the data from the expansion FIFO buffer. The status flag processing unit 521 and the control signal processing unit 522 check the data to be read, and if the contents of the status flag are normal, the status flag processing unit 521 extracts the data stored in the data word storage cell as it is and performs serial conversion. After that, the transmission / reception control unit main body 50 is instructed to perform the process of transferring to the transmission path interface D. When the content of the extracted flag means abnormality, the status flag processing unit 521 instructs the transmission / reception control unit main body 50 to execute abnormality processing by a preset method such as stopping data transfer or inserting a dummy.

While the control signal processing unit 522 detects a signal with continuous data, the control signal processing unit 522 instructs the transmission / reception control main unit 50 to continue the data extraction transfer from the extended FIFO buffer 2. When the end signal of the message frame is detected and notified to the transmission / reception control unit main body, the operation mode of the transmission / reception control unit shifts to a mode such as preparation for transmission / reception of the next message frame.

Contrary to the above, when the data conversion interface 4 performs the operation of converting the serial data input from the transmission path interface D into parallel data and storing the parallel data in the extended FIFO buffer 2, the data conversion interface control section 52 is operated. Status flag processing unit 521 and control signal processing unit 522
Is a control signal that indicates the presence or absence of continuous data in the received data word by performing the same operation as when receiving the transmission data from the internal data bus of the bus interface control unit 51 and storing it in the expansion FIFO buffer 2. A status flag indicating the inspection result of the stored data is added.

As mentioned above, the control signal and the status flag are
It is added and used only when exchanging data between the bus interface 3 and the data conversion interface 4 via the extended FIFO buffer 2. Data transmission from the bus interface 3 to the internal data bus A,
In addition, when transmitting data from the data conversion interface 4 to the transmission interface D, this additional information is deleted. That is, the data flowing through the internal data bus A and the serial transmission line B becomes the message frame body having the structure illustrated in FIG.

The controller or the like connected to the network via the transmission control device according to the present invention described above receives data from the serial transmission line and stores the received data in the external data memory C of the controller through the internal data bus of the controller. FIG. 3 shows the flow of data and signals in the transmission control device in the case of doing so, and FIG. 4 shows the state of signal flow in the internal data bus A and the serial transmission line B at this time. In this example, the storage of the third data of the data block in the expansion FIFO buffer 2 fails and a status flag indicating an abnormality is set, and this abnormality flag is detected on the serial transmission side, and the data word storage segment at the same stage as the flag. It is shown that the data stored in is discarded and the transmission is interrupted or dummy data is sent out instead.

Contrary to the above, FIG. 5 shows the flow of data and signals in the device when data is sent from the controller or the like to the serial transmission line via the transmission control device.
At this time, the internal data bus A and the serial transmission line B
FIG. 6 shows the state of signal flow in. In this example, the storage of the third data of the data block in the expansion FIFO buffer 2 fails and a status flag indicating an abnormality is set, and the data in which this abnormal segment has been transmitted on the serial transmission side is discarded and the transmission is interrupted. Or dummy data is being sent out instead.

Further, in FIG. 6, the storage of data from the bus interface A having a high transmission speed to the FIFO buffer 2 is completed, and the control signal processing unit 512 sends a data end code to the control signal storage cell 23 of the FIFO buffer. It is indicated that when writing and notifying this to the transmission control unit main body 5, the transmission / reception control unit switches to the sequence and shifts the operation on the reception side to another operation until the transfer processing on the serial transmission side with a slow processing speed ends. There is.

In the above description, the status flag storage cell 22 and the control signal storage cell 23 added to the expansion FIFO buffer 2 are assumed to be 1-bit storage cells. By the way, when the number of bits of the additional memory cell of each of the status flag and the control signal is increased, the amount of information exchanged for transfer control between the bus interface control unit 51 and the data conversion interface control unit 52 is increased, and more precise It is possible to execute various transmission controls.

When the message frame 100 having the structure shown in FIG. 8 is transmitted, it is 1 when the control signal storage cell 23 has 4 bits.
Since 6 types of classification are possible, the frame header 110, the block header 121, etc.
It can tell which component of 0 is being transferred. When this division notification becomes possible, for example, in the case of the transfer of the header part, the number of words forming the header part is preset in the communication protocol, so when the first word of the header part is detected by the control signal processing part 512. , It becomes possible to continuously transfer word data of the number of constituent words of the header, and it is not necessary to check the existence of subsequent data one by one.

The word number information of the block header 121
If 123 is detected, the data in the data block corresponding to the number of words can be continuously transmitted without checking for the presence of subsequent data. Then, by expanding the number of bits of the status flag storage cell together with the number of bits of the control signal storage cell, it is possible to generate a check code such as a Hamming code that enables error correction on the data receiving side and store it in the FIFO buffer. Therefore, even if an erroneous data word is stored in the FIFO buffer, it is possible to repair the error to some extent by inspecting the extracted data using the Hamming code according to the status flag on the side that extracted this.

[0032]

When the received data is stored in the extended FIFO buffer in which the status flag storage cell and the control signal storage cell are provided in the same stage as the storage segment of the data word, the process to be performed next after storing each received data word is In the transmission control device according to the invention of the present application, the transfer signal is written in the control signal storage cell or in the normal / abnormal state of the stored data or in the state flag, and the transfer processing is executed on the sending side according to the information of the control signal storage cell and the state flag. , The control signal and the status flag corresponding to each word data to be transferred are attached, and the processing operation of transmission and reception is managed by the information of the control signal and the status flag, so that there is a difference in the transmission speed between the transmission and reception transmission paths. However, there is no need to have strict synchronization between the receiving and transmitting ends, and even if an incorrect transfer occurs, the data will be processed correctly,
It is possible to obtain an effect that erroneous data is not transmitted, or correctly received data does not remain without being transmitted.

The second embodiment of the present invention in which the storage cells for the control signal and the status flag of the extended FIFO buffer are expanded to 1 bit or more.
According to the transmission control device of the invention, the structure information of the message frame to be transmitted is sent by the control signal.
For each data structure of each stage of the message frame, it is possible to adopt a simpler data transfer means adaptable to the data structure, and it is possible to obtain the effect of improving the speed and efficiency of data transmission. As a result, it becomes possible to transmit a code for precise inspection of the corresponding transfer data, so that even if a transfer error occurs, it can be repaired to some extent on the receiving side.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of a transmission control device according to the present invention.

FIG. 2 is an explanatory diagram of a configuration of an extended FIFO buffer.

FIG. 3 is a diagram for explaining the flow of data and signals when receiving data from a serial transmission line.

FIG. 4 is a diagram for explaining the timing of data delivery when receiving data from a serial transmission line.

FIG. 5 is a diagram for explaining the flow of data and signals when sending data from an internal data bus to a serial transmission line.

FIG. 6 is a diagram for explaining the timing of data delivery when sending data from an internal data bus to a serial transmission line.

FIG. 7 is a configuration diagram of a transmission control device according to a conventional technique.

FIG. 8 is an explanatory diagram of a configuration of a message frame placed on a transmission line.

[Explanation of symbols]

 A internal data bus B serial transmission line C external data memory D transmission line interface 1 transmission control device 2 extended FIFO buffer 3 bus interface 4 data conversion interface 5 transmission / reception control unit 50 transmission / reception control unit 51 bus interface control unit 52 data conversion interface control Parts 511, 521 Status flag processing unit 512, 522 Control signal processing unit 70 Transmission / reception control unit 71 FIFO buffer monitoring circuit 72 Timing control circuit 20 FIFO buffer

Claims (2)

[Claims] 1. A transmission control device for connecting a device equipped with an internal data bus for transferring parallel data to a serial transmission line, comprising a plurality of storage segments each having the same number of storage cells as a data word. When extracting the data stored in the FIFO, the FIFO buffer for extracting in the order of storage stores a control signal indicating the contents to be processed after each data word is extracted from the FIFO buffer, and the FIFO buffer.
A status flag indicating the result of inspecting each data word stored in the buffer, and a storage cell of at least 1 bit for storing the status flag are added, and the number of storage cells in each stage of the FIFO buffer is added to the data word, the control signal, and the status. The data passing through the expansion FIFO buffer having the same number as the total number of bits of the flag and the bus interface for transferring data between the internal data bus and the expansion FIFO buffer are monitored, and when the data is written to the expansion FIFO buffer, the expansion is performed. A bus interface control unit that reads the contents of the control signal storage cell and the status flag storage cell when writing the passing data inspection result to the control signal storage cell and the status flag storage cell of the FIFO buffer, and when extracting the storage data of the extended FIFO buffer, and a serial interface. Transmission line interface connected to transmission line The data passing through the data conversion interface for converting and transferring the data in serial / parallel between the input FIFO buffer and the expansion FIFO buffer, and in the case of writing data to the expansion FIFO buffer, control signal storage cells and status flag of the expansion FIFO buffer. When the inspection result of the passing data to the memory cell is written and the stored data of the extended FIFO buffer is extracted, the contents of the control signal memory cell and the status flag memory cell are read. The data conversion interface control unit, the bus interface control unit and the data conversion interface read the contents. And a transmission / reception control unit that controls transmission / reception of frame message data based on the contents of the control signal storage cell and the status flag storage cell. 2. A control signal storage cell and a status flag storage cell of an extended FIFO buffer have a storage capacity of 1 bit or more, a control signal indicates structure information of a message frame, and a status flag indicates an error state of the stored information. The transmission / reception control unit performs transmission processing according to the structure information and data error recovery processing according to the status flag.
The transmission control device according to.