JPH1145189A - Data setting method and data processing device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To reduce a processing load at the time of setting new data in a data setting method and a data processing device for setting data in a controlled part composed of a plurality of blocks. A control unit includes a plurality of blocks for performing a series of processing on input data and a control unit including a processor. 1-m, at least a recovery register 14 and a transfer control unit 15 are provided together with the setting register 12, and when writing new data into the setting register 12, the transfer control unit 1
5, the old data is transferred from the setting register 12 to the recovery register 14, the new data is transferred from the control unit 2 to the setting register 12 and written, and the new data read from the setting register 12 is transferred to the control unit 2. The data is compared with the new data held therein, and in the case of a write error in which the comparison does not match, a recovery return instruction is given to the transfer control unit 15 to transfer the old data from the recovery register 14 to the setting register 12 and write the old data. Process and configuration.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data setting method for setting data to be subjected to a series of processes from a control unit to a controlled unit which sequentially performs a series of processes by a plurality of blocks on input data, and a data setting method. The present invention relates to a data processing device to which a data setting method is applied.

When input data is, for example, STM (Synchro
nous Transfer Mode) -N (STM-0 = 50Mb
ps, STM-1 = 155 Mbps, STM-4 = 62
2 Mbps, STM-16 = 2.488 Gbps), the data is input in a format including a payload and an overhead. In a data processing device such as a data transmission device, the main data is inserted or extracted into the payload. At the same time, extraction or insertion of a plurality of types of bytes of overhead is required. If the type and the number of bytes of the overhead are large, the processing function of a single block cannot cope with the problem. In this case, it is necessary to set control data for a processing function in each block, and it is desired to facilitate the processing of the data setting.

[0003]

2. Description of the Related Art FIG. 11 is an explanatory view of a conventional example.
1 to 51-m are blocks constituting a controlled unit, 52 is a control unit, 53 is a processor (CPU), 54 is a higher-level control device, 55 is a bus, 61 is an interface unit (IF), 6
2 is a setting register, 63 is a processing unit, Din is input data, and Dout is output data.

The blocks 51-1 to 51-m have, for example, the same or different configurations in which a plurality of semiconductor integrated circuits are mounted on a printed circuit board, and are connected to each other by a back board or the like (not shown). Interface section 6
1 includes an address decoder for identifying that the own block is designated, receives data to be set in the setting register 62 from the processor 53 of the control unit 52 via the bus 55, and reads out the data from the setting register 62. It has a bus access function for transmitting data.

The processing section 63 performs a series of processing on the input data Din in each block to produce output data Dout. The processing contents include, for example, the above-described input data of the ATM-N. Processing of bytes corresponding to various types of overhead of Din, or processing such as insertion or dropping of a multiplexed data block for main data is performed, and processing according to data set in the setting register 62 is performed. Therefore, the setting data of the setting register 62 corresponding to each block often differs, but may be the same.

When writing data to the setting register 62, the processor 53 of the control unit 52 sequentially designates each of the blocks 51-1 to 51-m of the controlled unit via the bus 55 in accordance with an instruction from the host controller 54. Then, the data is transferred to the setting register 62 via the interface unit 63. The processor 53 of the control unit 52 can read data from the setting register 62 by designating each of the blocks 51-1 to 51-m. Therefore, the bold line is the path of the data related to the setting register 62.

FIG. 12 is an explanatory diagram of a sequence in a normal state in a conventional example, in which a host controller 54, a processor (CPU) 53 of a control unit, and blocks 51-1 to 51 of a controlled unit.
-M indicates a case in which the data of the setting register 62 is changed. In a state where the processing of the input data Din is stopped, the upper control device 54 inputs a change request to the processor (CPU) 53 of the control unit 52. I do. Thereby, the processor 53 controls the blocks 51-1 to 51-1 of the controlled unit.
For example, the old data is read out by designating the block 51-1 of 51-m. Thereby, the setting register 62
Is read out, and the processor 5 of the control unit 52 is read out via the interface unit 61 and the bus 55.
3 and the processor 53 holds the old data.

Next, the processor 53 issues a new data write instruction, transfers new data for the block 51-1 to the setting register 62 via the bus 55 and the interface unit 61, and writes the new data. Upon completion of writing, new data reading instruction is performed, new data is read from setting register 62, and the read new data is checked. That is, the new data to be written to the setting register 62 is compared with the new data to be read from the setting register 62, and it is determined that the data has been normally written due to the comparison coincidence. Is performed.

Similarly, for the last block 51-1m, the old data is read from the setting register 62 and held.
After writing the new data, the new data is read, the new data written to the setting register 62 is compared with the new data read from the setting register 62, and it is determined that the writing has been normally performed based on the comparison match. Then, the processor 53 of the control unit 52 notifies the host controller 54 of the end of the change. The higher-level control device 54 sets new data in all the blocks 51-1 to 51-m by the change end notification.
The processing of the input data Din in 1-m is started.

FIG. 13 is an explanatory diagram of a sequence at the time of an abnormality in the conventional example.
The writing of the new data to the blocks 51-1 to 51-m-1 is normally performed. In the writing of the new data to the block 51-m, the new data to be written to the setting register 62 and the new data from the setting register 62 This indicates a case where the data does not match when compared with the new read data. In this case, since the writing is abnormal, the processor 53 of the control unit 52 reads out from the setting register 62 of the blocks 51-1 to 51-m. The held old data is sequentially transferred and written to the setting register 62 of the original block.

That is, when an error occurs during data setting, writing is performed so that the old data is restored, and when the writing of the old data is completed, the upper controller 54 is notified of the change failure. The higher-level control device 54 causes the data setting to be retried in response to the change failure notification, or the input data D according to the processing content by returning to the old data.
A series of processes for "in" is restarted.

[0012]

When new data is set in the setting register 62 of each of the blocks 51-1 to 51-m in response to a change request from the host control device 54, the old data in the setting register 62 is read and controlled. The data to be set in the setting register 62 may be relatively large depending on the complexity of the processing contents of the processing unit 63. When processing the input data Din, block 51-1
~ 51-m becomes large.

Therefore, the amount of old data to be held in the control unit 52 becomes very large, and when an abnormality occurs, the process of restoring the old data to the block where the abnormality has occurred is sequentially performed. There is a problem that the processing load on the processor 53 is large and the processing time is long. SUMMARY OF THE INVENTION It is an object of the present invention to reduce the processing load of setting data in a setting register and reduce the processing time with a relatively simple configuration.

[0014]

According to the data setting method of the present invention, there are provided: (1) a plurality of blocks 1 for input data Din;
A data setting method for setting data for performing a series of processes from the control unit 2 to each block 1-1 to 1-m of a controlled unit that sequentially performs a series of processes according to -1 to 1-m. ,
When new data is set in the plurality of blocks 1-1 to 1-m from the control unit 2, the old data in the setting register 12 is replaced with the recovery register 1 by a transfer instruction from the control unit 2.
4, the new data from the control unit 2 is written into the setting register 12, and then the new data is written into the setting register 1.
2 and comparing the new data written to the setting register 12 and the new data read from the setting register 12 to determine whether the writing of the new data is normal or abnormal. Therefore, the control unit 2 does not need to hold the old data, can reduce the size of the hardware configuration, and can reduce the processing load on the processor 3 of the control unit 2.

(2) The new data to be written to the setting register 12 is compared with the new data to be read from the setting register 12. This includes a process of performing recovery recovery processing for transferring the old data held in the recovery register 14 to the setting register 12 and writing the old data held in the recovery register 14 for 1-1 to 1-m. That is, when the data to be set in the setting register 12 is changed, the process of restoring the old data due to a write error is performed from the recovery register 14, so that the control unit 2 in the recovery process of restoring the old data is performed. , The processing load on the processor is significantly reduced.

(3) When the old data is transferred between the setting register 12 and the recovery register 14, a step of monitoring a transfer error of the old data can be included. Thereby,
It is possible to monitor the occurrence of an error in the old data transferred from the setting register 12 to the recovery register 14 and from the recovery register 14 to the setting register 12 to maintain the reliability of the old data.

(4) The new data to be written to the setting register 12 is compared with the new data to be read from the setting register 12, and when it is determined that the writing is abnormal due to a comparison mismatch, a plurality of blocks 1- A process may be included in which a simultaneous recovery return instruction is sent to signal lines 1 to 1-m via a signal line, and the old data held in the recovery register 14 is transferred to the setting register 12 and written.

The data processing apparatus according to the present invention comprises: (5) a controlled unit for sequentially performing a series of processing on input data by a plurality of blocks 1-1 to 1-m; and a plurality of blocks of the controlled unit. A control unit 2 for setting data for controlling the processing in 1-1 to 1-m in the controlled unit, wherein the plurality of blocks 1-1 to 1-m include: A setting register 12 for setting data from the control unit 2, a recovery register 14 for transferring data between the setting register 12, and a setting register 1 for writing new data.
2 is transferred to the recovery register 14, and when it is determined that writing is abnormal by the determination process after writing new data to the setting register 12, the old data is transferred from the recovery register 14 to the setting register 12. And a transfer control unit 15 for controlling the transfer and writing of the data. Therefore, when the setting data is changed, the transfer control unit 1
5, the old data can be transferred from the setting register 12 to the recovery register 14, and the old data can be returned from the recovery register 14 to the setting register 12 when writing of new data is abnormal.

(6) A plurality of blocks 1-1 to 1-m
May include a monitoring unit that monitors an error in data transferred between the setting register 12 and the recovery register 14. That is, the setting register 12 and the recovery register 1
When the old data is transferred to and from the host 4, the normality of the transferred old data can be confirmed by parity check, CRC check, sum check, and the like.

(7) A signal line for transferring a simultaneous recovery return instruction can be provided between the control unit 2 and the transfer control units 15 of the plurality of blocks 1-1 to 1-m of the controlled unit. . In other words, the process of returning the old data from the recovery register 14 to the setting register 12 can be performed at the same time when the writing of new data is abnormal.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an explanatory diagram of a first embodiment of the present invention, wherein 1-1 to 1-m are blocks of a controlled unit, 2 is a control unit, and 3 is a processor (CPU). 4 is a host controller, 5 is a bus, and 11 is an interface unit (I
F) and 12 are setting registers, 13 is a processing unit, 14 is a recovery register, and 15 is a transfer control unit. As in the conventional example, blocks 1-1 to 1--1 are used for input data Din.
The m processing unit 13 sequentially performs a series of processes to obtain output data Dout. A bold line indicates an outline of a data transfer path to the setting register 12.

This embodiment corresponds to a configuration in which a recovery register 14 and a transfer control unit 15 are provided for a conventional block, and the transfer control unit 15 responds to an instruction from the processor 3 of the control unit 2. , And transfer control of old data between the setting register 12 and the recovery register 14. As described above, each of the blocks 1-1 to 1-m can be configured to, for example, share and process bytes corresponding to each type of overhead of the input data Din of the STM-N. Therefore, the data set in the setting register 12 of each of the blocks 1-1 to 1-m often differs depending on the blocks 1-1 to 1-m.
Generally, commonality is difficult. For this reason, the conventional example has a configuration in which data is written to the setting register corresponding to each block.

FIG. 2 is an explanatory diagram of a sequence in a normal state according to the first embodiment of the present invention.
Processor (CPU) 3 and block 1-1 of the controlled unit
When the data set in the setting register 12 of each of the blocks 1-1 to 1-m is changed, the processing of the input data Din is stopped, and the host controller 4 The processor 3 inputs a change request to the processor 3. The processor 3 designates, for example, the block 1-1 among the plurality of blocks 1-1 to 1-m and issues a recovery transfer instruction.

In the block 1-1 of the controlled unit, this recovery transfer instruction is input to the transfer control unit 15 via the bus 5 and the interface unit 11. Thereby, the transfer control unit 15 transfers the old data of the setting register 12 to the recovery register 14. The processor 3 of the control unit 2 sends a new data write instruction after sending the recovery transfer instruction, after the time when the transfer of the old data to the recovery register 14 ends, or after receiving the transfer end notification, and Send out new data.

The new data is input to the setting register 12 via the bus 5 and the interface unit 11, and the new data is written to the setting register 12. Immediately after this writing is completed,
A new data read instruction is sent from the processor 3 of the control unit 2. Thus, new data is read from the setting register 12 and transferred to the processor 3. The processor 3 compares the held new data to be written to the setting register 12 with the new data read from the setting register 12 after the writing is completed. Then, the process of writing new data to the next block 1-2 is started.

That is, the processor 3 sequentially issues a recovery transfer instruction, a new data write instruction, a new data transmission, and a new data read instruction to write new data to the setting register 12 and read new data from the setting register 12. To determine whether or not the writing is normal. If the writing is normal, the new block is written to the next block. Then, when the writing of the new data to the last block 1-m is also completed normally, the processor 3 of the control unit 2 notifies the host controller 4 of the completion of the change. The host controller 4 restarts the processing of the input data Din based on the change end notification.

Therefore, the control unit 2 does not need to read the old data from the setting register 12 via the bus 5 and does not need to retain the old data. Is reduced, and the configuration of the control unit 2 can be reduced in size.

FIG. 3 is an explanatory diagram of a sequence when an abnormality occurs in the first embodiment of the present invention. The process of writing new data to the setting register 12 is the same as that shown in FIG. For example, in writing new data to the block 1-m, new data written to the setting register 12 held in the processor 2 is compared with new data read from the setting register 12 after the writing is completed. At this time, when it is determined that the writing is abnormal due to the comparison mismatch, the processor 3 of the control unit 2 sequentially sends a recovery return instruction to the plurality of blocks 1-1 to 1-m.

Upon receiving the recovery return instruction, the transfer control unit 15 sends the recovery register 14 to the setting register 12.
The old data is transferred and written to all blocks 1-1 to 1--1.
After sending the recovery return instruction to m, the processor 3 of the control unit 2 notifies the host controller 4 of the change failure.

Therefore, the control unit 2 only needs to send a recovery return instruction to each of the blocks 1-1 to 1-m after judging a write error. Data can be written. Further, the processing load on the processor 3 of the control unit 2 can be remarkably reduced as compared with the case where the old data is sequentially transferred and written under the control of the processor 3 as in the conventional example.

FIG. 4 is an explanatory view of the second embodiment of the present invention. The same reference numerals as in FIG. 1 denote the same parts, and 16 denotes a monitoring unit. The upper control device is not shown.
The monitoring unit 16 performs a parity check, a CRC, and the like in the process of transferring old data between the setting register 12 and the recovery register 14 under the control of the transfer control unit 15.
Has a function of performing a check process such as a check, a sum check, and the like.

For example, since the old data is serially transferred from the setting register 12 to the recovery register 14 and written, the monitoring unit 16 obtains and stores a data sum in the process, and in response to the recovery return instruction, Since the old data is serially transferred from the recovery register 14 to the setting register 12 and written, the monitoring unit 16 obtains a data sum in the process and compares it with the previously stored data sum. In the case of a comparison match, the transferred old data can be determined to be normal. If the comparisons do not match, the old data returned to the setting register 12 is determined to be abnormal, and the processor 3 of the control unit 2 is notified of the abnormality.

When a parity bit is added to the data written in the setting register 12, the monitoring unit 16 performs a parity check when transferring the data to the recovery register 14 and writing the data. A parity check is also performed when the data is transferred to the register 12 and written. If the parity is abnormal, the processor 3 of the control unit 2 is notified of the abnormality.

In the case of data to which a parity bit is not added, the setting register 12 sends the recovery register 1
In the process of transferring the data to the H.4, the monitoring unit 16 performs a parity operation, writes the parity bit with the parity bit added to the recovery register 14, and transfers the data from the recovery register 14 to the setting register 12 for writing. , A parity check can be performed, and the parity bit can be deleted and written to the setting register 12. Also in this case, in the case of a parity error, an error is notified to the processor 3 of the control unit 2. Also, it can be checked by CRC calculation in the same manner as described above.

FIG. 5 is an explanatory diagram of a sequence in a normal state according to the second embodiment of the present invention, in which the host controller, the processor (CPU) 3 of the control unit 2, and the blocks 1-1 to 1-1 of the controlled unit.
1-m, when the data set in the setting register 12 of each of the blocks 1-1 to 1-m is changed, the processing of the input data Din is stopped and the processor of the control unit 2 Enter the change request in 3.
The processor 3 designates, for example, the block 1-1 among the plurality of blocks 1-1 to 1-m and issues a recovery transfer instruction.

In the block 1-1 of the controlled unit, the recovery transfer instruction is input to the transfer control unit 15 via the bus 5 and the interface unit 11. Thereby, the transfer control unit 15 transfers the old data of the setting register 12 to the recovery register 14. At this time, the monitoring unit 16 monitors the transfer data. After sending the recovery transfer instruction, the processor 3 of the control unit 2 sends out a new data write instruction after the time when the transfer of the old data to the recovery register 14 ends, or after receiving the transfer end notification, And it sends out new data.

The new data is input to the setting register 12 via the bus 5 and the interface unit 11, and the new data is written to the setting register 12. Immediately after this writing is completed,
A new data read instruction is sent from the processor 3 of the control unit 2. Thus, new data is read from the setting register 12 and transferred to the processor 3. The processor 3 compares the held new data to be written to the setting register 12 with the new data read from the setting register 12 after the writing is completed. Then, the process of writing new data to the next block 1-2 is started.

As described above, the processor 3 sequentially issues a recovery transfer instruction, a new data write instruction, a new data transmission, and a new data read instruction to write new data to the setting register and read new data from the setting register. By comparing the data with the data, it is determined whether or not the writing is normal. If the writing is normal, the new data is written to the next block. When the writing of the new data to the last block 1-m is completed normally, the processor 3 of the control unit 2 notifies the host controller of the change completion. The host controller restarts the processing of the input data Din based on the change end notification.

FIG. 6 is an explanatory diagram of a sequence at the time of an abnormality according to the second embodiment of the present invention. The process of writing new data to the setting register 12 is the same as that shown in FIG. For example, in writing new data to the block 1-m, new data written to the setting register 12 held in the processor 2 is compared with new data read from the setting register 12 after the writing is completed. At this time, if it is determined that there is a write error due to the comparison mismatch, the processor 3 of the control unit 2 sends a recovery return instruction to the new data write end block and the write error occurrence block. As described above, when a write error occurs in the last block 1-m, a plurality of all blocks 1-1 to 1-l
m, a recovery return instruction is sequentially transmitted.

The transfer control unit 15 having received the recovery return instruction sends the recovery register 14 the setting register 12
Transfer and write old data to In this data transfer process, the monitoring unit 16 monitors the transfer data, and when an error such as a parity check error is detected, notifies the processor 3 of the control unit 2 of an error. If no abnormality is detected in the transfer data, a recovery recovery instruction is sequentially sent to all blocks 1-1 to 1-m, and the processor 3 of the control unit 2
Notifies the host controller of the change failure. Further, during the recovery process according to the recovery return instruction, if the above-described abnormality of the transfer data is detected and the abnormality is notified to the processor 3, the maintenance person is notified of the abnormality as an abnormal end or the processor of the control unit 2 is notified. From 3, the process of sequentially writing new data or old data into the setting registers 12 of the blocks 1-1 to 1-m can be performed. That is, a retry process can be performed.

FIG. 7 is an explanatory view of the third embodiment of the present invention. The same reference numerals as in FIG. 1 denote the same parts, and reference numeral 20 denotes a signal line. The signal line 20 is connected to the processor 3 of the control unit 2.
To issue a simultaneous recovery return instruction to the transfer control unit 15 of each of the blocks 1-1 to 1-m. When the new data is normally written in the setting register 12 in response to the change request from the higher-level control device, the writing is performed according to the sequence shown in FIG.

FIG. 8 is an explanatory diagram of a sequence at the time of abnormality according to the third embodiment of the present invention. In the process of writing new data to the setting register 12 in accordance with a change request from a higher-level control device, block 1- This indicates that an error has occurred during the writing of new data to m, the new data to be written to the setting register 12 of the block 1-m held in the processor 3, and the setting after writing the new data. The processor 3 compares the read new data from the register 12 with the new data, and determines that the writing is abnormal due to the comparison mismatch.
, And sends a simultaneous recovery return instruction to all blocks 1-1 to 1-m to notify the host controller of the change failure.

The transfer control unit 15 to which the simultaneous recovery return instruction has been input via the signal line 20
Is transferred to the setting register 12 for writing. Therefore, the processor 3 of the control unit 2 only needs to send the simultaneous recovery return instruction at the time of the writing error, so that the processing load is remarkably reduced, and the recovery processing in all the blocks 1-1 to 1-m is performed in parallel. There is an advantage that it can be completed in a short time. Therefore, even if it fails when writing new data to the setting register 12, the input data D
The stop time of the processing of “in” can be reduced.

FIG. 9 is an explanatory diagram of the fourth embodiment of the present invention. The same reference numerals as in FIG. 4 denote the same parts, and reference numeral 20 denotes a signal line. This signal line 20 is sent from the processor 3 of the control unit 2 to each of the blocks 1-1 to 1 as in the case shown in FIG.
This is for instructing the −m transfer control unit 15 to return to the simultaneous recovery. When the new data is normally written in the setting register 12 in response to the change request from the higher-level control device, the writing is performed according to the sequence shown in FIG. The monitoring unit 16 monitors the transfer data between the setting register 12 and the recovery register 14.

FIG. 10 is an explanatory diagram of a sequence at the time of an abnormality according to the fourth embodiment of the present invention. In the process of writing new data to the setting register 12 in accordance with a change request from a higher-level control device, block 1- This indicates a case where an abnormality has occurred during writing of new data to m. New data to be written to the setting register 12 of the block 1-m held in the processor 3 When the comparison is made with the read new data and it is determined that the writing is abnormal due to the comparison inconsistency, the processor 3 transmits all the blocks 1-1 to 1--1 through the signal line 20 as in the case shown in FIG.
m, a simultaneous recovery return instruction is sent out, and a change failure is notified to the host controller.

The transfer control unit 15 to which the simultaneous recovery return instruction has been input via the signal line 20
Is transferred to the setting register 12 for writing. The transfer data is monitored by the monitoring unit 16 by a parity check or the like, and when an abnormality is detected, the processor 3 is notified of the abnormality. The processor 3 of the control unit 2 only needs to send a simultaneous recovery return instruction when writing of new data is abnormal, so that the processing load is remarkably reduced, and all blocks 1-1.
Since the recovery processing in .about.1-m is performed in parallel, there is an advantage that the processing can be performed in a short time, and the reliability of the old data by the recovery processing can be maintained.

The present invention is not limited to the above-described embodiments, but can be variously added and changed. In addition, although STM-N is shown as an example of the input data Din, the present invention is not limited to this. The present invention can also be applied to a case where a series of processing is performed on data in various formats.

[0048]

As described above, according to the present invention, a plurality of blocks 1 for performing a series of processing on input data Din are provided.
A data setting method for setting various data from the control unit 2 to a controlled unit consisting of -1 to 1-m, and a data processing apparatus to which the data setting method is applied, wherein each block 1-m
1 to 1-m, a recovery register 14 and a transfer control unit 15 are provided together with the setting register 12, and when the control unit 2 sets new data in the setting register 12, the old data of the setting register 12 is transferred to the transfer control unit 15. Is transferred to the recovery register 14, the new data is transferred from the control unit 2 and written to the setting register 12, the new data is read from the setting register 12, and the setting register stored in the control unit 2 is stored. The new data to be written into the register 12 is compared with the new data read from the setting register 12 after the writing is completed to determine whether the writing of the new data is normal or not. Since there is no need to transfer data to the control unit 2 and hold it, the size of the control unit 2 can be reduced, and the processing load on the processor 3 of the control unit 2 can be reduced. A.

The control unit 2 compares the new data to be written to the setting register 12 with the new data to be read from the setting register 12. By simply giving a recovery return instruction, the old data of the recovery register 14 is set to the setting register 1
2, it is possible to quickly perform a recovery process in the case of a writing error at the time of writing new data without increasing the processing load on the processor 3 of the control unit 2, and There is an advantage that the suspension period of the processing of the input data Din can be shortened.

The setting register 12 and the recovery register 1
The reliability of the old data after recovery processing in the event of a write error is ensured by monitoring the old data by parity check, CRC check, sum check, etc. in the transfer of the old data to the old data. There are advantages that can be.

A simultaneous recovery return instruction is simultaneously applied from the control unit 2 to the transfer control units 15 of all the blocks 1-1 to 1-m via a signal line, and the recovery processing is performed for all the blocks 1 to 1-m.
In the case where the processing is performed in parallel in steps 1 to 1-m, the processing load on the processor 3 of the control unit 2 at the time of an error in writing new data can be significantly reduced, and the recovery processing time can be shortened. There are advantages that can be done.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of a sequence in a normal state according to the first embodiment of this invention;

FIG. 3 is a diagram illustrating a sequence when an abnormality occurs according to the first embodiment of this invention.

FIG. 4 is an explanatory diagram of a second embodiment of the present invention.

FIG. 5 is an explanatory diagram of a sequence in a normal state according to the second embodiment of this invention.

FIG. 6 is a sequence explanatory diagram at the time of abnormality according to the second embodiment of this invention.

FIG. 7 is an explanatory diagram of a third embodiment of the present invention.

FIG. 8 is a diagram illustrating a sequence when an abnormality occurs according to the third embodiment of this invention.

FIG. 9 is an explanatory diagram of a fourth embodiment of the present invention.

FIG. 10 is a sequence explanatory diagram at the time of abnormality according to the fourth embodiment of the present invention.

FIG. 11 is an explanatory diagram of a conventional example.

FIG. 12 is an explanatory diagram of a sequence in a normal state in a normal state.

FIG. 13 is an explanatory diagram of a sequence at the time of abnormality in the conventional example.

[Explanation of symbols]

 1-1 to 1-m block 2 control unit 3 processor (CPU) 4 higher-level control device 5 bus 11 interface unit (IF) 12 setting register 13 processing unit 14 recovery register 15 transfer control unit

Claims (7)

[Claims] 1. A method according to claim 1, wherein each block of the controlled unit sequentially performs a series of processes on a plurality of blocks with respect to input data.
In a data setting method for setting data for performing the series of processes from a control unit, when setting new data in the plurality of blocks from the control unit, a transfer instruction from the control unit causes a setting register to be set. After the old data is transferred to the recovery register, new data from the control unit is written to the setting register, and the new data is read from the setting register, and the new data written to the setting register and the setting register are written. A data setting method comprising the step of comparing read new data from a new data to determine whether writing of new data is normal or abnormal. 2. A new data to be written to the setting register is compared with new data to be read from the setting register. If the two data do not match, it is determined that a writing error has occurred. 2. The data setting method according to claim 1, further comprising a step of performing a recovery return process of transferring old data held in the recovery register to the setting register and writing the old data. 3. The method according to claim 1, further comprising the step of monitoring a transfer error of the old data when transferring the old data between the setting register and the recovery register.
Data setting method described. 4. The control unit compares the new data written to the setting register with the new data read from the setting register, and determines that the writing is abnormal due to a comparison mismatch. 4. The method according to claim 1, further comprising a step of transmitting a simultaneous recovery return instruction via a signal line, and transferring and writing old data held in the recovery register to the setting register. Data setting method. 5. A controlled unit for sequentially performing a series of processing on input data by a plurality of blocks, and data for controlling processing of the controlled unit in the plurality of blocks is transmitted to the controlled unit. In the data processing device including a control unit for setting, the plurality of blocks include: a setting register for setting data from the control unit; a recovery register for transferring data between the setting register; When writing, the old data set in the setting register is transferred to the recovery register, and when it is determined that writing is abnormal by a determination process after writing new data to the setting register, the setting is performed from the recovery register. A data processing device comprising: a transfer control unit that controls transfer of old data to a register for writing. 6. The apparatus according to claim 1, wherein the plurality of blocks include a monitoring unit that monitors an error in data transferred between the setting register and the recovery register.
The data processing device according to claim 1. 7. A signal line for transferring a simultaneous recovery return instruction is provided between the control unit and the transfer control units of the plurality of blocks of the controlled unit. 7. The data processing device according to 6.