JPH07249697A - Nonvolatile semiconductor memory device - Google Patents

Abstract

(57) [Summary] [Object] To provide a non-volatile semiconductor memory device capable of high integration by significantly reducing the influence of variations in element characteristics while ensuring long-term reliability. In a nonvolatile semiconductor memory device, a gate bird's beak in a post-oxidation step is formed large on a first insulating film side between a silicon substrate and a floating gate and small on a second insulating film side between a floating gate and a control gate. To do. Therefore, the impurity concentration on the upper side of the polycrystalline silicon film to be the floating gate is made lower than that on the lower side. Further, a similar effect can be obtained by forming a nitride film on the upper surface of this polycrystalline silicon film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device.

[0002]

2. Description of the Related Art A nonvolatile memory has a floating gate as an intermediate electrode and a control gate above the floating gate. An electric field is applied by the control gate to inject charges into the floating gate by the tunnel effect, or There is a double gate structure that enables electrical writing and erasing by pulling out.

In this structure, a layer of polycrystalline silicon that serves as a floating gate is sandwiched between oxide films, and electrons or holes generated near the drain are injected into the floating gate by the Fowler-Nordheim effect. As a result, as the floating gate is charged, the opposite charge is induced on the semiconductor surface of the channel region, and the conduction state between the source and drain is determined.

At present, the dual gate type nonvolatile memory has N
AND-type 4-megabit LSIs are the mainstream, and 16-megabit ones are being developed.

In such a non-volatile memory, the reliability of the insulating film is important, but it is becoming difficult to secure the reliability as the integration and the miniaturization progress.

One of the factors that impair the reliability of the insulating film is considered to be variations in the geometrical shape of the element. Due to this variation, an electric field is applied more than designed, and an excessive current or a shortened life is caused. It is considered.

Therefore, in the process of processing the memory element, it is proposed to perform post-oxidation in order to recover the damage of the insulating film and secure long-term reliability after the gate processing.

[0008]

However, an increase in thickness called gate bird's beak occurs in the insulating film between the silicon substrate and the floating gate and between the floating gate and the control gate in this post-oxidation step. This causes a problem that the ratio of capacitive coupling between the control gate and the floating gate is changed and the device characteristics are varied.

An object of the present invention is to provide a highly reliable nonvolatile semiconductor memory device which is not easily affected by variations in device characteristics due to gate bird's beaks generated in the post-oxidation process.

[0010]

According to the present invention, a first insulating film is formed on a channel region formed on a surface of a semiconductor substrate,
In a nonvolatile semiconductor memory device having a stacked structure in which a floating gate, a second insulating film, and a control gate are sequentially stacked,
The increase in the film thickness at the end portion with respect to the central portion of the second insulating film is
It is characterized in that it is smaller than the increase in the film thickness of the end portion with respect to the central portion of the first insulating film.

The floating gate is preferably a polycrystalline silicon film having a high impurity concentration gradient on the first insulating film side and a low impurity concentration gradient on the second insulating film side.

Further, nitride films may be formed at the interface between the floating gate and the second insulating film and at the interface between the control gate and the second insulating film, respectively.

[0013]

In the non-volatile semiconductor memory device according to the present invention, the gate bird's beak is formed small on the second insulating film side above the floating gate and large on the first insulating film side below. ing.

In such a structure, a large gate bird's beak is formed at the end of the first insulating film,
The ratio of the tunnel current flowing between the silicon substrate and the floating gate in the central portion of the channel region increases. That is, since the gate bird's beak is formed at the end portion of the first insulating film, the tunnel current flows through the highly reliable first insulating film portion in the central portion of the channel region. As a result, the influence on the tunnel current characteristics after the post-oxidation process can be significantly reduced.

In order to obtain such a structure, when forming the floating gate, the impurity concentration of polycrystalline silicon should be low on the upper second insulating film side and high on the lower first insulating film side. It is graded. This utilizes the fact that the higher the impurity concentration in polycrystalline silicon, the higher the oxidation rate.

Further, instead of adjusting the entry of the gate bird's beak by such an impurity concentration gradient, the interface between the floating gate and the second insulating film and the interface between the second insulating film and the control gate are adjusted. When the nitride film is formed, the gate bird's beak is hardly formed on the second insulating film in the post-oxidation process, and thus the tunnel current characteristics can be similarly stabilized.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of an embodiment of a nonvolatile semiconductor memory device according to the present invention. In this non-volatile semiconductor memory device, N-type source and drain regions 2 are formed on a surface of a P-type silicon substrate 1 with a channel region 1a sandwiched therebetween, and a first gate insulating layer is formed on the channel region 1a. A film 3, a floating gate 4 made of polycrystalline silicon, a second gate insulating film 5, a control gate 6 made of polycrystalline silicon, and a tungsten silicide (WSi ₂ ) film 7 are sequentially stacked thereon.

Also in this non-volatile semiconductor memory device, gate bird's beaks 3a, 5a are generated in the post-oxidation step, but the amount thereof is large on the first insulating film 3 side and the second
Is small on the insulating film 5 side. Therefore, as described above, most of the tunnel current flows through the central portion of the first insulating film, so that the effect of the gate bird's beak generated by the post-oxidation process on the tunnel current characteristics can be significantly reduced. It can be seen that the device characteristics are improved.

Further, since the large gate bird's beak is formed on the side of the first insulating film, the capacitance between the silicon substrate and the floating gate is reduced, and the potential of the floating gate determined by the capacitive coupling with the control gate is increased. This means that when the entire device is viewed as an FET, the increase in the threshold voltage due to the thick oxide film is relatively compensated.

On the other hand, when the gate bird's beak is formed on the second insulating film side, it causes variations in the potential of the floating gate, and apparently causes variations in the threshold voltage. Therefore, by reducing the gate bird's beak on the second insulating film side, it is possible to reduce variations in device characteristics.

To obtain the structure shown in FIG. 1, a concentration gradient is applied to the polycrystalline silicon film forming the floating gate 4. That is, in the polycrystalline silicon floating gate 4, the side 4a in contact with the first gate insulating film 3 has a high impurity concentration, and the side 4b in contact with the second gate insulating film 5 has a low impurity concentration. Such a concentration distribution can be formed by sequentially stacking polycrystalline silicon films having different concentrations or by ion implantation and diffusion with different acceleration voltages.

Next, a method of manufacturing this semiconductor memory device will be described with reference to FIGS. After forming a normal element isolation structure (LOCOS or trench element isolation) on the P-type single crystal silicon substrate 1, the thermal oxide film 3 is formed on the active region for forming the element under an atmosphere containing a small amount of hydrochloric acid. 1
Then, a polycrystalline silicon layer 4 containing phosphorus (P) at a high concentration is deposited to a total thickness of about 1500 Å. With respect to the phosphorus concentration, a concentration gradient that is higher on the lower surface side 4a and lower on the upper surface side 4b is provided by the method described above. This concentration gradient does not necessarily have to be smooth, and may be stepwise. It is 10 ²⁰ cm ^-3 or more on the lower surface side and 10 ¹⁹ cm ^-3 on the upper surface side.
The following is acceptable.

Next, this polycrystalline silicon is oxidized to form a second oxide film 5 of about 200 Å as shown in FIG. Generally, a thermal oxide film on silicon with a low impurity concentration is said to have high reliability, but insulating film characteristics,
A so-called ONO film may be formed by sandwiching a silicon nitride film or the like in order to improve reliability, and other improvements may be made to the insulating film. In addition, it is possible to use a deposited oxide film in order to avoid the thermal process as much as possible so that the concentration distribution in the floating gate does not change.

Subsequently, a polycrystalline silicon film 6 having the same impurity concentration as that of the upper side 4b of the floating gate 4 is formed by about 150.
0 Å is deposited, and a tungsten (W) film is sputtered thereon to about 500 Å, and tungsten silicide (WSi) is formed by thermal reaction.
₂ ) Form the film 7. At this time, instead of tungsten, another material, for example, titanium which is another refractory metal, may be appropriately selected according to the entire thermal process and the required gate resistance value to form titanium silicide.

Next, the laminated control gate, floating gate and the like are patterned by anisotropic etching such as reactive ion etching (RIE) to obtain the structure shown in FIG.

After this, a post-oxidation step is carried out. During this step, the difference in the impurity concentration in the polycrystalline silicon causes a difference in the oxidation rate of the insulating film, so that the gate bird's beak 3a is formed large in the first insulating film 3, which is larger than that in the second insulating film 3. The gate bird's beak 5a is formed small in the insulating film 5. After that, the normal source / drain region 2 is ion-implanted to complete the transistor structure (FIG. 1).
Note that the entire surface may be covered with an oxide film as an interlayer insulating film before post-oxidation, and post-oxidation may be performed thereafter.

As described above, by providing a concentration gradient to the polycrystalline silicon forming the floating gate, it is possible to manufacture a highly integrated non-volatile semiconductor memory having high reliability and small variations in element characteristics. In addition, P on the N-type substrate
In the case of a P-channel transistor having a source and a drain of the same type, the same method can be applied only by changing the dopant to the opposite conductivity type.

In FIG. 5, instead of adjusting the amount of formation of the gate bird's beak depending on the impurity concentration of the floating gate, the interface where the floating gate 4 is in contact with the second insulating film 5 and the second insulating film 5 are controlled. Nitride films 8a and 8a are formed at the interface with the gate 6, respectively.
It is sectional drawing of the Example which formed 8b. In this case, almost no gate bird's beak is formed at the interface where the nitride film is formed in the post-oxidation step.

On the other hand, since no nitride film is formed at the interface between the first insulating film 3 and the lower surface side of the floating gate, a large gate bird's beak is formed as in the case of FIG. Therefore, the tunnel current avoids this part,
Since it flows through the highly reliable insulating film portion in the central portion of the channel region, stable tunnel current characteristics can be obtained.

To obtain such a structure, the floating gate 4
After depositing polycrystalline silicon for forming the film, nitriding is performed to form a nitride film 8a having a thickness of 10 Å. Next, a silicon oxide film is deposited by the CVD method to obtain the second insulating film 5. Here, after nitriding the surface thereof to form a nitride film 8b, polycrystalline silicon having the same impurity concentration as that of the floating gate 4 is deposited, and then the control gate 6 and the tungsten silicide are formed in the same manner as in FIG. In the structure in which the film 7 is formed, the fluctuation of the threshold voltage is reduced by suppressing the gate bird's beak on the upper surface of the floating gate,
In addition, it is possible to obtain a nonvolatile semiconductor memory device having stable tunnel current characteristics.

[0031]

As described above, according to the present invention,
It is possible to obtain a non-volatile semiconductor memory device having excellent element characteristics and excellent in high integration while ensuring long-term reliability.

[Brief description of drawings]

FIG. 1 is an element cross-sectional view showing an embodiment of a nonvolatile semiconductor memory according to the present invention.

FIG. 2 is an element-by-step cross-sectional view showing a manufacturing process of a nonvolatile semiconductor memory device according to the present invention.

FIG. 3 is an element-by-step cross-sectional view showing a manufacturing process of a nonvolatile semiconductor memory device according to the present invention.

FIG. 4 is a cross-sectional view of elements for each step showing the manufacturing process of the nonvolatile semiconductor memory device according to the present invention.

FIG. 5 is an element cross-sectional view showing another embodiment of the nonvolatile semiconductor memory device according to the present invention.

[Explanation of symbols]

 1 Silicon Substrate 1a Channel Region 2 Source and Drain Region 3 First Insulating Film 3a Gate Bird's Beak on First Insulating Film Side 4 Floating Gate 4a Region with High Floating Gate Impurity Concentration 4b Region with Low Floating Gate Impurity Concentration 5 Second insulating film 5a Gate bird's beak on second insulating film side 6 Control gate 7 Tungsten silicide film 8a First nitride film 8b Second nitride film

Claims (3)

[Claims] 1. A nonvolatile semiconductor memory device having a stacked structure in which a first insulating film, a floating gate, a second insulating film, and a control gate are sequentially stacked on a channel region formed on the surface of a semiconductor substrate. 2. The nonvolatile semiconductor memory device according to claim 2, wherein the increase in the film thickness at the end of the second insulating film with respect to the center is smaller than the increase in the film thickness at the end of the first insulating film with respect to the center. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the floating gate has a high impurity concentration gradient on the first insulating film side and a low impurity concentration gradient on the second insulating film side. And a nonvolatile semiconductor memory device. 3. The non-volatile semiconductor memory device according to claim 1, wherein a nitride film is formed on each of the interface between the floating gate and the second insulating film and the interface between the control gate and the second insulating film. A non-volatile semiconductor memory device comprising: