JPH07250079A - Packet data comparator circuit - Google Patents

Abstract

PURPOSE:To reduce the circuit scale of a packet data comparator circuit for comparing the successively and serially inputted packet data of two systems. CONSTITUTION:In a latch circuit 11, the data for one packet of the packet data of a first system are fetched and outputted as serial data. The packet data of a second system are compared with the output serial data of the latch circuit 11 one by one packet by a comparator 12. The phase difference of the packet data by the first and second systems is detected by the compared result of each packet and the detected phase difference is adjusted. Thus, since the serial data are processed as they are and phases are compared, the circuit scale is made small.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packet data comparison circuit, and more particularly to a circuit for comparing active packet data and standby packet data when a packet communication transmission line is duplicated.

[0002]

2. Description of the Related Art Generally, ATM (Asyncrono)
When a packet communication transmission line such as a U.S. Transfer Mode) is duplicated, it is necessary to always match the phases of the packet data of the two systems of 0 system and 1 system.
This uses one of the 0 system and the 1 system as the current system and the other as the spare system.
This is because when a failure occurs in the active system, it is necessary to switch to the standby system, and it is necessary to match the phases of both systems when switching.

Conventionally, in this type of packet data comparison circuit, the packet data of two systems of 0 system and 1 system are serial-parallel converted and then the two are compared. The conventional comparison circuit will be described with reference to FIG.

In FIG. 6, the conventional packet data comparison circuit is advanced among two systems, and n-stage shift registers 21 and 22 for converting n-bit serial packet data into n-bit parallel data. N D-type flip-flops 23 for latching parallel data of the side system
And n comparators 24 for comparing the latched data and the delayed data on a bit-by-bit basis,
N-input OR circuit 2 that takes the logical sum of the comparison results for each bit
5 is included. The comparator 24 is composed of n exclusive OR circuits provided corresponding to the n D-type FFs 23, and the output of the corresponding D-type FF 23 is input to one input of each exclusive-OR circuit. Input and n for other input
The output of the stage shift register 22 is input.

In such a configuration, the n-bit serial packet data of the advancing system and the lagging system are converted into parallel data in packet units by the n-stage shift registers 21 and 22, respectively. Then, the arbitrary packet data of the advanced system latched by the latch clock and the packet data of the delayed system are sequentially compared bit by bit. The comparison result of each bit is the n-input OR circuit 25.
Is ORed and output as a comparison result in packet units.

With the above configuration, if the contents of the packets to be compared are not the same, the comparison result for at least one bit indicates a mismatch. On the other hand, if the contents of the packets are the same, it indicates that all the comparison results match. Therefore, if there is a phase difference between the packets, the comparison result at the start of comparison indicates a mismatch, but if the number of pulses output from the OR circuit 25 is counted from that time until the comparison result indicates a match, the packet will be The phase difference between them can be detected. Specifically, the output of the OR circuit 25 may be counted by a counter circuit or the like. Then, if an empty packet is inserted into the system that advances according to the detected phase difference, the phase difference between both systems can be eliminated.

Here, it is not possible to identify the advanced system of the two systems. Therefore, a method is considered in which one of the systems is regarded as an advancing system and the comparison is started, and if the comparison result shows no agreement after a certain period of time, the other is regarded as an advancing system and the comparison is performed again. Conceivable. To switch between the two systems, a selector capable of exchanging the two systems with each other for output can be provided in the preceding stage of the comparison circuit (FIG. 6) and the switching can be controlled. For a certain fixed time, it is controlled by switching the selector by measuring a fixed time with a timer by software or detecting that the maximum value of the phase difference (for example, 600 cells) is exceeded.

The detection of the phase difference and the like are mainly performed when the apparatus is started up, but are also performed when out of synchronization occurs during the operation of the apparatus.

[0009]

The above-mentioned conventional packet data comparison circuit converts the packet data into parallel data packet by packet and then compares the bits with each other. D-type FF, n comparators and n-input OR circuit are required.
There is a drawback that the circuit scale becomes large.

Here, there is Japanese Patent Laid-Open No. 63-279632 as a known technique for comparing bits, but only the coincidence between the bits is detected and the phase difference between the two systems cannot be detected.

The present invention has been made to solve the above-mentioned drawbacks of the prior art, and an object thereof is to provide a packet data comparison circuit capable of reducing the circuit scale.

[0012]

A packet data comparison circuit according to the present invention is a packet data comparison circuit for comparing packet data of a first system and a second system, which are serially input sequentially, with each other. A latch circuit for taking in and outputting one packet of data of the packet data of the above system as serial data, and a comparing means for comparing the packet data of the second system with the output serial data of the latch circuit one packet at a time. And the phase difference between the packet data in the first and second systems is detected based on the comparison result for each packet.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a packet data comparison circuit according to the present invention. In the figure, a packet data comparison circuit according to an embodiment of the present invention includes a latch circuit 11 for holding one packet of serial data of the advancing system as serial data, and a serial data of a system delayed from this latch output. And a comparator 12 that compares each packet one by one, a compression circuit 13 that compresses the comparison result by ORing the comparison result with the comparison result delayed by a predetermined bit, and the number of output pulses of this compression circuit. And a determination circuit 14 for determining.

The latch circuit 11 is used to select the n-bit packet data 10 of the advanced system selected by the select signal.
It is composed of a 2-1 selector 15 that outputs 0 and an n-stage shift register 16 that receives the output 110 of this selector as an input and latches one packet of n-bit packet data. After the shift register 16 holds the data for one packet, the selector 15 is switched by the select signal 111, and the data for one packet is always output serially from the selector 15.

The comparator 12 compares the output 110 of the selector 15 in the latch circuit 11, that is, one packet of data with the delayed serial data 200 in bit units, and is a well-known exclusive logic. It is composed of a sum circuit.

The compression circuit 13 outputs the output 120 of the comparator 12.
A 3-bit delay circuit 17 for delaying 3 bits, an OR circuit 18 for taking a logical sum of the delayed output 170 and the output 120 of the comparator 12, and an AND circuit for taking a logical product of the logical sum output and the compression timing pulse. And 19 are included. Here, when the comparison result indicates coincidence, the output 120 of the comparator 12 is all "L" and the output 180 of the OR circuit 18 is all "0". In contrast,
If the comparison result shows a mismatch, the output 120 of the comparator 12
Is not all "L", and any one bit is "H". As a result, the output 180 of the OR circuit 18 is not all "L". Therefore, it can be determined whether or not the comparison result by the comparator 12 is the same, depending on whether or not the output 180 of the OR circuit 18 is all "L".

The judgment circuit 14 outputs the output 13 of the compression circuit 13.
Input of reset pulse for each packet set by 0 1
The S-R FF 20 is reset by 41, and the AND circuit 26 that takes the logical product of the output 143 and the determination timing pulse 142. The output 140 of the determination circuit 14 becomes the final output of the packet data comparison circuit, and the number of output pulses is counted by a counter circuit (not shown) or the like. Then, by inserting the number of empty packets corresponding to the detected phase difference into the advancing system, the phase difference between both systems can be eliminated.

Next, the operation of the circuit shown in FIG. 1 will be described with reference to the drawings.

FIG. 2 is a time chart showing the operation of each part of the circuit of FIG. 1, and the same parts as in FIG. 1 are designated by the same reference numerals.

In this example, the latched n of the advanced system
The packet data of bits is packet A, and the phase difference between the advanced system and the delayed system is 2 packets.

Normally, the latch circuit 11 outputs the select signal 11
By 1, the input b of the 2-1 selector 15 is selected only when the packet is taken in from the advancing system, and the input a is selected otherwise. Therefore, the select signal 111
In response to the input of, the latch circuit 11 selects the input b and fetches the data of the advancing system for one packet. Once the packet A is taken into the latch circuit 11, the packet A is shifted by n bits by the n-stage shift register 16 (Q
1 to Qn), and its output 160 is input again to the n-stage shift register 16 via the 2-1 selector 15. By this feedback operation, the output 110 of the latch circuit 11 (the output of the 2-1 selector 15) is always in the packet A (abc ... fg).
h).

In the comparator 12, the output 11 of the latch circuit 11
The bitwise exclusive OR of 0 and the delayed data 200 is taken, and the packets are sequentially compared. That is, the packet A in the figure is the data 20 of the delayed system.
0 packets Y, Z ... Are compared bit by bit.

Output 1 which is the comparison result in the comparator 12.
20 is delayed by 3 bits by the delay 17 in the compression circuit 13 and is logically ORed with the delayed output 170. Then, the result of the logical product of the logical sum output and the compression timing pulse 131 is input to the determination circuit 14 as an output 130 and set in the SR type FF 20.

At this time, since the packet A latched in the latch circuit 11 and the delayed packet Y do not match, at least one bit of the output 130 does not match. Therefore, the output of the final comparison result 140 becomes "H" due to the input of the determination timing pulse 142, indicating a mismatch. Immediately after that, the SR FF 20 is reset by the input of the reset pulse 141 for each packet.

When the packet A and the packet Z are compared with each other, the two do not match, so the output 130 is at least one of them.
Bits do not match. Therefore, the output 140 becomes "H", indicating a mismatch.

On the other hand, when the latched packet A and the delayed packet A are compared, they match each other, so that all the bits of the output 130 match. Therefore, the output of the final comparison result 140 becomes “L” by the input of the determination timing pulse 142, which indicates a match. Immediately after that, the SR FF 20 is reset by the input of the reset pulse 141 for each packet.

Here, paying attention to the output 130 of the compression circuit 13, the output 130 has an "L" section for 3 clocks between the comparison results for 1 packet. This is provided to secure the reset timing by the reset pulse 141 for each packet and to clarify the boundary between the packets. In order to provide the “L” section for 3 clocks, the compression timing pulse 131 as shown in the figure is generated, and the comparison result (n
Bit) must be compressed to (n-3) bits,
The generation method will be described later.

As described above, the output 140 which is the packet comparison result becomes "H" for two pulses, so that "2 packets" which is the phase difference between the leading system and the delayed system can be detected. By inserting these two empty packets into the advancing system, the phase difference between the systems can be eliminated.

Here, the select signal 11 in FIG.
1, a method of generating the compression timing pulse 131, the packet reset pulse 141, and the determination timing pulse 142 will be described.

First, FIG. 3A is a circuit diagram showing an example of a circuit for generating the select signal 111 in FIG. 2, and FIG. 3B is a time chart showing its operation.

This circuit is composed of three D-type FFs 31 to 33.

In such a structure, the start (START) signal 300 for starting the phase comparison is held in the D-type FF 31 at the change timing of the cell pulse CP having a cycle equal to the length of one packet. Then, the output signal 310 is held in the D-type FF 32 in response to the input of the clock pulse for each bit. Furthermore, the output signal 320 is output to the D-type FF at the change timing of the cell pulse CP.
Hold at 33. By resetting the D-type FF 31 with this output signal 330, the select signal 111 having a pulse width equal to the length of one packet can be obtained.

Next, FIG. 4 is a circuit diagram showing an example of a circuit for generating the determination timing pulse 142, the packet reset pulse 141 and the compression timing pulse 131 in FIG. 2, and FIG. 5 shows the operation thereof. It is a time chart. In FIG. 4, the same parts as those in FIG. 3A are indicated by the same reference numerals.

This circuit is composed of D-type FFs 41 and 43, an AND circuit 42, an inverter 40, an OR circuit 47, and D-type FFs 44 to 46 connected in three stages.

In such a structure, the cell pulse CP is held in the D-type FF 41 in response to the input of the clock pulse. The determination timing pulse 142 is obtained by taking the logical product of the output signal 410 and the cell pulse CP.

Further, the determination timing pulse 142 is held in the D-type FF 43 at the change timing of the clock pulse CK. The output is a reset pulse 141 for each packet
Becomes

Further, the inverted signal 400 of the cell pulse CP from the inverter 40 is held in the D-type FFs 44, 45 and 46 in sequence at the change timing of the clock pulse CK.
Then, the compression timing pulse 131 is obtained by changing as signals 440, 450, and 460 and taking the logical sum of the signal 460 and the signal 400. The compression timing pulse 131 has an “L” section for 3 clocks between “H” sections, which is to secure the reset timing by the per-packet reset pulse 141.

That is, the comparison result (n bits) for one packet is (n-
3) Compress to bits and FF for each packet of comparison result
20 is being reset.

Obviously, more "L" sections may be provided instead of three clocks. In this case, a delay circuit according to the number of clocks may be provided. Even if the interval is less than 3 clocks, there is no problem if the reset timing can be secured and the boundary between the packets becomes clear.

As described above, in this embodiment, since the serial data is processed as it is and the phase is compared, the conventional circuit (FIG. 6) is used.
N bit shift register, n input OR circuit,
(N-1) exclusive OR circuits and n D-type Fs
F can be reduced and the circuit scale can be reduced.

Since it is not possible to identify the advanced system of the two systems, one of the two systems is regarded as the advanced system and the comparison is started in the same manner as in the conventional system, and a certain period of time elapses. However, if the comparison results do not show a match, the other is regarded as a system in progress and the comparison is repeated. To switch between these two systems, a selector capable of switching between the two systems and outputting them is provided in the preceding stage of the comparison circuit (FIG. 1), and this switching control may be performed. For a certain fixed time, it is controlled by switching the selector by measuring a fixed time with a timer by software or detecting that the maximum value of the phase difference (for example, 600 cells) is exceeded. The detection of the phase difference and the like are mainly performed when the apparatus is started up, but are also performed when out of synchronization occurs during operation of the apparatus.

[0043]

As described above, according to the present invention, since serial data are processed and compared with each other, the circuit scale can be reduced. Further, since the comparison result is compressed, the boundaries between the packets are clarified, and the phase difference can be reliably detected.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a packet data comparison circuit according to an embodiment of the present invention.

FIG. 2 is a time chart showing the operation of the packet data comparison circuit of FIG.

3A is a circuit diagram showing an example of a circuit for generating the select signal in FIG. 2, and FIG. 3B is a time chart showing its operation.

4 is a circuit diagram showing an example of a circuit for generating a determination timing pulse, a reset pulse for each packet, and a compression timing pulse in FIG.

5 is a time chart showing the operation of the circuit of FIG.

FIG. 6 is a block diagram showing a configuration of a conventional packet data comparison circuit.

[Explanation of symbols]

 12 comparator 15 n-stage shift register 16 2-1 selector 17 delay circuit 18 OR circuit 19 AND circuit 20 SR type FF

Claims (3)

[Claims] 1. A packet data comparison circuit for comparing packet data of a first system and a packet data of a second system, which are serially input in sequence, wherein the packet data of the first system is 1
A latch circuit for fetching and outputting packet data as serial data and a comparing means for comparing the packet data of the second system with the output serial data of the latch circuit for each packet are provided. The packet data comparison circuit is characterized in that the phase difference between the packet data by the first and second systems is detected based on the result of the comparison. 2. The output of the logical sum means further includes delay means for delaying the comparison result of each packet by the comparing means by a predetermined bit, and logical sum means for logically summing the delayed output and the comparison result. 2. The packet data comparison circuit according to claim 1, wherein the phase difference between the packet data by the first and second systems is adjusted according to the number of pulses. 3. The packet data comparison circuit according to claim 2, further comprising a judging means for judging the number of output pulses of said logical sum means in response to the input of a predetermined judging signal.