JPH07263643A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] [Object] To provide an integrated circuit of a tunnel diode and a compound semiconductor FET, which is small in size and easy to manufacture. A tunnel diode in which a compound semiconductor field effect transistor having a contact layer 2e of a first conductivity type provided on a source region 31 or a drain region 32 and a tunnel diode connected to the contact layer 2e are integrated. Is provided on the contact layer 2e on the source region 31 or the drain region 32, and
The first conductivity type first high concentration layer 3 is a lower layer and the second conductivity type second high concentration layer 4 is an upper layer, and an etch stopper layer is provided between the contact layer 2e and the first high concentration layer 3. 7 is provided, and the etch stopper layer 7, the first and second high-concentration layers 3 and 4 are epitaxially deposited.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a tunnel diode and a compound semiconductor field effect transistor are integrated and a method of manufacturing the same.

Since the compound semiconductor FET (field effect transistor) has a low Hall mobility, the operation speed of the p-type FET is slow, and it is not possible to fabricate a complementary circuit that operates at high speed. Therefore, an attempt has been made to combine a n-channel FET and a negative resistance element to form a high-speed circuit with low power consumption.

In particular, the tunnel diode is known as a negative resistance element which is excellent in high-speed switching characteristics and has a simple structure and is easy to manufacture. It is a high-speed n-type FET HEMT.
It is expected to realize a high-speed integrated circuit in combination with (High Electron Mobility Transistor).

Therefore, there is a need for a semiconductor device in which a tunnel diode and a compound semiconductor FET are integrated in a small area and which is easy to manufacture, and a manufacturing method thereof.

[0005]

2. Description of the Related Art Since a tunnel diode has a simple structure, it may be easily manufactured even if it is integrated. Conventionally, a semiconductor device in which a silicon FET and a tunnel diode are integrated has been devised. On the other hand, compound semiconductor F
The integration of the ET and the tunnel diode is difficult due to the inherent difficulty in the manufacturing process of the compound semiconductor device.
As with T, integration is not easy.

A structure of a semiconductor device in which a conventional tunnel diode and a compound semiconductor FET are integrated and a manufacturing method thereof will be described below. FIG. 7 is a cross-sectional view of a conventional example and shows a semiconductor device in which a compound semiconductor FET and a tunnel diode are integrated on the same substrate.

First, referring to FIG. 7, a channel layer 2a, an electron supply layer 2b, a contact thin layer 2c, a stopper layer 2d are formed on an insulating semiconductor substrate 1 as a transistor forming layer 2 which becomes a semiconductor forming an FET. , Are sequentially deposited.

Next, a transistor formation region and a tunnel diode formation region are defined, and an element isolation band 8 for insulatingly isolating each region is formed. At this time, the contact layer 2e in the tunnel diode formation region is insulated and separated and acts as a buried layer having a high impurity concentration.

Next, the first high concentration layer 3 and the second high concentration layer 4 forming the pn junction of the tunnel diode are deposited on the tunnel diode formation region by selective epitaxial growth using a mask.

Next, an insulating film 9 is deposited and the gate electrode 5
The contact layer 2e, the stopper layer 2d, and the contact thin layer 2c in the formation region are etched to form an electron supply layer 2b on the bottom surface.
Forming a groove that exposes After that, the gate electrode 5 is formed by lift-off.

Next, after opening a window in the insulating film 9, by lift-off, the source wiring 11 ohmic-connected to the source region 31 and the drain wiring ohmic-connected to the drain region 32 and the buried layer 6 and electrically connected to each other. 1
Form 2. After that, the wiring 10 for ohmic connection is formed on the second high concentration layer 4 to manufacture a semiconductor device.

In the above-described conventional semiconductor device, since the FET and the tunnel diode are formed in separate element isolation regions, the reduction of the area of the element is limited, and sufficient integration cannot be realized. Further, since the first and second high concentration layers 3 and 4 constituting the tunnel diode are deposited by selective epitaxial growth, the process is complicated and it is difficult to deposit an epitaxial layer having good crystallinity. .

In order to solve such a problem and improve the integration degree of a semiconductor device, Watanabe et al. Have made an attempt to form a negative resistance element on a formation region of a compound semiconductor FET in a superposition manner. 9 (1993-04). There, a resonant tunneling diode was used as the negative resistance element and a HEMT was used as the FET.

However, the resonant tunneling diode is
Forming on T requires an extremely complicated structure and a complicated and delicate manufacturing process, and has not yet been put to practical use.

[0015]

As described above, in the structure of the conventional semiconductor device, separate element isolation regions are required to integrate the compound semiconductor FET and the negative resistance element, which is sufficient. There is a drawback that it is difficult to reduce the area. Further, since the semiconductors forming the tunnel diode are deposited by the selective epitaxial growth method, the manufacturing process is complicated, and since the semiconductor having good crystallinity cannot be deposited, the characteristics of the tunnel diode are deteriorated.

The present invention epitaxially grows a semiconductor forming an etch stopper layer and a tunnel diode on a transistor forming layer which is a compound semiconductor forming an FET, forms a tunnel diode by selective etching, and then forms the FET. Manufactured, F
A semiconductor device in which a tunnel diode is arranged on the ET can be manufactured without using a selective epitaxial process,
An object of the present invention is to provide a high-speed compound semiconductor device having excellent electrical characteristics, easy to manufacture, and highly integrated, and a manufacturing method thereof.

[0017]

FIG. 1 and FIG. 2 are sectional process views of a first embodiment of the present invention, and FIG.
2 shows a cross-sectional structure of a part of the circuit. FIG. 3 is a plan view of the first embodiment of the present invention, and shows a planar layout of a part of the circuit of FIG. 4A of the semiconductor device. FIG. 4 is a circuit diagram of an embodiment of the present invention and shows a combination circuit of a compound semiconductor FET and a tunnel diode. Note that Fig. 1
2 is a cross-sectional view taken along line AB in FIG.

FIGS. 5 and 6 are sectional process drawings of the second embodiment of the present invention, showing the sectional structure of the circuit portion of the semiconductor device shown in FIG. 4 (a). A first configuration of the present invention for solving the above-mentioned problem is that a contact layer 2e of a first conductivity type is provided on a source region 31 or a drain region 32 with reference to FIGS. 2 (f) and 3. In a semiconductor device in which a compound semiconductor field effect transistor and a tunnel diode electrically connected to the contact layer 2e are integrated on the same substrate 1, the tunnel diode includes the source region 3
1 or the contact layer 2e directly above the drain region 32
A first high-concentration layer 3 made of a semiconductor of the first conductivity type is provided as an upper layer, and a second high-concentration layer 4 made of a semiconductor of a second conductivity type opposite to the first conductivity type is an upper layer. Pn
An etch stopper layer 7 made of a compound semiconductor of the first conductivity type is provided between the contact layer 2e and the first high-concentration layer 3 and has a junction. The one high-concentration layer 3 and the second high-concentration layer 4 are characterized in that they are epitaxial layers deposited on the contact layer 2e, and the second constitution is the semiconductor device of the first constitution. 2 is characterized in that the etch stopper layer 7 has a wider band gap than the first high concentration layer 3 and the second high concentration layer 4 and is made of a compound semiconductor containing Al, and In the third structure, referring to FIG. 6E, a compound semiconductor field effect transistor in which a contact layer 2e of the first conductivity type is provided on the source region 31 or the drain region 32, and the contact layer 2e Electrical connection to In a semiconductor device in which a diode is integrated on the same substrate 1, a semiconductor of a second conductivity type, which is provided on the contact layer 2e immediately above the source region 31 or the drain region 32 and is opposite to the first conductivity type A second high-concentration layer 4 made of a metal, and an etch stopper layer 7 made of a first-conductivity-type compound semiconductor provided between the contact layer 2e and the second high-concentration layer 4. The layer 7 and the second high-concentration layer 4 are characterized in that they are epitaxial layers deposited on the contact layer 2e, and the fourth structure is a method for manufacturing a semiconductor device of the third structure. The etch stopper layer 7 has a forbidden band width wider than those of the contact layer 2e and the second high-concentration layer 4, and is made of a compound semiconductor containing Al. The configuration of 1, with reference to FIGS. 2 and 3, in the manufacturing method of the semiconductor device of the first or second configuration, on the substrate 1, consisting of the contact layer 2e of a compound semiconductor and uppermost transistor forming layer 2
And a step of depositing the etch stopper layer 7, the first high concentration layer 3, and the second high concentration layer 4 on the contact layer 2e in this order, and the etch stopper layer 7 The first high-concentration layer 3 forming the tunnel diode on the region where the source region 31 or the drain region 32 is to be formed by selective etching serving as a stopper.
And a step of removing the other first high-concentration layer 3 and the second high-concentration layer 4 while leaving the second high-concentration layer 4;
An etching step of removing the etch stopper layer 7 exposed to the outside of the first high concentration layer 3 using the first high concentration layer 3 and the second high concentration layer 4 as a mask. And the sixth structure is the method for manufacturing a semiconductor device having the third or fourth structure, wherein the transistor formation layer 2 made of a compound semiconductor having the contact layer 2e as the uppermost layer is deposited on the substrate 1. The step of depositing the etch stopper layer 7 and the second high-concentration layer 4 on the contact layer 2e in this order, and the selective etching using the etch stopper layer 7 as a stopper. The second high-concentration layer 4 forming the tunnel diode on the region where the source region 31 or the drain region 32 is to be formed.
And the other second high-concentration layer 4 is removed to form the tunnel diode composed of the contact layer 2e, the etch stopper layer 7, and the second high-concentration layer 4, and then, And an etching step of removing the etch stopper layer 7 exposed to the outside of the second high concentration layer 4 by using the second high concentration layer 4 as a mask, and a seventh configuration In the method of manufacturing a semiconductor device having the fifth or sixth configuration, after the etching step of removing the etch stopper layer 7, a step of forming an element isolation band 8 that defines a formation region of the field effect transistor. ，
Then, using a resist mask 16 having an opening 13 that defines the gate electrode 5 of the field effect transistor, a groove for dividing the contact layer 2e into the source region 31 and the drain region 32 is formed on the surface of the transistor formation region. It is characterized in that it has a step of forming and then a step of forming the gate electrode 5 on the groove by lift-off.

[0019]

In the first structure of the present invention, referring to FIGS. 1 and 2, the tunnel diode is formed on the source or drain region (31, 32) of the FET. Therefore, it is not necessary to provide a region for element isolation for the tunnel diode, and the element formation area can be reduced, so that the degree of integration is improved.

The tunnel diode is composed of the first high-concentration layer 3 and the second high-concentration layer 4 which are epitaxially deposited with the etching stopper layer 7 epitaxially deposited on the contact layer 2e of the FET as a deposition surface. It
Therefore, the first high-concentration layer 3 forming the tunnel diode
The second high-concentration layer 4 has excellent crystallinity, and a tunnel diode having excellent characteristics is manufactured.

Further, in this structure, the etch stopper layer 7 is provided between the first high concentration layer 3 and the contact layer 2e. In this configuration, the first high concentration layer 3 and the second high concentration layer 4
When etching the tunnel diode to form a tunnel diode,
Contact layer 2e which is the outermost layer of the transistor formation layer 2
Since there is no damage or etching, the FET manufacturing process can be performed after the tunnel diode is manufactured. Therefore, the tunnel diode can be manufactured by patterning the semiconductor epitaxially grown on the entire surface of the transistor forming layer provided on the substrate. As a result, it is possible to manufacture a semiconductor device in which a semiconductor having a good crystallinity that constitutes a tunnel diode is deposited by a simple process and integrated with an FET while maintaining the crystallinity, as compared with the case of using selective epitaxial growth.

In the third structure of the present invention, referring to FIG. 6 (e), in the first structure, a first high concentration layer 3 forming a tunnel diode and a contact layer 2e forming a transistor forming layer are formed. Is common.

In this configuration, as in the first configuration, the etch stopper layer 7 epitaxially deposited on the contact layer 2e is used, and the second high-concentration layer 4 epitaxially deposited thereon is etched and patterned. To do. Therefore, the tunnel diode is composed of a pn junction formed between the contact layer 2e and the second high-concentration layer 4 with the etch stopper layer 7 interposed therebetween.

Such a tunnel diode in which different kinds of semiconductor layers are sandwiched between pn junctions can increase the operating voltage and is particularly suitable for being incorporated in a logic integrated circuit to output a necessary logic amplitude. Further, in this configuration, it is sufficient to deposit one second high-concentration layer 4 on the etch stopper layer 7 and pattern it. Therefore, two layers of the first high-concentration layer 3 and the second high-concentration layer 4 are patterned. It is easier to manufacture than the first configuration. It is the same as in the first embodiment described above that the device area can be reduced, ease of manufacture, and excellent tunnel diode characteristics can be maintained.

In the second configuration or the fourth configuration of the present invention,
The etch stopper layer 7 has a wider band gap than the other semiconductor layers forming the tunnel diode and is made of a compound semiconductor containing Al. Since such a semiconductor layer serves as an effective stopper for etching a semiconductor layer having a narrow forbidden band, it is possible to reliably perform etching. The fourth configuration also has the above-described effect of increasing the operating voltage of the tunnel diode.

A fifth structure of the present invention relates to a method for manufacturing a semiconductor device having the first and second structures, and a sixth structure relates to a method for manufacturing a semiconductor device having the third and fourth structures. In the fifth and sixth configurations, referring to FIG. 1 or 5, first, the transistor formation layer 2 is deposited, and the etch stopper layer 7 and the semiconductor layer constituting the tunnel diode are epitaxially formed on the transistor formation layer 2, that is, the fifth configuration. In the configuration, the first and second high-concentration layers 3, 4, and in the sixth configuration, the second high-concentration layer 3 is sequentially deposited. Since all of these layers may be uniformly deposited on the entire surface of the substrate 1, a semiconductor layer having good crystallinity is produced as compared with selective epitaxial growth.

Then, the semiconductor layer forming the tunnel diode is patterned by etching using the etch stopper layer 7 as a stopper to manufacture the tunnel diode. Since this tunnel diode consists of a semiconductor layer patterned by etching, crystal defects are not introduced during deposition and processing, and excellent characteristics can be maintained.

Next, the etch stopper layer 7 exposed on the outside of the tunnel diode is removed and the transistor formation layer 2 is exposed, so that the FET can be manufactured thereafter in accordance with the normal FET manufacturing process. For example, the seventh configuration can be used for this step. Since the etch stopper layer 7 protects the transistor forming layer in the tunnel diode forming step, the FET characteristics are not impaired by the tunnel diode manufacturing step. Therefore, a semiconductor device in which elements having excellent characteristics are integrated in both the tunnel diode and the FET is manufactured.

Further, in these structures, as in the usual semiconductor device manufacturing process, selective epitaxial is not used,
Since the semiconductor layer is formed by epitaxial deposition and etching on the entire surface of the substrate, it can be easily applied to the normal manufacturing process. Furthermore, the manufacturing process is simple and does not require a process that requires fine adjustment, so that the manufacturing is easy and the reliability is high.

The seventh structure relates to a method of manufacturing a semiconductor device suitable for manufacturing an FET after manufacturing a tunnel diode in the fifth or sixth manufacturing method. With this configuration,
A tunnel diode is manufactured by the fifth or sixth method, the transistor formation layer 2 is exposed, and then an element isolation band is formed with reference to FIG. 1C or 5B. Such an element isolation band is formed, for example, by using the resist mask 15 as an FET.
Can be formed by implanting oxygen ions or forming trenches. Since the tunnel diodes according to the fifth and sixth configurations are in the FET formation region, this configuration protects the FET formation region as well as the tunnel diode at the same time, requiring a special step for tunnel diode protection. Not.

Next, referring to FIG. 2E or FIG. 6D, an insulating film 9 and a resist are applied, an opening 13 for defining the gate electrode 5 is provided in the resist and the insulating film 9, and the opening 13 is formed. A trench is formed in the bottom contact layer 2e to divide the source and drain. After that, the gate electrode 5 is formed by lift-off, and the FET is manufactured.

The above-mentioned method of forming a FET is similar to the method of forming a normal compound semiconductor, and the semiconductor device having the first to fourth structures of the present invention is used in a normal FET manufacturing process after forming a tunnel diode. Since it can be formed in the same process, it has excellent adaptability to conventional processes.

[0033]

EXAMPLES The present invention will be described with reference to examples. The first embodiment of the present invention relates to a method of manufacturing a semiconductor device having the first and second configurations, and relates to manufacturing of an inverter circuit having a negative resistance element as a load shown in FIG. Fig. 4
Inside, TD is a tunnel diode and TR is a field effect transistor.

Referring to FIG. 1 (a), a semi-insulating compound semiconductor substrate 1, a GaAs substrate, a channel layer 2a, an electron supply layer made of a compound semiconductor in the following order, for example, by the MBE method or the MOCVD method. The transistor forming layer 2 is formed by epitaxially depositing 2b, the contact thin layer 2c, the stopper layer 2d, and the contact layer 2e.

The channel layer 2a is made of intrinsic semiconductor GaAs having a thickness of 200 nm, for example, and a channel is formed under the gate electrode by the two-dimensional electrons supplied from the electron supply layer.

The electron supply layer 2b is made of a semiconductor having an electron affinity lower than that of the channel layer 2a, for example, n-type AlGaAs having a thickness of 30 nm and a carrier concentration of 2 × 10 ¹⁸ cm ^-3 , and supplies electrons to the channel layer 2a.

The contact thin layer 2c has a thickness of 8 nm, for example.
It ^consists of n-type GaAs with a carrier concentration of 2 × 10 ¹⁸ cm ^-3 ,
It is provided to make ohmic contact with the source and drain regions.

The stopper layer 2d is made of n-type AlGaAs having a thickness of 3 nm and a carrier concentration of 2 × 10 ¹⁸ cm ^-3 , for example,
As described later, it acts as an etch stopper when forming the gate electrode.

The contact layer 2e has, for example, a thickness of 80 nm,
It ^consists of n-type GaAs with a carrier concentration of 2 × 10 ¹⁸ cm ^-3 ,
The source and drain are ohmic-connected via the contact thin layer 2c, and further ohmic-connected to the electrode formed on the upper surface thereof to supply and output source and drain currents.

The transistor forming layer composed of the above layers is a normal HEMT (high electron mobility transistor).
It is the same as the forming layer. Next, contact layer 2
In the same manner as the deposition of the transistor forming layer 2 on e,
The etch stopper layer 7 is epitaxially deposited, and further,
The first high concentration layer 3 and the second high concentration layer 4 are epitaxially deposited on the etch stopper layer 7.

The etch stopper layer 7 has a thickness of 3 nm, for example.
It is made of n-type AlGaAs having a carrier concentration of 2 × 10 ¹⁸ cm ⁻³ . The first high concentration layer 3 has a thickness of 80 nm and a carrier concentration of 8 ×
Second high concentration layer 4 ^consisting of 10 ¹⁸ cm ^-3 n-type GaAs
Is a p-type G with a thickness of 80 nm and a carrier concentration of 2 × 10 ¹⁹ cm ^-3.
A pn junction made of aAs and formed of the first high concentration layer 3 and the second high concentration layer 4 constitutes a tunnel diode.

Next, a resist mask 14 that defines a tunnel diode is formed on the second high-concentration layer 4. Next, referring to FIG. 1B, the first high concentration layer 3 and the second high concentration layer 4 are etched using the resist mask 14 as an etching mask and the etch stopper layer 7 as an etch stopper to form a tunnel diode. Form.

Such etching is performed by using a fluorocarbon system such as C
Reactive ion etching using Cl ₂ F ₂ , CHClCCl ₂ F, or a mixture of HF, H ₂ O ₂ and H ₂ O, a mixture of citric acid and H ₂ O ₂ , or ammonia, H ₂ O
It can be performed by selective etching using a mixed solution of ₂ and H ₂ O as an etchant. The etch stopper layer 7 of _the embodiment is AlGaAs, but the same etchant can be used with InGaP.

Then, the etch stopper layer 7 exposed to the outside of the tunnel diode is removed by etching using the first high concentration layer 3 and the second high concentration layer 4 as a mask and the contact layer 2e as an etch stopper. Referring to FIG. 1C, the surface of the contact layer 2e outside the tunnel diode formation region is exposed.

Such etching is performed by using, for example, AlGaA.
The etching stopper layer 7 of s is removed by selective etching using an etchant of a mixed liquid of HF, H ₂ O ₂ and H ₂ O. The InGaP etch stopper layer 7
An aqueous solution of hydrochloric acid is used to remove. Further, in the embodiment, the first high-concentration layer 3, the second high-concentration layer 4 and the contact layer 2e are made of GaAs, but the contact layer 2e may be made of InGaAs having good conductivity.

Then, the resist mask 14 is peeled off.
Next, referring to FIG. 1C, a resist mask 15 that defines a transistor formation region is formed, and oxygen ions are implanted to form an insulating element isolation band 8. At this time, the tunnel diode formed on the drain formation region is covered with and protected by the resist mask 15.

Next, the resist mask 15 is peeled off.
Then, referring to FIG. 2D, for example, a silicon oxynitride (SiO 2) having a thickness of 300 nm is formed on the entire surface of the substrate 1.
N) is deposited using, for example, the plasma CVD method to form the insulating film 9.

Next, the insulating film 9 on the upper surface of the first high concentration layer 4
A contact hole was opened in the first high concentration layer 4 and ohmic contact.
A wiring 10 that makes a contact is formed. Such contour
The formation of ecto-holes is usually done using photoresist.
Etching, eg etching using a hydrofluoric acid-based etchant
Or CF_FourOr CHF₃Reactive Io using
It is done by etching. In addition, p-type GaAs and
The wiring 10 for the ohmic connection is W by, for example, sputtering.
After depositing the W film on the Si thin film, for example, SF ₆Gas
Patterned by the reactive ion etching used
Can be formed.

Next _, referring to FIG. 2E, a resist mask 16 is applied to the entire surface of the substrate 1 and an opening 13 for defining the gate electrode 5 is opened by photolithography. Then, the insulating film 9 exposed on the bottom surface of the opening 13 is removed by reactive ion etching using the resist mask 16 as an etching mask, and the contact layer 2e is formed on the bottom of the opening 13.
Express.

Then, a mixed solution of citric acid and hydrogen peroxide water,
Alternatively, a mixture of ammonia and hydrogen peroxide is used as an etchant, the stopper layer 2d is used as an etch stopper, and the opening 13 is formed.
The contact layer 2e exposed at the bottom of is removed by etching. Alternatively, ion etching using a mixed gas of CCl ₂ F ₂ and He can be used.

Then, the stopper layer 2d exposed at the bottom of the opening 13 is removed with an aqueous ammonia solution or diluted hydrofluoric acid. Further, the contact thin layer 2 exposed at the bottom of the opening 13
c is removed by anisotropic etching using CCl ₂ F ₂ .

As a result of the above steps, referring to FIG. 2E, a groove is formed on the surface of the transistor forming layer 2 exposed on the bottom surface of the opening 13 formed in the resist mask 16. Contact layer 2e, stopper layer 2d, and contact thin layer 2
Referring to FIG. 3, c is divided into two parts by this groove, and a source region 31 and a drain region 32 are formed under each of them.

Next, referring to FIG. 2F, an Al layer having a thickness of 350 nm, for example, is deposited and lifted off together with the resist mask 16 to form the gate electrode 5 in the groove. After that, the resist mask 16 is removed.

Next, the source wiring 11 and ohmic connection to the source region 31 and the drain region 32,
The drain wiring 12 (see FIG. 3) is formed by lift-off, and the FET is manufactured. The source wiring 11 and the drain wiring 12, which are ohmic-connected to the n-type region, are configured by wiring in which Au of 270 nm thick is stacked on AuGe of 30 nm thick, for example.

Since the tunnel diode manufactured in this step is formed on the drain region of the FET with reference to FIG. 3, it does not require an element formation region and can be made compact.
Furthermore, when the tunnel diode shown in FIG. 4A is used in an inverter circuit having a load, wiring between both elements is not required and the element structure can be simplified, which facilitates manufacturing.

The present invention can be applied not only to the inverter circuit but also to the memory cell with reference to FIG. That is, two serially connected tunnel diodes T
The bistable circuit constituted by D and TD2 is driven by the field effect transistor TR having the gate wiring 14 and the source wiring 11 as X and Y wirings, respectively. Furthermore, the present invention can be applied to other circuits that combine an FET and a tunnel diode.

The second embodiment of the present invention relates to a method of manufacturing a semiconductor device according to the third or fourth structure of the present invention. The circuit of this embodiment is the same as that of the first embodiment shown in FIG. 4 (a).

First, for example, MBE is formed on the GaAs substrate 1.
Method, the MOCVD method is used to epitaxially deposit the channel layer 2a, the electron supply layer 2b, the contact thin layer 2c, the stopper layer 2d, and the contact layer 2e to form the transistor formation layer 2.

The contact layer is made of n-type GaAs having a thickness of 80 nm and a carrier concentration of 8 × 10 ¹⁸ cm ^-3 , for example. All other layers are the same as in the first embodiment. Then, for example, n-type AlG having a thickness of 3 nm and a carrier concentration of 2 × 10 ¹⁸ cm ^-3
The etch stopper layer 7 made of aAs is epitaxially deposited.

Next, the thickness is 80 nm and the carrier concentration is 2 × 1.
A second high-concentration layer 4 of 0 ¹⁹ cm ⁻³ of p-type GaAs is epitaxially deposited. Then, the second high-concentration layer 4 is patterned by the same method as in the first embodiment, and the etch stopper layer 7 exposed outside the tunnel diode formation region is removed.

The tunnel diode is composed of a pn junction formed by the patterned second high-concentration layer 4 and the contact layer 2 e sandwiching the etch stopper layer 7. Next, referring to FIG. 5B, oxygen ions are implanted using the resist mask 15 that defines the transistor formation region, and the element isolation band 8 is formed.

Next, referring to FIG. 5C, a silicon oxynitride insulating film 9 is deposited, a contact hole is formed to connect to the second high-concentration layer 4, and a second high-concentration layer is formed thereon. The wiring 10 which makes ohmic contact with the wiring 4 is formed.

Next, referring to FIG. 6D, similarly to the first embodiment, a groove is formed in the resist mask 16 on the surface of the transistor forming layer 2 at the bottom of the opening 13 for defining the gate electrode 5. Form.

Next, referring to FIG. 6E, the gate electrode 5 is formed by lift-off, and the source wiring 11 is formed.
A drain wiring (not shown) is formed by lift-off.

The tunnel diode according to this embodiment is
Since the pn junction includes a layer having a large forbidden width, the operation amplitude is large. In addition, the semiconductor layer forming the tunnel diode is
Since it is thinner than the first embodiment, both the deposition process and the etching process are simple.

[0066]

As described above, according to the present invention, the FE
Since a tunnel diode composed of a semiconductor layer having excellent crystallinity can be formed on T without damaging the FET formation layer, the tunnel diode and the FET having a small area and excellent electrical characteristics are integrated. Since the semiconductor device and the simple manufacturing method thereof can be provided, it greatly contributes to the performance improvement of the semiconductor device.

[Brief description of drawings]

FIG. 1 is a sectional process diagram of the first embodiment of the present invention (No. 1)

FIG. 2 is a sectional process drawing of the first embodiment of the present invention (No. 2)

FIG. 3 is a plan view of the first embodiment of the present invention.

FIG. 4 is a circuit diagram of an embodiment of the present invention.

FIG. 5 is a sectional process drawing of the second embodiment of the present invention (No. 1)

FIG. 6 is a sectional process diagram of the second embodiment of the present invention (No. 2)

FIG. 7 is a sectional view of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 substrate 2 transistor formation layer 2a channel layer 2b electron supply layer 2c contact thin film 2d stopper layer 2e contact layer 3 first high concentration layer 4 second high concentration layer 5 gate electrode 6 burying layer 7 etch stopper layer 8 element isolation band 9 Insulating film 10 Wiring 11 Source wiring 12 Drain wiring 13 Openings 14, 15, 16 Resist mask 31 Source region 32 Drain region

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 29/88 F

Claims (7)

[Claims] 1. A compound semiconductor field effect transistor in which a contact layer (2e) of a first conductivity type is provided on a source region (31) or a drain region (32), and the contact layer (2e) is electrically connected to the compound semiconductor field effect transistor. In a semiconductor device in which a tunnel diode to be connected is integrated on the same substrate (1), the tunnel diode has the contact layer (2) immediately above the source region (31) or the drain region (32).
e) a second high-concentration layer formed of a semiconductor of a second conductivity type opposite to the first conductivity type with a first high-concentration layer (3) of a semiconductor of the first conductivity type provided as a lower layer An etch stopper layer having a pn junction with the layer (4) as an upper layer and made of a first conductivity type compound semiconductor between the contact layer (2e) and the first high-concentration layer (3). (7) is provided, and the etch stopper layer (7), the first high-concentration layer (3) and the second high-concentration layer (4) are epitaxial layers deposited on the contact layer (2e). There is a semiconductor device. 2. The semiconductor device according to claim 1, wherein the etch stopper layer (7) has a wider band gap than the first high concentration layer (3) and the second high concentration layer (4). And a semiconductor device comprising a compound semiconductor containing Al. 3. A compound semiconductor field effect transistor in which a contact layer (2e) of the first conductivity type is provided on a source region (31) or a drain region (32), and electrically to the contact layer (2e). In a semiconductor device in which a tunnel diode to be connected is integrated on the same substrate (1), the source region (31) or the drain region (32)
A second high-concentration layer (4) which is provided on the contact layer (2e) directly above the inside and is made of a semiconductor of a second conductivity type opposite to the first conductivity type, the contact layer (2e) and the second And an etch stopper layer (7) made of a compound semiconductor of the first conductivity type, the etch stopper layer (7) and the second high concentration layer (4). ) Is a semiconductor device characterized in that it is an epitaxial layer deposited on the contact layer (2e). 4. The semiconductor device according to claim 3, wherein the etch stopper layer (7) has a wider band gap than the contact layer (2e) and the second high-concentration layer (4), and A semiconductor device comprising a compound semiconductor containing Al. 5. The method for manufacturing a semiconductor device according to claim 1, wherein a transistor forming layer (2) made of a compound semiconductor having the contact layer (2e) as an uppermost layer is formed on the substrate (1). And a step of depositing the etch stopper layer (7), the first high-concentration layer (3), and the second high-concentration layer (4) on the contact layer (2e) in this order. The source region (31) is formed by a process and selective etching using the etch stopper layer (7) as a stopper.
Alternatively, the first high-concentration layer (3) forming the tunnel diode on the region where the drain region (32) is to be formed.
And a step of removing the other first high-concentration layer (3) and the second high-concentration layer (4) while leaving the second high-concentration layer (4), and then the first high-concentration layer ( And an etching step of removing the etch stopper layer (7) exposed to the outside of 3) using the first high concentration layer (3) and the second high concentration layer (4) as a mask. Of manufacturing a semiconductor device. 6. The method for manufacturing a semiconductor device according to claim 3, wherein a transistor forming layer (2) made of a compound semiconductor having the contact layer (2e) as an uppermost layer is formed on the substrate (1). And a step of depositing the etch stopper layer (7) and the second high-concentration layer (4) on the contact layer (2e) in this order, and the etch stopper layer (7). The source region (31) or the drain region (3
The second high-concentration layer (4) forming the tunnel diode is left on the region where the second high-concentration layer (4) is to be formed, and the other second high-concentration layer (4) is removed, and the contact layer (2e) is removed. ，
Forming the tunnel diode composed of the etch stopper layer (7) and the second high-concentration layer (4);
Next, an etching step of removing the etch stopper layer (7) exposed to the outside of the second high-concentration layer (4) using the second high-concentration layer (4) as a mask. Manufacturing method of semiconductor device. 7. The method of manufacturing a semiconductor device according to claim 5, wherein after the etching step of removing the etch stopper layer (7), an element isolation band defining a formation region of the field effect transistor. Using the step of forming (8) and then a resist mask (16) having an opening (13) defining the gate electrode (5) of the field effect transistor, the contact layer (2e) is formed on the surface of the transistor formation region. 2) is divided into the source region (31) and the drain region (32), and then a gate electrode (5) is formed on the groove by lift-off. Manufacturing method of semiconductor device.