JPH07264004A - Signal processor - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a signal processing technique capable of realizing an improvement in operating speed at lower cost with lower power consumption. A clock generating means C for generating N clocks (C1 to Cn) whose phases are sequentially shifted by a data interval Td.
LK and the input signal Xin are input, and N clocks (C1 to Cn) are input as shift clocks, respectively.
M stage shift register means (SR1 to SRn)
The M outputs of the stage shift register means are latched with a clock sequentially delayed by a data interval Td with respect to the N shift clocks (N-1) sets of N M stage latch means (L1).
(1) to Ln (n-1)), and the N first shift registers that are operated by the same clock and the N first shift registers that receive the output signals of the (N-1) sets of N M stage latches, respectively.
Signal processing means (SP1 to SPn).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to signal processing technology,
In particular, the present invention relates to a technique effective when applied to a magnetic, optical and magneto-optical recording / reproducing device, a digital signal processing device used in a disk array system or the like.

[0002]

2. Description of the Related Art For example, Nikkei BP, January 17, 1994, "Nikkei Electronics No 599" P71-P
As described in the literature such as 97, the digital data recording / reproducing technology is suitable for processing the waveform of a reproduced signal, for example, in response to a request for improving the recording density and the data transfer rate of a medium. It is an important issue to speed up waveform equalization techniques such as partial response (PR) that transforms into a shape, and digital signal processing techniques such as maximum likelihood decoding techniques that detect data.

An equalizer will be described as an example of a conventional digital signal processing device with reference to FIGS.

The equalizer is composed of a shift register group SR, a multiplier group MUL and an adder SUM as shown in FIG. The digital data Xin that is an input signal is input to the shift register group SR, and the data latched at the front stage is sequentially shifted to the rear stage. Shift register group SR
Of each latch data is output to the multiplier group MUL, and each of the multipliers MUL1 to 7 outputs the multiplication result of each latch data and each coefficient value K1 to K7. Then, the respective multiplication results are added by the adder SUM and become the output Yout of the equalizer. That is, an equalizer is a system that performs a convolution operation of a signal input to the shift register group SR and each coefficient value at an input time interval (data interval) of an input signal.

[0005]

At this time, if the operating speed of each multiplier or adder is sufficiently high with respect to the clock, the equalizer output can be immediately obtained for the input signal sequence. Is. But as the clock gets faster,
The operating speed of the multiplier and the adder cannot be kept sufficiently high. In this case, generally, a method (pipelining) is used in which a latch is provided inside the multiplier or the adder at a time interval at which calculation is possible. Although high-speed operation is guaranteed by this, the scale of the equalizer is increased by the number of latches provided inside the multiplier and the adder, and the increase in scale further increases power consumption.

Here, a rough estimation of the circuit scale and power consumption when a digital equalizer is composed of CMOS elements in a general WalleTree configuration having a 1-bit full adder as a constituent element will be estimated.

As shown in FIG. 11, the number of inputs of the 1-bit full adder is 3 bits (input 2, Carry 1), and the number of outputs is 2 bits (output 1, Carry 1). Therefore, as shown in FIG. 12, the number of bits N to be added in the first-stage full adder (generally, the number of input bits × the number of coefficient bits × the number of taps)
Is about 2 (N / 3) in the 1-bit full adder, which is about N / 3 of the number of bits to be added. Similarly for the subsequent steps, the number of full adders is about 1/3 of the number of bits received from the previous stage, and about 2/3 of the number of bits received from the previous stage.
The bit number of is output to the subsequent stage. In this way, the number of bits output to the subsequent stage and the number of adders change in geometric progression.

According to this estimation, the number of full adders is almost equal to the number of bits N to be added in the first full adder. What should be noted here is the number of bits to be output to the subsequent stage. If the operating speed of the full adder is not sufficiently high with respect to the clock, a latch is provided for every several stages of the full adder,
It becomes necessary to hold the total number of bits output to the subsequent stage with a clock. For example, if the sum of the operating speeds of the two full adders and the latch exceeds the clock, a latch is required for each full adder, and the sum of the operating speeds of the three full adders and the latch is the clock. If it exceeds, it is necessary for every two full adders. At this time, the approximate number of latches is about 0.25 times the number of full adders when a latch is provided for every four full adders, and the full adder when a latch is provided for every three full adders. About the number of
0.6 times, about 1.2 times for every two full adders, full adder 1
It becomes about 3 times for each step. Since the circuit scale of one latch is about 1 / 1.2 times that of one full adder, the latch is provided for every three stages of full adders in comparison with the circuit scale when no latch is provided at all. In this case, the circuit scale is approximately 1.5 times, in the case of every two full adders being approximately twice, and in the case of every one full adder being approximately 3.5 times. In addition, the power consumption of one latch is about twice as much as that of one full adder. (While the full adder operates only with the clock, the latch operates internally with twice the clock. The power consumption when there are no latches is about 2.2 times that when latches are provided for every three full adders, and about 3.4 when there are two full adders.
In the case of each double adder and each full adder, the power consumption reaches about seven times.

That is, it is assumed that the equalizer operating at a clock of 50 Mbps has a pipeline structure in which a latch is provided for every two stages of full adders and can be designed with a circuit scale of 4 Kgates and 200 mW. If an equalizer with the same function that operates at a clock of 100 Mbps is designed with the components used in this design, a latch is required for each full adder stage,
The circuit scale is about 1.8 times (3.5 / 2) 7Kgates, and the power consumption is about 4.1 times (7/3.) Considering the increase of the clock.
It becomes 820 mW of 4 × 2). In particular, the increase in power consumption is remarkable. Furthermore, speeding up beyond 100 Mbps is practically impossible because one full adder stage cannot be allocated between the latches.

Further, since the increase in power consumption due to the pipelining to cope with such speedup is similarly applied to the digital signal processing circuits other than the equalizer, it corresponds to the speedup of the apparatus. It has been extremely difficult to realize a highly integrated LSI.

In recent years, the tendency toward high-speed transfer of magnetic and optical recording / reproducing devices has been remarkable. Along with this, a digital signal processing method suitable for mass production and having higher speed and higher accuracy (such as an increase in the number of equalizer taps) is being adopted. However, in order to meet the demand for high-speed transfer, the speedup of the LSI process is not sufficient, and therefore an increase in power consumption cannot be avoided for the reasons described above. Further, in order to reduce the device cost, it is necessary to adopt a process that is as slow and inexpensive as possible to reduce the circuit cost. Therefore, it can be said that it is extremely difficult to realize a high-speed high-speed digital signal processing device capable of high-speed transfer using the conventional technique (pipelined structure).

An object of the present invention is to provide a signal processing technique capable of realizing an improved operation speed at lower cost with lower power consumption.

Another object of the present invention is to provide a signal processing technique capable of high-speed operation exceeding the operation speed of circuit components.

Still another object of the present invention is to provide a signal processing technique suitable for signal processing of digital data in which signal quality does not deteriorate due to multistage shift and latch operations.

Still another object of the present invention is to realize high-speed and high-reliability decoding processing in a system in which interference between data is large by executing waveform equalization processing and maximum likelihood decoding processing at high speed. It is to provide a possible signal processing technology.

Still another object of the present invention is to provide a signal processing technique suitable for integration into an integrated circuit.

[0017]

The present invention provides, as an example, the signal processing apparatus shown in FIG.

That is, first, N clocks (C1 to Cn) whose phases are sequentially shifted by the data interval Td at a repetition frequency of 1 / N (N is an integer of 2 or more) from the clock C of the data interval Td. ) For generating a clock
And N number of M (M is a positive integer) stage shift register means (SR1 to SRn) which receives the input signal Xin as input and N clocks (C1 to Cn) of the clock generating means as shift clock inputs, respectively. And for the M outputs of the M-stage shift register means, the N clocks (C
1 to Cn), a (N-1) group of N M-stage latch means (L1 (1) to Ln) is latched by a clock sequentially delayed by a data interval with respect to the shift clock used for the shift of the M-stage shift register means. (N-1)) and the output signals of the N M-stage shift register means and the (N-1) sets of N M-stage latch means are input by the shift or latch output signals by the same clock operation. A signal processing device is configured with N first signal processing means (SP1 to SPn).

Second, the M-stage shift register means and the M-stage shift register means
The stage latch means may be composed of a 1-bit or multi-bit digital circuit.

Thirdly, the N outputs of the N first signal processing means may be provided with the second signal processing means similar to the first signal processing means.

Fourth, the first and second signal processing means may be equalizers.

Fifth, the first and second signal processing means may be a discriminator such as a maximum likelihood decoder that handles time series signals.

Sixth, the first and second signal processing means may have a subordinate or composite structure of an equalizer and a discriminator.

Seventh, any one of the first and second signal processing means may be an integrated circuit.

Eighth, the clock generating means, the M-stage shift register means, and the M-stage latch means may be the same integrated circuit.

Ninth, the operation may be performed at a speed exceeding the operating speed of the subordinate structure of the M-stage latching means and the bit adding means.

Tenth, a magnetic recording / reproducing apparatus including the signal processing apparatus according to any one of the first to ninth means may be used.

Eleventh, an optical regenerator including the signal processing device according to any one of the first to ninth means may be used.

Twelfthly, a magneto-optical recording / reproducing apparatus including the signal processing apparatus according to any one of the first to ninth means may be provided.

Thirteenth, an array system of a magnetic recording / reproducing apparatus including the tenth means may be used.

Fourteenth, an array system of an optical reproducing apparatus including the eleventh means may be used.

Fifteenthly, an array system of a magneto-optical recording / reproducing apparatus including the twelfth means may be provided.

[0033]

In the above-described first invention, the input of the N first signal processing means is N times the data interval. For this reason,
The N first signal processing means only have to operate at a time interval N times the data interval Td, and the number of stages of the internal pipeline can be significantly reduced. That is, if the present invention is applied to a conventional high-speed signal processing device having a pipeline configuration for each full adder, it is estimated that the circuit scale and power consumption will be as shown in FIG.

On the other hand, if N signal processing circuits having the same circuit configuration are used, a circuit that operates at N times the data interval can be achieved with N times the circuit scale and power consumption. That is, N = 2 may be set in order to enable double speed operation, and the circuit scale and power consumption at this time are both double. In the enhancement of the pipelining described in the prior art, the double-speed operation can be realized by making the pipeline configuration in which the latch is provided for every two stages of full adders every one stage of full adders. In addition, the circuit scale at this time is about 1.8 times, and the power consumption is about 4.1 times. According to the present invention, although the circuit scale is slightly increased, the power consumption is reduced to about 1/2, and it can be said that extremely low power consumption can be realized with extremely high efficiency. Moreover, while the conventional pipeline cannot be expected to achieve higher speed, the present invention can be expected to achieve higher speed within a range in which the shift register and the latch circuit can operate.

Therefore, according to the present invention, the operating speed of the device by the process is sufficient, as in the case of manufacturing a circuit device by the MOS process or the C-MOS process, which is inferior in speed to the bipolar process or the like. Even if it is not, a high-speed signal processing device can be achieved with low power consumption.

Second, the M-stage shift register means and the M-stage shift register means
By configuring the stage latch means with a 1-bit or multi-bit digital circuit, it is possible to realize signal processing without deterioration of signal quality. That is, the parallelization of the signal processing means according to the present invention consists of multi-stage shift and latch operations by the M-stage shift register means and the M-stage latch means. Therefore, a configuration using a digital circuit in which the signal quality does not deteriorate due to multi-stage shift and latch operations is suitable.

Thirdly, by providing a second signal processing means similar to the first signal processing means to the N outputs of the N first signal processing means, for example, parallelization processing is performed. By outputting the N outputs of the N first signal processing means obtained in step 1 as time-series signals, it is possible to obtain signal-processed outputs with a small circuit delay, and feedback processing using these outputs as inputs The system including can be controlled stably.

Fourthly, by using the first and second signal processing means as an equalizer, a linear equalizer including a multiplier, a decision feedback equalizer, etc., which is particularly difficult to speed up, etc. By using the equalizer, a high speed and low power consumption equalizer can be configured. At this time, the number of taps of the transversal equalizer is N
× M taps, and the number of parallelization stages N (the number of shift register sets) required for speeding up and the number of taps L required for equalization are M to the number of stages M of shift registers and latches (M = L / N: M is a positive Integer).

Fifth, the first and second signal processing means are discriminators such as maximum likelihood decoders that handle time-series signals, so that a signal sequence method and a maximum likelihood decoder capable of parallel processing can be obtained. By combining them, a high-speed and high-performance decoder can be constructed.

Sixth, the first and second signal processing means have a subordinate or composite structure of an equalizer and a discriminator, and are capable of high-speed and high-performance signal processing adaptable to a system having a large interference between data. The device is configurable.

Seventhly, by using any one of the first and second signal processing means as an integrated circuit, the blocks to be parallelized have the same circuit configuration, so that the configuration of the repetitive circuit is easy. The circuitization makes it possible to improve the efficiency of the manufacturing process.

Eighth, means for generating the clock and M
By making the stage shift register means and the M stage latch means the same integrated circuit, it becomes possible to control the phase between clocks sufficiently accurately with respect to the data interval.

Ninth, by operating at a speed exceeding the operating speed of the subordinate structure of the M-stage latching means and the bit adding means, the operating speed which cannot be realized only by the conventional pipeline processing is exceeded. It is possible to provide a signal processing device capable of high-speed operation.

Tenth, a high-speed and high-performance magnetic recording / reproducing apparatus can be constructed by using the magnetic recording / reproducing apparatus including the signal processing device according to any one of the first to ninth means.

Eleventh, by providing an optical reproducing device including the signal processing device according to any one of the first to ninth means,
A high-speed and high-performance optical regenerator can be constructed.

Twelfth, by using the magneto-optical recording / reproducing apparatus including the signal processing device according to any one of the first to ninth means, a high-speed and high-performance magneto-optical recording / reproducing apparatus can be constructed.

Thirteenth, by using the array system of the magnetic recording / reproducing apparatus including the tenth means, an array system of the magnetic recording / reproducing apparatus of high speed and high performance can be constructed.

Fourteenth, by using the array system of the optical reproducing apparatus including the eleventh means, an array system of the optical reproducing apparatus of high speed and high performance can be constructed.

Fifteenth, the array system of the magneto-optical recording / reproducing apparatus including the above-mentioned twelfth means can constitute an array system of the high-speed and high-performance magneto-optical recording / reproducing apparatus.

[0050]

Embodiments of the present invention will now be described in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a conceptual diagram showing an example of the configuration of a signal processing apparatus according to a first embodiment of the present invention.

The signal processing apparatus according to the present embodiment includes a clock generating means CLK, N M-stage shift register means SR1 to SRn to which an input signal Xin is input in parallel, and (N-
1) A set of N M stage latch means L1 (1) to Ln (n-
1) and N signal processing means SP1 to SPn for outputting output signals Yout1 to Yountn, respectively.

M-stage shift register means SRn and M-stage latch means Ln (1) to Ln (n-1) connected thereto.
And the signal processing means SPn connected to them form N blocks n, and output signals Yo from each block n
utn is output.

As shown in FIG. 3, the clock generating means CLK has a repetition frequency of 1 / N (N is an integer of 2 or more) from the clock C of the data interval Td, and the phase thereof is sequentially shifted by the data interval Td. The individual clocks C1 to Cn are generated. N M (M is a positive integer) stage shift register means S
The input signals Xin are input to R1 to SRn, and the N clocks C1 to Cn of the clock generating means CLK are input as clocks.

Explaining focusing on the block 1, the M outputs of the M stage shift register means SR1 are connected to the inputs of the M stage latch means L1 (1), respectively, and are used for the shift of the M stage shift register means SR1. The shift clock C1 is latched by the clock C2 delayed by the data interval Td. The input of the M-stage latch means L1 (2) in the next stage is the output of L1 (1) in the previous stage, and is latched by the clock C3.
Hereinafter, L1 (3) to L1 (n-1) have the same configuration.
At this time, the M-stage shift register means SR1 and the M-stage latch means L1 (1) to Ln (n-1) need to operate at the data interval Td, but the N signal processing means SP1 to SP.
It can be seen that Pn has a sufficient operating speed of N × Td. Considering that the shift register is basically composed of latches, the signal processing device according to the present embodiment can be speeded up to an operating speed at which the latch means can operate.

Block 2 has exactly the same circuit configuration, but differs only in clock input. The clock of the M-stage shift register means SR2 is C2, and the clock of the M-stage latch means L2 (1) receiving its output is C3, i
The clock of the Mth stage latch means L2 (i) is C (i +
2). However, the clock of the last stage L2 (n-1) is C1.

Here, as shown in FIG. 4, N = 2 and M = 3.
FIG. 5 shows how the outputs of the shift registers and the latches change in time series in the case of. The data alternately fetched into the shift registers SR1 and SR2 is
It is output as shown at times T6 to T8. Time T6
~ T7 for shift register SR2 and latch L1
The output of (1) is constant, and the outputs of the shift register SR1 and the latch L2 (1) are constant from time T7 to T8. Therefore, if these two sets of data outputs are input to the two signal processing means SP1 and SP2 and SP1 and SP2 are operated by the clocks C2 and C1, respectively, the operation of the two signal processing means SP1 and SP2 It can be seen that the speed is 2Td. In this case, if the signal processing means is an equalizer, a 6-tap equalizer can be constructed. Note that N ≧ 2,
It is obvious that M ≧ 1 can be applied, and when configuring an equalizer, it can be easily inferred that it is appropriate to select N from the operating speed and power consumption and M from the accuracy.

At this time, by adding a processing circuit 10 as shown in FIG. 6 to the output stage of the equalizer, signal processing corresponding to partial response waveform processing (1 + D) can be realized. The processing circuit 10 includes a latch 11 that holds the output signal Yout1 of the signal processing apparatus illustrated in FIG. 4 at the timing of the clock C2, a latch 12 that holds the output signal Yout2 at the timing of the clock C1, and the current input signal Yout1. , An adder 13 that calculates the sum of the input signal Yout1 held at the previous clock held in the latch 11 and outputs it as Yout1 ′, the current input signal Yout2, and the latch 12 And an adder 14 that calculates the sum of the input signal Yout2 held at the immediately preceding clock and outputs it as Yout2 '.

That is, in the partial response, the waveform processing (1 + D) means the sum of the input signal at the current time and the input signal one sample before, while the input signal Yout.
When 1~Yout2 is for example that of the magnetic recording system, since it has originally (1-D) corresponding characteristics in the magnetic recording system, Yout1'～Yout2 'is, 1-D ² =
Since it has a characteristic equivalent to (1-D) (1 + D), the class 4 (PR4) processing of partial response can be realized.

Further, since the inputs of the N signal processing means change at a time N times the data interval, the N signal processing means may operate at a time interval N times the data interval Td. The number of stages in the internal pipeline can be significantly reduced.

On the other hand, by using N signal processing circuits having the same circuit configuration, a circuit which operates at N times the data interval can be achieved with N times the circuit scale and power consumption. That is, N = 2 may be set in order to enable double speed operation, and the circuit scale and power consumption at this time are both double. In the case of speeding up by strengthening the pipelining of the equalizer described in the prior art, twice the high-speed operation is possible by making the pipeline configuration in which a latch is provided for every two stages of full adders every one stage of full adders. However, the circuit scale at this time is about 1.8 times, and the power consumption is about 4.1 times. Therefore, according to the present invention, a high-speed signal processing device can be achieved with low power consumption, even if the operating speed of the device by the process is not sufficient.

Although the first embodiment according to the present invention can be basically constituted by an analog circuit mainly composed of a sample hold circuit, the M stage shift register means and the M stage latch means are digital of 1 bit or plural bits. It may be configured by a circuit. The parallelization of the signal processing means according to the present invention is M
It consists of multi-stage shift and latch operations by the stage shift register means and the M stage latch means. Therefore, it is possible to expect a signal processing circuit that does not deteriorate in signal quality due to multi-stage shift and latch operations by digitization.

(Embodiment 2) FIG. 7 is a conceptual diagram showing an example of the configuration of a signal processing apparatus according to a second embodiment of the present invention.

The signal processing apparatus of this embodiment comprises a variable gain amplifier 107 for controlling the amplitude of an analog input signal, an A / D converter 100 for digitizing an analog signal, and the first
Of the first signal processing means 108 and the second signal processing means 110 having the configuration illustrated in the embodiment of the present invention, and the gain control circuit 111- for performing the control operation of each of the variable gain amplifier 107 and the A / D converter 100. 1, a sample phase control circuit 111-2. The first signal processing means 108 of this embodiment is, for example, an equalizer with several taps.

The signals equalized by the first signal processing means 108 are corrected by the gain control circuit 111-1 and the sample phase control circuit 111-2 of the variable gain amplifier 107 and the A / D converter 100, respectively. The gain amount and the sample phase amount are calculated, and the gain and the sample phase are adjusted.

According to this embodiment, the first signal processing means 1
The equalizer composed of 08 has a few taps and has a small circuit delay. Therefore, more stable gain and phase feedback control is possible.

At this time, the second signal processing means 110 may also be an equalizer. In the second signal processing means 110,
The first signal processing unit 108 equalizes a portion that cannot be equalized. The second signal processing unit 110 particularly equalizes a region with a large circuit delay that cannot be equalized by the first signal processing unit 108. High-precision equalization suitable for high-performance identification is possible.

The second signal processing means 110 may be a discriminator such as a maximum likelihood decoder that handles time series signals. A high-speed and high-performance decoder can be constructed by combining a parallel processing coding method and a maximum likelihood decoder.

Further, the second signal processing means 110 may have a subordinate or composite structure of an equalizer and a discriminator. By providing the second signal processing means 110 with a subordinate circuit of an equalizer and a discriminator or a composite configuration circuit, a high-speed and high-performance equalization discriminator adaptable to a system having a large interference between data can be constructed.

Further, any one of the first signal processing means 108 and the second signal processing means 110 may be an integrated circuit. INDUSTRIAL APPLICABILITY The present invention has the same circuit configuration in blocks to be parallelized, and therefore is suitable for an integrated circuit in which the configuration of a repetitive circuit is easy by a photolithography technique or the like.

Further, the clock generating means, the M-stage shift register means and the M-stage latch means may be the same integrated circuit. In the present invention, it is necessary to control the phase between the clocks sufficiently accurately with respect to the data interval, and the above configuration is suitable for the configuration provided in the same integrated circuit in close proximity.

(Embodiment 3) FIG. 8 is a conceptual diagram showing a third embodiment of the present invention. In the present embodiment, the signal processing device according to the embodiment of the present invention is applied to a magnetic disk device.

The magnetic disk device M includes a magnetic disk 115 as a recording medium, a rotation control mechanism 117 for rotating the magnetic disk 115, a magnetic head 116 for recording / reproducing data to / from the magnetic disk 115, and a magnetic head 116. Seek control mechanism 118 for performing a positioning operation in the radial direction of the magnetic disk 115, a control system circuit, a recording system circuit and a reproducing system circuit, and a driver and a reproducing unit for a recording current, which are commonly provided for the recording system and the reproducing system. Recording / reproducing amplifier 105 including a preamplifier and a modulating / demodulating circuit 10 for performing a modulating process for generating recorded data and a demodulating process for converting reproduced magnetization information into user data.
Equipped with 3.

The control system circuit includes the controller 102, which controls various controls, the mechanical system driver 120, the mechanical system driver 120, and the rotation control mechanism 117.
6, the servo control circuit 106 for controlling the seek operation and the rotation of the magnetic disk 115, the data buffer 114 for storing the data exchanged with the host device, and the like.

The recording system circuit includes a recording correction circuit 104 for controlling the reversal position of the recording current from the recording data string, and a recording variable clock generator 11 for generating the recording clock WCLK.
It is composed of 9 etc.

The reproducing circuit system includes a variable gain amplifier 107, A
A / D converter 100, a signal processing device 101, a gain control circuit 111 that controls the variable gain amplifier 107, and a reproduction clock that gives a read clock RCLK to the A / D converter 100 and the signal processing device 101 under the control of the gain control circuit 111. It is composed of a variable clock generator 112, a coefficient calculation circuit 109, and a counting memory set circuit 113. Further, the signal processing device 101 uses the count value set in the count memory set circuit 113 to perform the waveform equalization process on the equalizer 10.
8, identification circuit 110, equalizer 108 and identification circuit 11
Clock generation means CLK for giving 0 to the operating clock
Etc.

Here, the reproducing system related to the signal processing device 101 will be described in more detail.

The operation during reproduction will be briefly described with reference to FIG. The magnetization information recorded on the magnetic disk 115 is detected as an electric signal by the magnetic head 116, the signal is amplified by the reproduction preamplifier of the recording / reproduction amplifier 105, and the output amplitude of the equalizer 108 has an output amplitude suitable for identification. The amplitude is adjusted by the variable gain amplifier 107 so as to be obtained, digitized through the A / D converter 100, and then input to the signal processing device 101. Here, in the signal processing device 101, the equalizer 108 (first unit) configured to cause the signal processing means SP1 to SPn in the configuration illustrated in FIG. 1 to perform the waveform equalization processing illustrated in FIGS. Signal processing means), and the signal processing means SP1 to SPn in the configuration illustrated in FIG. 1, for example, an identification circuit 110 (second signal processing means) adapted to perform maximum likelihood decoding processing. Equalizer 1
The coefficient of 08 is set corresponding to the seek operation of the magnetic head 116, and the coefficient calculation circuit 109 having a coefficient correction algorithm such as LMS (least squares method) is operated for each seek operation to always perform optimum equalization. To be able to do it. further,
The output of the equalizer 108 is sent to the identification circuit 110, converted into user data by the modulation / demodulation circuit 103, and error correction is performed by the controller 102.

At this time, the coefficient calculating circuit 109 is operated only at the time of shipment or power-on at track positions appropriately divided between the inner and outer circumferences of the magnetic disk 115 to calculate the coefficient, and this coefficient is set in the coefficient memory setting circuit 113. By storing the value in the coefficient memory set circuit 113, the value of the coefficient memory set circuit 113 can be set in the equalizer 108 based on the seek destination information (track position) from the controller 102 during the reproducing operation. In this case, the training area on the magnetic disk 115 used for calculating the coefficient can be erased when the coefficient is calculated, and this area can be used as the user data area. Moreover,
The coefficient calculation circuit 109 needs to operate only at the time of shipment or power-on, and does not operate in the normal reproduction state, so that the power consumption of this portion can be reduced. In addition, the A / D converter 100
It goes without saying that an LPF (low-pass filter) is provided in the preceding stage. Further, a boost circuit for enhancing high frequency components within the band of the signal may be included in order to improve the number of effective bits of the A / D converter 100.

According to the present embodiment, the signal processing device 101 has a high speed and low power consumption, so that high speed and low power consumption can be achieved.
A small magnetic disk device M can be easily realized.

In this embodiment, the signal processing device 101 according to the present invention is applied to the reproducing system of the magnetic disk device M. However, a magnetic recording / reproducing device including a floppy disk device and a magnetic tape device, an optical reproducing device. It is obvious that the same can be applied to a reproducing system such as a magneto-optical recording / reproducing device.

(Embodiment 4) FIG. 9 is a conceptual diagram showing a fourth embodiment of the present invention.

The present embodiment is an array system using the magnetic disk device M illustrated in the above-mentioned third embodiment as a drive. Multiple drives M1 to Mn
Is connected to an input / output channel of a host device (not shown) via the controller 102 '.

By using the high-speed, low-power-consumption magnetic disk device M according to the present invention as the drives M1 to Mn, an ultra-high-speed array system of high-performance magnetic disk devices can be realized with low power consumption.

In this embodiment, the array system constituted by the magnetic disk device provided with the signal processing device according to the present invention is shown, but other magnetic recording / reproducing device, optical reproducing device, magneto-optical recording / reproducing device according to the present invention are shown. It is obvious that the array system by etc. can be realized similarly.

[0086]

According to the signal processing device of the present invention, it is possible to obtain the effect that the operating speed can be improved at lower power consumption and lower cost.

Further, according to the signal processing device of the present invention, it is possible to obtain the effect that high-speed operation exceeding the operation speed of the constituent elements of the circuit can be realized.

Further, according to the signal processing device of the present invention, it is possible to obtain the effect that the signal processing of digital data which does not deteriorate the signal quality due to the multi-stage shift and latch operations and the like can be executed with lower power consumption and at higher speed. .

Further, according to the signal processing apparatus of the present invention, the waveform equalization processing and the maximum likelihood decoding processing are executed at high speed, thereby realizing high-speed and highly reliable decoding processing in a system where there is a large amount of interference between data. The effect of being able to do is obtained.

Further, according to the signal processing device of the present invention, since it is easy to form an integrated circuit, downsizing, high integration,
Further, the effect that the manufacturing cost can be reduced can be obtained.

The recording / reproducing apparatus to which the signal processing apparatus of the present invention is applied can achieve high density recording of information on a recording medium, high reliability, and high speed data transfer.
The effect is obtained.

Further, the array system composed of the recording / reproducing apparatus using the signal processing apparatus of the present invention has an effect of being capable of supporting ultra-high speed data transfer.

[Brief description of drawings]

FIG. 1 is a conceptual diagram showing an example of a configuration of a signal processing device that is an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an example of the operation.

FIG. 3 is a diagram showing an example of the operation.

FIG. 4 is a conceptual diagram showing a specific configuration of a part thereof.

FIG. 5 is a diagram showing an example of the operation.

FIG. 6 is a conceptual diagram showing a modified example thereof.

FIG. 7 is a conceptual diagram showing an example of a configuration of a signal processing device which is another embodiment of the present invention.

FIG. 8 is a conceptual diagram showing still another embodiment of the present invention.

FIG. 9 is a conceptual diagram showing still another embodiment of the present invention.

FIG. 10 is a conceptual diagram showing an example of a basic configuration of a conventional equalizer.

FIG. 11 is a conceptual diagram showing an example of an input / output relationship of a conventional full adder.

FIG. 12 is a conceptual diagram showing an example of the operation of a conventional equalizer.

[Explanation of symbols]

CLK ... Clock generating means, SR1 to SRn ... M stage shift register means, shift register, C1 to Cn ... Clock, L1 (1) to Ln (n-1) ... M stage latch means, latches, SP1 to SPn, 108 ... First signal processing means (signal processing device), equalizer, 110 ... Second signal processing means, equalizer, maximum likelihood decoder, 10 ... Processing circuit, 11, 12
... latches, 13, 14 ... adders, M ... magnetic disk devices, M1 to Mn ... drives, 100 ... A / D converters, 1
01 ... Signal processing device, 103 ... Modulation / demodulation circuit, 115
... magnetic disk, 116 ... magnetic head, 109 ... coefficient calculation circuit, 113 ... coefficient memory set circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Terumi Takashi Inventor Terumi Takashi 2880 Kozu, Odawara, Kanagawa Stock Company Hitachi Storage Systems Division (72) Yoshito Watanabe 2880 Kozu, Odawara, Kanagawa Hitachi Storage Co., Ltd. System Division

Claims (5)

[Claims] 1. A signal processing device for processing a time series discrete signal having a data interval Td, wherein 1 / N (N is an integer of 2 or more) from a clock C having the data interval Td as one cycle.
At a repetition frequency of N, the clock generating means CLK for generating N clocks (C1 to Cn) sequentially shifted in phase by the data interval Td, and the input signal Xin as input.
N M (M is a positive integer) stage shift register means (SR1 to SRn) which receives the respective clocks (C1 to Cn) as shift clock inputs, and M of the M stage shift register means (SR1 to SRn). Of the N outputs (C1 to Cn) from the M stages of shift register means (S).
(N1) sets of N M-stage latch means (L1) that are latched by a clock sequentially delayed by a data interval Td with respect to the shift clock used for shifting R1 to SRn).
(1) to Ln (n-1)), the N M-stage shift register means (SR1 to SRn), and (N-1) sets of N M.
Among the output signals of the stage latch means (L1 (1) to Ln (n-1)), the M stage shift register means (SR1 to SRn) and the (N-1) group N are operated by the same clock.
A signal characterized by comprising N first signal processing means (SP1 to SPn) which respectively receive the output signals of the M stage latching means (L1 (1) to Ln (n-1)). Processing equipment. 2. The signal processing device according to claim 1, wherein the M-stage shift register means and the M-stage latch means are configured by a 1-bit or a multi-bit digital circuit. 3. The N first signal processing means comprises at least one of an equalizer and a discriminator such as a maximum likelihood decoder that handles a time series signal. The signal processing device described. 4. A second signal processing means is provided on each of the N output sides of the N first signal processing means, and the first and second signal processing means are both equalizers. 1 configuration, a second configuration in which the first signal processing means is an equalizer, and the second signal processing means is a discriminator such as a maximum likelihood decoder that handles a time-series signal, the first and the second 4. The signal processing device according to claim 1, wherein the second signal processing means comprises at least one of a third configuration including a subordinate or composite configuration of an equalizer and a discriminator. . 5. The clock generating means, the M-stage shift register means, the M-stage latch means, and at least one of the first and second signal processing means are formed in the same integrated circuit. Claims 1, 2, 3
Alternatively, the signal processing device according to item 4.