JPH07273684A - PLL frequency synthesizer - Google Patents

Abstract

(57) [Summary] [Object] The present invention provides a PLL frequency synthesizer capable of reducing the operation load of the CPU and realizing stable circuit operation. [Structure] When a call signal is received by a control command SW of the CPU 3, the operation of the adder circuit 33 is blocked, so that the comparison frequency divider 6 is constituted only by the comparison frequency division number according to the communication channel set in the latch 5. Is set to the latch 32 for comparison and the difference according to the communication channel set in the latch 5 by allowing the operation of the adder circuit 33 when transmitting the call signal. The frequency division number N of the comparison frequency divider 6 is set by adding the differential frequency division numbers according to the frequency difference at the time of reception / transmission.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL frequency synthesizer for outputting a signal having a predetermined frequency, and more particularly to a device for continuously switching a predetermined frequency.

[0002]

2. Description of the Related Art Recently, a digital wireless terminal device adopting a TDD communication system has been widely used as a portable terminal device capable of calling a caller from outside to talk.

By the way, in such a digital radio terminal device, in order to frequency-convert a high-frequency signal into a low-frequency signal or a low-frequency signal into a high-frequency signal, a local oscillator that performs different local oscillations at the time of transmission and reception is used. , PLL frequency synthesizers are used.

FIG. 5 shows a schematic configuration of a conventional PLL frequency synthesizer. In this case, the reference signal generator 1 is used.
Is applied to the reference frequency divider 2 to output a reference signal fr (= ftcxo / R) divided by R.

On the other hand, the frequency division number data signal Data (frequency division number N) corresponding to a predetermined frequency from the CPU 3 is supplied to the clock C.
According to LK, it is taken into the shift register 4, and the data signal of this shift register 4 is transferred to the latch 5 by the load enable signal LE as the comparison frequency division number, thereby setting the frequency division number N of the comparison frequency divider 6. The output signal fvco of the voltage controlled oscillator (VCO) 7 is frequency-divided by this frequency division number N to output a comparison signal fr '.

Then, the reference signal fr and the comparison signal f
r ′ is phase-compared by the phase comparator 8, the error signal is integrated by the loop filter (LPF) 9, and converted into an error voltage,
By applying this to the control terminal of the voltage controlled oscillator (VCO) 7, it is possible to operate so that fr = fr 'and obtain a signal that keeps the set predetermined frequency constant.

[0007]

However, according to the PLL frequency synthesizer configured as described above, when the modulation method of the digital wireless terminal device is a direct modulation method or when different IF frequencies are used for transmission and reception, respectively. In addition, as a local oscillator, I
The oscillation frequency differs by the F frequency or the IF frequency difference.

For this reason, the CPU 3 prepares two kinds of setting data signals Data for one communication channel, and changes and outputs the data signals Data each time the transmission / reception state changes. Since the comparison frequency division number has to be set, there is a problem that the operation load of the CPU 3 increases and the circuit operation becomes unstable.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a PLL frequency synthesizer capable of reducing the operation load on the CPU and realizing stable circuit operation.

[0010]

According to the present invention, a voltage controlled oscillator for outputting a predetermined frequency based on a predetermined voltage,
A frequency divider that divides the predetermined frequency signal output by the voltage controlled oscillator by a predetermined division number, a reference signal oscillator that outputs a reference frequency signal, a reference frequency signal output from the reference signal oscillator, and the division It has a phase comparator that compares the phase with the frequency-divided signal divided by the frequency divider and outputs a phase difference signal, and the voltage based on the voltage based on the phase difference signal output from the phase comparator In a PLL frequency synthesizer for inputting to an oscillator, a first frequency division number setting means for setting a frequency division number corresponding to the predetermined frequency signal, and a differential frequency signal between a frequency signal different from the predetermined frequency signal. Second frequency division number setting means for setting the frequency division number, and in one state, the frequency division number set in the first frequency division number setting means is output to the frequency divider, and in other states, The first frequency division number setting hand It is constituted by a means for outputting to said frequency divider adding or subtracting to the frequency division number set to set the frequency division number and the second dividing number setting means.

Further, according to the present invention, the second frequency division number setting means includes a shift register for taking in frequency division number data corresponding to a difference frequency signal between the predetermined frequency signal and a different frequency signal. And a latch for latching the frequency division number data of the shift register.

Further, according to the present invention, the second frequency division number setting means generates the frequency division number data corresponding to a frequency difference signal between the predetermined frequency signal and a different frequency signal. It is configured to consist of.

[0013]

As a result, according to the present invention, the differential frequency signal between the first frequency division number setting means for setting the frequency division number corresponding to the predetermined frequency signal and the frequency signal different from the predetermined frequency signal is dealt with. The second frequency division number setting means for setting the frequency division number is set, and outputs the frequency division number set in the first frequency division number setting means in a certain state, and outputs the frequency division number in the other state. The frequency division number set in the first frequency division number setting means and the frequency division number set in the second frequency division number setting means are added or subtracted and output. As a result, the comparison frequency can be set for each of transmission and reception by one type of setting data according to the communication channel, and even if the transmitting and receiving states are repeated, the setting data can be dealt with without changing.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a schematic configuration of a digital wireless terminal device to which the present invention is applied. In the figure, reference numeral 11 denotes an antenna, and a high frequency section 12 is connected to the antenna 11. The high frequency unit 12 performs frequency conversion processing, and has an antenna switch unit 121, a receiving unit 122, a transmitting unit 123, and a PLL frequency synthesizer 124, which will be described in detail later.

The high frequency section 12 has a modem 13
TDMA14, speech codec 15 and PCM
16, a speaker 18 on the receiving side and a microphone 19 on the transmitting side are connected to the PCM 16 via an amplifier 17.

Here, the modem 13 uses a π / 4 shift QP
It performs SK modulation and demodulation processing, and at the receiving side, the receiving unit 1
The IF signal from 22 is demodulated and separated into IQ data,
The data is transferred to the TDMA 14 as a data string, and on the transmission side, IQ data is created from the data transferred from the TDMA 14, and π / 4 shift QPSK modulation is performed, and the IQ data is sent to the transmission unit 123.

The TDMA 14 performs frame synchronization and slot format processing. On the receiving side, the scramble of the data of the predetermined slot sent from the modem 13 is descrambled, and the configuration data is extracted from the format of this slot. , Sends control data to the control unit 20 described later, transfers voice data to the speech codec 15, and at the transmitting side, adds control data to the voice data transferred from the speech codec 15 to create slot data. Then, the data is scrambled, the slot data is inserted into the frame at a predetermined timing (allocated time slot for transmission), and the modem 13
I am trying to transfer to.

The speech codec 15 performs compression / expansion processing of digital data.
ADPCM audio signal (4bi) sent from MA14
t × 8 KHz = 32 Kbps for PCM audio signal (8 b
(it × 8 KHz = 64 Kbps), it is expanded by decoding and output to PCM16.
The PCM voice signal sent from the D.6 is compressed by being encoded into the ADPCM voice signal and sent to the TDMA 14.

The PCM 16 performs analog / digital processing. On the receiving side, the PCM audio signal sent from the speech codec 15 is converted into an analog signal by D / A conversion, and then output to the amplifier 17 to be a speaker. 18 and a microphone 19 on the transmitting side.
A / D conversion of the analog audio signal input from the PC
The M audio signal is output to the speech codec 15. The PCM 16 also controls a volume, a ringer, a tone signal and the like.

The high frequency section 12 and the modem 1
3, TDMA14, speech codec 15 and P
A control unit 20 is connected to the CM 16 and the control unit 20
ROM 21, RAM 22, recording / reproducing circuit 23, memory 2
4, the display unit 25 and the key input unit 26 are connected.

Here, the ROM 21 stores the control program in the control unit 20. The RAM 22 temporarily stores the data handled by the control of the control unit 20. Further, the recording / reproducing circuit 23 records and reproduces a message message from the other party when it is used as an answering machine. The memory 24 stores a standard message when used as an answering machine. The display unit 25 displays input data and results for various controls. The key input unit 26 is adapted to give a key input for setting various functions to the control unit 20.

FIG. 2 shows a schematic structure of the high frequency section 12. In this case, the antenna switch unit 121 connected to the antenna 11 distributes the input signal from the antenna 11 to the receiving unit 122 and the output signal from the transmitting unit 123 to the antenna 11.

In the receiving section 122, 1.9 GHz is input from the antenna 11 via the antenna switch section 121.
RF received signal in the band (eg, 1895.15MHz)
A PLL frequency synthesizer 124 that takes in the first stage mixer 1222 via an amplifier 1221 and performs local oscillation.
248. which is input via the buffer amplifier 1229 based on the frequency signal of 248.
Frequency conversion to IF signal of 45MHz, IF amplifier 12
23, and a bandpass filter (BPF) 1
Via the 224 into the second stage mixer 1225,
Oscillation frequency signal of local oscillator 1226 1237.65M
Frequency conversion to 10.8MHz signal based on Hz,
IF amplifier 1227, bandpass filter (BPF) 1
The data is output to the next-stage modem 13 via 228.

On the other hand, in the transmitting section 123, the π / 4 shift QPSK modulated wave signal (23
7.65MHz) with a bandpass filter (BPF) 12
The frequency signal of the PLL frequency synthesizer 124 (16
9.5 GHz band (e.g., 1895.) that is input via the buffer amplifier 1235 based on 57.5 MHz).
15MHz) frequency conversion, drive amplifier 1
The signal is output from the antenna switch unit 121 to the antenna 11 via the power supply amplifier 233 and the power amplifier 1234. At this time, the difference between the local oscillation frequencies of transmission and reception of the PLL frequency synthesizer 124 is 10.8 MHz. The output frequency of the PLL frequency synthesizer 124 is
It depends on the channel.

FIG. 3 shows a schematic structure of the PLL frequency synthesizer 124 used in the high frequency section 12. In this case, in FIG. 3, the same parts as those in FIG.
Shift register 31 for taking in the difference data signal Data ′ according to the frequency difference at the time of reception / transmission from the device according to the clock CLK ′, and the data signal of the difference shift register 31 is divided by the load enable signal LE ′. It has a difference latch 32 that latches as a set value of the frequency, and further has an adder circuit 33 that adds the set values of the latch 5 and the difference latch 32. In the adding circuit 33, whether the addition is possible or not is selected by the control command SW of the CPU 3, the adding operation is performed at the time of transmission, and the adding operation is not performed at the time of reception.

Others are the same as those in FIG. 5, and therefore the description thereof is omitted here. Next, the operation of the embodiment configured as described above will be described. Now, in the call mode of the digital wireless terminal device shown in FIG. 1, when a call signal is inputted from the other party subscriber through the antenna 11, the receiving section 12 of the high frequency section 12
2, the voice is output from the speaker 18 on the receiving side via the modem 13, the TDMA 14, the speech codec 15, and the PCM 16, while the microphone 19 on the transmitting side is output.
When a call signal is further input, it is output from the PCM 16 to the partner subscriber through the speech codec 15, the TDMA 14, the modem 13, and the transmission section 123 of the high frequency section 12 from the antenna 11.

In this case, the receiving unit 1 in the high frequency unit 12
A local oscillation signal is output from the PLL frequency synthesizer 124 to the transmitter 22 and the transmitter 123. Although the transmission / reception frequency is described here as 1895.15 MHz for the sake of explanation, if the channel frequency changes, P
The frequency of the LL frequency synthesizer 124 also changes. In the PLL frequency synthesizer 124 shown in FIG.
The data signal Data (= 5489) corresponding to the channel frequency at the time of reception from the CPU 3 in the control unit 20 is taken into the shift register 4 according to the clock CLK, and the data signal of this shift register 4 is latched by the load enable signal LE. 5, the comparison frequency division number according to the communication channel is set, and the CPU in the control unit 20
The differential data signal Data ′ (= 36) according to the frequency difference at the time of reception / transmission from 3 is taken into the difference shift register 31 according to the clock CLK ′, and the data signal of the difference shift register 31 is load-enabled. Signal LE
'To transfer to the difference latch 32, and the difference frequency division number is set according to the frequency difference at the time of reception / transmission.

From this state, in the above-mentioned communication mode, when a call signal is input from the other party subscriber via the antenna 11, the control operation SW of the CPU 3 blocks the addition operation in the addition circuit 33. Comparison frequency division number (= 548) according to the communication channel set in the latch 5
Only 9) is sent to the comparison frequency divider 6 via the adder circuit 33, and the frequency division number N is set. The frequency division number N sets the signal fvco (= 1657.5MH) of the voltage controlled oscillator (VCO) 7.
A comparison signal fr ′ obtained by dividing z) by N is output.

On the other hand, at the time of transmission in which a call signal is output via the antenna 11, the addition operation in the addition circuit 33 is permitted by the control command SW of the CPU 3, and the comparison component according to the communication channel set in the latch 5 is allowed. The frequency divider (= 5489) and the difference frequency divider (= 36) according to the frequency difference at the time of reception / transmission set in the difference latch 32 are added to the adder circuit 33 and sent to the comparison frequency divider 6. The frequency division number N (= 5525) is set, and the voltage control oscillator (VC
O) 7 signal fvco (1647.7 MHz) is divided by N to output a comparison signal fr '.

The comparison signal fr 'is a reference signal fr (= ftcxo / R = 19.2 MHz / 64 = 300) obtained by dividing the signal ftcxo of the reference signal generator 1 by R in the reference frequency divider 2.
KHz) and the phase comparator 8 perform phase comparison, the error signal is integrated by the loop filter (LPF) 9 to be converted into an error voltage, which is applied to the control terminal of the voltage controlled oscillator (VCO) 7 to set fr. A signal having a constant frequency such that = fr 'is generated as a local oscillation output.

Therefore, in this way, by the control command SW of the CPU 3, the operation of the adder circuit 33 is blocked when the call signal is received, so that the comparison frequency division number according to the communication channel set in the latch 5 is obtained. The frequency division number N of the comparison frequency divider 6 is set only by the addition, and when the call signal is transmitted, the adding circuit 33
By allowing the operation of, the comparison frequency division number according to the communication channel set in the latch 5 and the difference frequency division number according to the frequency difference between reception and transmission set in the difference latch 32 are added. Since the frequency division number N of the comparison frequency divider 6 is set, the comparison frequency division number settings suitable for transmission and reception can be obtained respectively, and the signal of the frequency for local oscillation according to the communication channel is obtained. Will be obtained.

As a result, two types of setting data are prepared for one conventional communication channel, and the comparison frequency division number is set by changing and outputting the data signal each time the transmission / reception state changes. Compared to the ones, the comparison frequency can be set for each of transmission and reception by one type of setting data according to the communication channel, and even if the state of transmission and reception is repeated, it corresponds without changing the data captured in the shift register 4. As a result, the operation load on the CPU can be reduced, and stable circuit operation can be realized.

In the present embodiment, the difference data is added at the time of transmission on the basis of the time of reception. However, the difference data may be subtracted at the time of reception on the basis of time of transmission.

FIG. 4 shows another embodiment of the present invention, in which only the schematic configuration of the PLL frequency synthesizer 124 is shown. In this case, FIG. 4 corresponds to FIG.
The same parts are indicated by the same reference numerals and the difference in frequency between transmission and reception (division difference) is constant due to the system configuration. It has a difference data generating circuit 34 that is generated as a number, and further has an adding circuit 35 that adds the difference data of the latch 5 and the difference data generating circuit 34. Adder circuit 3 here
5, whether or not the addition operation is possible is selected by the control command SW of the CPU 3, and addition is performed at the time of transmission, and addition is not performed at the time of reception.

Others are the same as those in FIG. 5, and therefore the description thereof is omitted here. By doing so, the difference shift register and the difference latch for setting the difference data by the CPU of the above-described embodiment can be omitted, the circuit configuration can be further simplified, and the operation load of the CPU can be further reduced. Therefore, stable circuit operation can be realized.

The present invention is not limited to the above-mentioned embodiments, and can be carried out by appropriately modifying it without changing the gist.
For example, when performing a channel search, the frequency division number data corresponding to the base channel frequency is stored with the difference frequency division number data corresponding to the difference frequency between the base channel frequency and another channel frequency. The channel search to which the present invention is applied can be performed by adding or subtracting the difference frequency division number data to the frequency division number data corresponding to the base channel.

[0037]

As described above, according to the present invention, the comparison frequency division number set in the first frequency division setting means is set as it is or the first frequency division number is set in accordance with the respective states of reception and transmission. It is possible to output a comparison frequency division number obtained by adding the difference frequency division number set in the second frequency division number setting means to the comparison frequency division number set in the means. The comparison frequency can be set for each of transmission and reception by setting data of, and even if the state of transmission and reception is repeated, it can be handled without changing the data, thereby reducing the operation load of the CPU and stable circuit operation. realizable.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic configuration of a digital wireless terminal device adopting a TDD communication method used in an embodiment of the present invention.

FIG. 2 is a diagram showing a schematic configuration of a high frequency unit used in one embodiment.

FIG. 3 is a diagram showing a schematic configuration of a PLL frequency synthesizer used in one embodiment.

FIG. 4 is a diagram showing a schematic configuration of a PLL frequency synthesizer used in another embodiment of the present invention.

FIG. 5 is a diagram showing a schematic configuration of a conventional PLL frequency synthesizer.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Reference signal generator, 2 ... Reference frequency divider, 3 ... CPU, 4 ... Shift register, 5 ... Latch, 6 ... Comparison frequency divider, 7 ... Voltage controlled oscillator (VCO), 8 ... Phase comparator, 9 ... loop filter (LPF), 11 ... antenna, 12 ... high frequency part, 121 ... antenna switch part, 122 ... reception part, 123 ... transmission part, 124 ... PLL frequency synthesizer, 13 ... modem, 14 ... TDMA, 15 ... speech codec , 16 ... PCM, 17 ... Amplifier, 18 ... Receiving side speaker, 19 ... Microphone, 20 ... Control section, 21 ... ROM, 22 ... RAM, 23 ... Recording / reproducing circuit, 24 ... Memory, 25 ... Display section, 26 ... Key Input section. 31 ... Difference shift register, 32 ... Difference latch, 33 ... Adder circuit, 34 ... Difference data generation circuit.

Claims (3)

[Claims] 1. A voltage-controlled oscillator that outputs a predetermined frequency based on a predetermined voltage, a frequency divider that divides a predetermined frequency signal output by the voltage-controlled oscillator by a predetermined frequency division number, and a reference frequency signal that is output. And a phase comparator that compares the phase of the reference frequency signal output from the reference signal oscillator with the frequency-divided signal divided by the frequency divider and outputs a phase difference signal. In a PLL frequency synthesizer for inputting a voltage based on the phase difference signal output from the phase comparator to the voltage controlled oscillator, first frequency division number setting means for setting a frequency division number corresponding to the predetermined frequency signal. A second frequency division number setting means for setting a frequency division number corresponding to a difference frequency signal between the predetermined frequency signal and a different frequency signal; and in a certain state, the first frequency division number setting means Constant has been the frequency division number output to the divider, the other state, the first
And a means for adding or subtracting the frequency division number set in the frequency division number setting means and the frequency division number set in the second frequency division number setting means to output to the frequency divider. Featured PLL frequency synthesizer. 2. A shift register, wherein the second frequency division number setting means captures frequency division number data corresponding to a difference frequency signal between a frequency signal different from the predetermined frequency signal, and a frequency division of the shift register. The PLL frequency synthesizer according to claim 1, further comprising a latch for latching numerical data. 3. The second frequency division number setting means comprises data generation means for generating frequency division number data corresponding to a difference frequency signal between the predetermined frequency signal and a different frequency signal. The PLL frequency synthesizer according to claim 1.